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From: Lokesh Vutla <lokeshvutla@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] board: ti: am57xx: Update EMIF SDRAM 1 and 3 Timings
Date: Mon, 11 Apr 2016 10:49:54 +0530	[thread overview]
Message-ID: <570B33FA.2050808@ti.com> (raw)
In-Reply-To: <1460152424-30181-1-git-send-email-nm@ti.com>



On Saturday 09 April 2016 03:23 AM, Nishanth Menon wrote:
> From: Schuyler Patton <spatton@ti.com>
> 
> Update EMIF data based on recommendations from the now standard TI
> EMIF tool version 1.1.1 based on 256MBx16 DDR3L Kingston D2516EC4BXGGB
> data sheet
> 
> Update T_RRD from 5 to 6 based on AM57xx TRM -
> Minimum number of DDR cycles from activate to ativate for a different
> bank, minus 1.
> 
> Update T_CKESR from 4 to 3 based on AM57xx TRM - Minimum number of DDR
> clocks cycles for which SDRAM must remain in self refresh, minus 1.

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

Thanks and regards,
Lokesh

  reply	other threads:[~2016-04-11  5:19 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-08 21:53 [U-Boot] [PATCH] board: ti: am57xx: Update EMIF SDRAM 1 and 3 Timings Nishanth Menon
2016-04-11  5:19 ` Lokesh Vutla [this message]
2016-04-11 15:00 ` Tom Rini
2016-04-21 11:21 ` [U-Boot] " Tom Rini

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