From mboxrd@z Thu Jan  1 00:00:00 1970
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 11 Apr 2016 10:49:54 +0530
Subject: [U-Boot] [PATCH] board: ti: am57xx: Update EMIF SDRAM 1 and 3
	Timings
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References: <1460152424-30181-1-git-send-email-nm@ti.com>
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On Saturday 09 April 2016 03:23 AM, Nishanth Menon wrote:
> From: Schuyler Patton <spatton@ti.com>
> 
> Update EMIF data based on recommendations from the now standard TI
> EMIF tool version 1.1.1 based on 256MBx16 DDR3L Kingston D2516EC4BXGGB
> data sheet
> 
> Update T_RRD from 5 to 6 based on AM57xx TRM -
> Minimum number of DDR cycles from activate to ativate for a different
> bank, minus 1.
> 
> Update T_CKESR from 4 to 3 based on AM57xx TRM - Minimum number of DDR
> clocks cycles for which SDRAM must remain in self refresh, minus 1.

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

Thanks and regards,
Lokesh