[U-Boot] [PATCH] board: ti: am57xx: Update EMIF SDRAM 1 and 3 Timings

[U-Boot] [PATCH] board: ti: am57xx: Update EMIF SDRAM 1 and 3 Timings

[Nishanth Menon]

From: Schuyler Patton <spatton@ti.com>

Update EMIF data based on recommendations from the now standard TI
EMIF tool version 1.1.1 based on 256MBx16 DDR3L Kingston D2516EC4BXGGB
data sheet

Update T_RRD from 5 to 6 based on AM57xx TRM -
Minimum number of DDR cycles from activate to ativate for a different
bank, minus 1.

Update T_CKESR from 4 to 3 based on AM57xx TRM - Minimum number of DDR
clocks cycles for which SDRAM must remain in self refresh, minus 1.

Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
X15 BOM: 
https://github.com/beagleboard/beagleboard-x15/blob/master/BeagleBoard-X15_RevA2B_BOM.xlsx

AM5728 Data sheet: http://www.ti.com/product/AM5728/datasheet

 board/ti/am57xx/board.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 18416ef64ad9..fda0ed59c6b7 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -131,9 +131,9 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 	.sdram_config2		= 0x08000000,
 	.ref_ctrl		= 0x000040F1,
 	.ref_ctrl_final		= 0x00001035,
-	.sdram_tim1		= 0xcccf36ab,
+	.sdram_tim1		= 0xcccf36b3,
 	.sdram_tim2		= 0x308f7fda,
-	.sdram_tim3		= 0x409f88a8,
+	.sdram_tim3		= 0x407f88a8,
 	.read_idle_ctrl		= 0x00050000,
 	.zq_config		= 0x5007190b,
 	.temp_alert_config	= 0x00000000,
-- 
2.8.0

[U-Boot] [PATCH] board: ti: am57xx: Update EMIF SDRAM 1 and 3 Timings

[Lokesh Vutla]

On Saturday 09 April 2016 03:23 AM, Nishanth Menon wrote:
> From: Schuyler Patton <spatton@ti.com>
> 
> Update EMIF data based on recommendations from the now standard TI
> EMIF tool version 1.1.1 based on 256MBx16 DDR3L Kingston D2516EC4BXGGB
> data sheet
> 
> Update T_RRD from 5 to 6 based on AM57xx TRM -
> Minimum number of DDR cycles from activate to ativate for a different
> bank, minus 1.
> 
> Update T_CKESR from 4 to 3 based on AM57xx TRM - Minimum number of DDR
> clocks cycles for which SDRAM must remain in self refresh, minus 1.

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

Thanks and regards,
Lokesh

[U-Boot] [PATCH] board: ti: am57xx: Update EMIF SDRAM 1 and 3 Timings

[Tom Rini]

On Fri, Apr 08, 2016 at 04:53:44PM -0500, Nishanth Menon wrote:

> From: Schuyler Patton <spatton@ti.com>
> 
> Update EMIF data based on recommendations from the now standard TI
> EMIF tool version 1.1.1 based on 256MBx16 DDR3L Kingston D2516EC4BXGGB
> data sheet
> 
> Update T_RRD from 5 to 6 based on AM57xx TRM -
> Minimum number of DDR cycles from activate to ativate for a different
> bank, minus 1.
> 
> Update T_CKESR from 4 to 3 based on AM57xx TRM - Minimum number of DDR
> clocks cycles for which SDRAM must remain in self refresh, minus 1.
> 
> Signed-off-by: Schuyler Patton <spatton@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] board: ti: am57xx: Update EMIF SDRAM 1 and 3 Timings

[Tom Rini]

On Fri, Apr 08, 2016 at 04:53:44PM -0500, Nishanth Menon wrote:

> From: Schuyler Patton <spatton@ti.com>
> 
> Update EMIF data based on recommendations from the now standard TI
> EMIF tool version 1.1.1 based on 256MBx16 DDR3L Kingston D2516EC4BXGGB
> data sheet
> 
> Update T_RRD from 5 to 6 based on AM57xx TRM -
> Minimum number of DDR cycles from activate to ativate for a different
> bank, minus 1.
> 
> Update T_CKESR from 4 to 3 based on AM57xx TRM - Minimum number of DDR
> clocks cycles for which SDRAM must remain in self refresh, minus 1.
> 
> Signed-off-by: Schuyler Patton <spatton@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!

-- 
Tom
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