From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dinh Nguyen Date: Tue, 12 Apr 2016 08:54:58 -0500 Subject: [U-Boot] FPGA detection failure on Cyclone V soc development kit In-Reply-To: <57056347.8070901@denx.de> References: <20160121161800.GZ3359@bill-the-cat> <201601211731.07808.marex@denx.de> <56A25A57.5080707@opensource.altera.com> <1453901681.2348.20.camel@altera.com> <1453904178.2016.2.camel@altera.com> <5705264B.8000508@gmail.com> <57053DC6.8050804@denx.de> <57056347.8070901@denx.de> Message-ID: <570CFE32.4090606@opensource.altera.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 04/06/2016 02:28 PM, Marek Vasut wrote: > On 04/06/2016 07:16 PM, M?ns Rullg?rd wrote: >> Marek Vasut writes: >> >>> On 04/06/2016 05:29 PM, Dinh Nguyen wrote: >>>> On Wed, Apr 6, 2016 at 10:07 AM, Marek Vasut wrote: >>>>> >>>>> I pushed some DDR fixes into u-boot-socfpga/ddr branch [1], which fixed >>>>> DDR calibration issue on a board I have in here. Can you try them ? Thanks >>>>> >>>>> [1] >>>>> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/ddr >>>>> >>>> >>>> I'll do it first thing when I get back from ELC. >>> >>> Cool. I will do proper submission by then. I think Mans had a CV SoCDK >>> which didn't boot with the mainline SPL, so it'd be cool if he could try. >> >> I will when I get back from ELC. I tested your branch on an DE0-NANO(Atlas) board, and everything looks great! Dinh