[U-Boot] FPGA detection failure on Cyclone V soc development kit

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Måns Rullgård]

I'm having a problem with u-boot 2016.01 failing to detect the FPGA on
my Altera Cyclone V SoC Development Kit.  On startup, it simply prints
"FPGA: Not Altera chip ID" (the ID having been read as all-zero).  No
amount of messing with jumpers or switches makes a difference.  The
software on the SD card included in the box appears to work, so on a
whim I took the SPL pre-loader from this card and combined it with the
main 2016.01 u-boot.  This makes the detection succeed, despite Marek
baulking at this idea.  The "good" SPL identifies as "U-Boot SPL
2013.01.01 (Dec 04 2014 - 08:59:41)" which is a different build date
than the main u-boot on the same SD card, so which source code version
it was built from is anyone's guess.

What's interesting is that Marek's board works with u-boot 2016.01 while
mine fails even with the very same binary.  The boards are different
revisions (his 100-0321003-C1, mine -E1), and the main Cyclone V chips
are also different (his 5CSXFC6D6F31C8NES, mine 5CSXFC6D6F31C6N).

Any suggestions for what to try next?

-- 
M?ns Rullg?rd

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Tom Rini]

On Wed, Jan 20, 2016 at 08:31:30PM +0000, M?ns Rullg?rd wrote:

> I'm having a problem with u-boot 2016.01 failing to detect the FPGA on
> my Altera Cyclone V SoC Development Kit.  On startup, it simply prints
> "FPGA: Not Altera chip ID" (the ID having been read as all-zero).  No
> amount of messing with jumpers or switches makes a difference.  The
> software on the SD card included in the box appears to work, so on a
> whim I took the SPL pre-loader from this card and combined it with the
> main 2016.01 u-boot.  This makes the detection succeed, despite Marek
> baulking at this idea.  The "good" SPL identifies as "U-Boot SPL
> 2013.01.01 (Dec 04 2014 - 08:59:41)" which is a different build date
> than the main u-boot on the same SD card, so which source code version
> it was built from is anyone's guess.
> 
> What's interesting is that Marek's board works with u-boot 2016.01 while
> mine fails even with the very same binary.  The boards are different
> revisions (his 100-0321003-C1, mine -E1), and the main Cyclone V chips
> are also different (his 5CSXFC6D6F31C8NES, mine 5CSXFC6D6F31C6N).
> 
> Any suggestions for what to try next?

v2016.01 release or to of tree?  If top of tree, try
http://patchwork.ozlabs.org/patch/570009/

-- 
Tom
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[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Måns Rullgård]

Tom Rini <trini@konsulko.com> writes:

> On Wed, Jan 20, 2016 at 08:31:30PM +0000, M?ns Rullg?rd wrote:
>
>> I'm having a problem with u-boot 2016.01 failing to detect the FPGA on
>> my Altera Cyclone V SoC Development Kit.  On startup, it simply prints
>> "FPGA: Not Altera chip ID" (the ID having been read as all-zero).  No
>> amount of messing with jumpers or switches makes a difference.  The
>> software on the SD card included in the box appears to work, so on a
>> whim I took the SPL pre-loader from this card and combined it with the
>> main 2016.01 u-boot.  This makes the detection succeed, despite Marek
>> baulking at this idea.  The "good" SPL identifies as "U-Boot SPL
>> 2013.01.01 (Dec 04 2014 - 08:59:41)" which is a different build date
>> than the main u-boot on the same SD card, so which source code version
>> it was built from is anyone's guess.
>> 
>> What's interesting is that Marek's board works with u-boot 2016.01 while
>> mine fails even with the very same binary.  The boards are different
>> revisions (his 100-0321003-C1, mine -E1), and the main Cyclone V chips
>> are also different (his 5CSXFC6D6F31C8NES, mine 5CSXFC6D6F31C6N).
>> 
>> Any suggestions for what to try next?
>
> v2016.01 release or to of tree?  If top of tree, try
> http://patchwork.ozlabs.org/patch/570009/

Tried release, top of tree, and top of tree with that patch.  Nothing
works.

-- 
M?ns Rullg?rd

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Marek Vasut]

On Thursday, January 21, 2016 at 05:20:33 PM, M?ns Rullg?rd wrote:
> Tom Rini <trini@konsulko.com> writes:
> > On Wed, Jan 20, 2016 at 08:31:30PM +0000, M?ns Rullg?rd wrote:
> >> I'm having a problem with u-boot 2016.01 failing to detect the FPGA on
> >> my Altera Cyclone V SoC Development Kit.  On startup, it simply prints
> >> "FPGA: Not Altera chip ID" (the ID having been read as all-zero).  No
> >> amount of messing with jumpers or switches makes a difference.  The
> >> software on the SD card included in the box appears to work, so on a
> >> whim I took the SPL pre-loader from this card and combined it with the
> >> main 2016.01 u-boot.  This makes the detection succeed, despite Marek
> >> baulking at this idea.  The "good" SPL identifies as "U-Boot SPL
> >> 2013.01.01 (Dec 04 2014 - 08:59:41)" which is a different build date
> >> than the main u-boot on the same SD card, so which source code version
> >> it was built from is anyone's guess.
> >> 
> >> What's interesting is that Marek's board works with u-boot 2016.01 while
> >> mine fails even with the very same binary.  The boards are different
> >> revisions (his 100-0321003-C1, mine -E1), and the main Cyclone V chips
> >> are also different (his 5CSXFC6D6F31C8NES, mine 5CSXFC6D6F31C6N).
> >> 
> >> Any suggestions for what to try next?
> > 
> > v2016.01 release or to of tree?  If top of tree, try
> > http://patchwork.ozlabs.org/patch/570009/
> 
> Tried release, top of tree, and top of tree with that patch.  Nothing
> works.

btw. you dropped Dinh from the CC .

Best regards,
Marek Vasut

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Dinh Nguyen]

On 01/21/2016 10:31 AM, Marek Vasut wrote:
> On Thursday, January 21, 2016 at 05:20:33 PM, M?ns Rullg?rd wrote:
>> Tom Rini <trini@konsulko.com> writes:
>>> On Wed, Jan 20, 2016 at 08:31:30PM +0000, M?ns Rullg?rd wrote:
>>>> I'm having a problem with u-boot 2016.01 failing to detect the FPGA on
>>>> my Altera Cyclone V SoC Development Kit.  On startup, it simply prints
>>>> "FPGA: Not Altera chip ID" (the ID having been read as all-zero).  No
>>>> amount of messing with jumpers or switches makes a difference.  The
>>>> software on the SD card included in the box appears to work, so on a
>>>> whim I took the SPL pre-loader from this card and combined it with the
>>>> main 2016.01 u-boot.  This makes the detection succeed, despite Marek
>>>> baulking at this idea.  The "good" SPL identifies as "U-Boot SPL
>>>> 2013.01.01 (Dec 04 2014 - 08:59:41)" which is a different build date
>>>> than the main u-boot on the same SD card, so which source code version
>>>> it was built from is anyone's guess.
>>>>
>>>> What's interesting is that Marek's board works with u-boot 2016.01 while
>>>> mine fails even with the very same binary.  The boards are different
>>>> revisions (his 100-0321003-C1, mine -E1), and the main Cyclone V chips
>>>> are also different (his 5CSXFC6D6F31C8NES, mine 5CSXFC6D6F31C6N).
>>>>
>>>> Any suggestions for what to try next?
>>>
>>> v2016.01 release or to of tree?  If top of tree, try
>>> http://patchwork.ozlabs.org/patch/570009/
>>
>> Tried release, top of tree, and top of tree with that patch.  Nothing
>> works.
> 
> btw. you dropped Dinh from the CC .
> 

Sorry, but I haven't had a chance to take a look at this. I'll try to
looking this in the following week.

Dinh

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Chin Liang See]

On Fri, 2016-01-22 at 10:35 -0600, Dinh Nguyen wrote:
> On 01/21/2016 10:31 AM, Marek Vasut wrote:
> > On Thursday, January 21, 2016 at 05:20:33 PM, M?ns Rullg?rd wrote:
> > > Tom Rini <trini@konsulko.com> writes:
> > > > On Wed, Jan 20, 2016 at 08:31:30PM +0000, M?ns Rullg?rd wrote:
> > > > > I'm having a problem with u-boot 2016.01 failing to detect
> > > > > the FPGA on
> > > > > my Altera Cyclone V SoC Development Kit.  On startup, it
> > > > > simply prints
> > > > > "FPGA: Not Altera chip ID" (the ID having been read as all
> > > > > -zero).  No
> > > > > amount of messing with jumpers or switches makes a
> > > > > difference.  The
> > > > > software on the SD card included in the box appears to work,
> > > > > so on a
> > > > > whim I took the SPL pre-loader from this card and combined it
> > > > > with the
> > > > > main 2016.01 u-boot.  This makes the detection succeed,
> > > > > despite Marek
> > > > > baulking at this idea.  The "good" SPL identifies as "U-Boot
> > > > > SPL
> > > > > 2013.01.01 (Dec 04 2014 - 08:59:41)" which is a different
> > > > > build date
> > > > > than the main u-boot on the same SD card, so which source
> > > > > code version
> > > > > it was built from is anyone's guess.
> > > > > 
> > > > > What's interesting is that Marek's board works with u-boot
> > > > > 2016.01 while
> > > > > mine fails even with the very same binary.  The boards are
> > > > > different
> > > > > revisions (his 100-0321003-C1, mine -E1), and the main
> > > > > Cyclone V chips
> > > > > are also different (his 5CSXFC6D6F31C8NES, mine
> > > > > 5CSXFC6D6F31C6N).
> > > > > 
> > > > > Any suggestions for what to try next?
> > > > 
> > > > v2016.01 release or to of tree?  If top of tree, try
> > > > http://patchwork.ozlabs.org/patch/570009/
> > > 
> > > Tried release, top of tree, and top of tree with that patch. 
> > >  Nothing
> > > works.

Both part number is different in speed grade. This is first time I
heard about this issue. A quick suspect might due to clock. Can you try
to copy pll_config.h that is passing (from 2013.01.01) and replace the
one in 2016?

Thanks
Chin Liang

> > 
> > btw. you dropped Dinh from the CC .
> > 
> 
> Sorry, but I haven't had a chance to take a look at this. I'll try to
> looking this in the following week.
> 
> Dinh
> 

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Måns Rullgård]

Chin Liang See <clsee@altera.com> writes:

> On Fri, 2016-01-22 at 10:35 -0600, Dinh Nguyen wrote:
>> On 01/21/2016 10:31 AM, Marek Vasut wrote:
>> > On Thursday, January 21, 2016 at 05:20:33 PM, M?ns Rullg?rd wrote:
>> > > Tom Rini <trini@konsulko.com> writes:
>> > > > On Wed, Jan 20, 2016 at 08:31:30PM +0000, M?ns Rullg?rd wrote:
>> > > > > I'm having a problem with u-boot 2016.01 failing to detect
>> > > > > the FPGA on my Altera Cyclone V SoC Development Kit.  On
>> > > > > startup, it simply prints "FPGA: Not Altera chip ID" (the ID
>> > > > > having been read as all -zero).  No amount of messing with
>> > > > > jumpers or switches makes a difference.  The software on the
>> > > > > SD card included in the box appears to work, so on a whim I
>> > > > > took the SPL pre-loader from this card and combined it with
>> > > > > the main 2016.01 u-boot.  This makes the detection succeed,
>> > > > > despite Marek baulking at this idea.  The "good" SPL
>> > > > > identifies as "U-Boot SPL 2013.01.01 (Dec 04 2014 -
>> > > > > 08:59:41)" which is a different build date than the main
>> > > > > u-boot on the same SD card, so which source code version it
>> > > > > was built from is anyone's guess.
>> > > > > 
>> > > > > What's interesting is that Marek's board works with u-boot
>> > > > > 2016.01 while mine fails even with the very same binary.
>> > > > > The boards are different revisions (his 100-0321003-C1, mine
>> > > > > -E1), and the main Cyclone V chips are also different (his
>> > > > > 5CSXFC6D6F31C8NES, mine 5CSXFC6D6F31C6N).
>> > > > > 
>> > > > > Any suggestions for what to try next?
>> > > >  v2016.01 release or to of tree?  If top of tree, try
>> > > > http://patchwork.ozlabs.org/patch/570009/
>> > >  Tried release, top of tree, and top of tree with that patch.
>> > > Nothing works.
>
> Both part number is different in speed grade. This is first time I
> heard about this issue. A quick suspect might due to clock. Can you
> try to copy pll_config.h that is passing (from 2013.01.01) and replace
> the one in 2016?

That doesn't work at all.  Now it fails to detect the FPGA, then hangs
after printing the amount of DRAM.

-- 
M?ns Rullg?rd

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Chin Liang See]

On Wed, 2016-01-27 at 13:46 +0000, M?ns Rullg?rd wrote:
> Chin Liang See <clsee@altera.com> writes:
> 
> > On Fri, 2016-01-22 at 10:35 -0600, Dinh Nguyen wrote:
> > > On 01/21/2016 10:31 AM, Marek Vasut wrote:
> > > > On Thursday, January 21, 2016 at 05:20:33 PM, M?ns Rullg?rd
> > > > wrote:
> > > > > Tom Rini <trini@konsulko.com> writes:
> > > > > > On Wed, Jan 20, 2016 at 08:31:30PM +0000, M?ns Rullg?rd
> > > > > > wrote:
> > > > > > > I'm having a problem with u-boot 2016.01 failing to
> > > > > > > detect
> > > > > > > the FPGA on my Altera Cyclone V SoC Development Kit.  On
> > > > > > > startup, it simply prints "FPGA: Not Altera chip ID" (the
> > > > > > > ID
> > > > > > > having been read as all -zero).  No amount of messing
> > > > > > > with
> > > > > > > jumpers or switches makes a difference.  The software on
> > > > > > > the
> > > > > > > SD card included in the box appears to work, so on a whim
> > > > > > > I
> > > > > > > took the SPL pre-loader from this card and combined it
> > > > > > > with
> > > > > > > the main 2016.01 u-boot.  This makes the detection
> > > > > > > succeed,
> > > > > > > despite Marek baulking at this idea.  The "good" SPL
> > > > > > > identifies as "U-Boot SPL 2013.01.01 (Dec 04 2014 -
> > > > > > > 08:59:41)" which is a different build date than the main
> > > > > > > u-boot on the same SD card, so which source code version
> > > > > > > it
> > > > > > > was built from is anyone's guess.
> > > > > > > 
> > > > > > > What's interesting is that Marek's board works with u
> > > > > > > -boot
> > > > > > > 2016.01 while mine fails even with the very same binary.
> > > > > > > The boards are different revisions (his 100-0321003-C1,
> > > > > > > mine
> > > > > > > -E1), and the main Cyclone V chips are also different
> > > > > > > (his
> > > > > > > 5CSXFC6D6F31C8NES, mine 5CSXFC6D6F31C6N).
> > > > > > > 
> > > > > > > Any suggestions for what to try next?
> > > > > >  v2016.01 release or to of tree?  If top of tree, try
> > > > > > http://patchwork.ozlabs.org/patch/570009/
> > > > >  Tried release, top of tree, and top of tree with that patch.
> > > > > Nothing works.
> > 
> > Both part number is different in speed grade. This is first time I
> > heard about this issue. A quick suspect might due to clock. Can you
> > try to copy pll_config.h that is passing (from 2013.01.01) and
> > replace
> > the one in 2016?
> 
> That doesn't work at all.  Now it fails to detect the FPGA, then
> hangs
> after printing the amount of DRAM.

Can you share with me the pll_config for 2013.01.01 that is working for
you? We would want to lower down the clock supplied to Scan Manager
which spi_m_clk and see whether that helps.

Thanks
Chin Liang



> 

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Måns Rullgård]

Chin Liang See <clsee@altera.com> writes:

> On Wed, 2016-01-27 at 13:46 +0000, M?ns Rullg?rd wrote:
>> Chin Liang See <clsee@altera.com> writes:
>> 
>> > On Fri, 2016-01-22 at 10:35 -0600, Dinh Nguyen wrote:
>> > > On 01/21/2016 10:31 AM, Marek Vasut wrote:
>> > > > On Thursday, January 21, 2016 at 05:20:33 PM, M?ns Rullg?rd
>> > > > wrote:
>> > > > > Tom Rini <trini@konsulko.com> writes:
>> > > > > > On Wed, Jan 20, 2016 at 08:31:30PM +0000, M?ns Rullg?rd
>> > > > > > wrote:
>> > > > > > > I'm having a problem with u-boot 2016.01 failing to
>> > > > > > > detect the FPGA on my Altera Cyclone V SoC Development
>> > > > > > > Kit.  On startup, it simply prints "FPGA: Not Altera chip
>> > > > > > > ID" (the ID having been read as all -zero).  No amount of
>> > > > > > > messing with jumpers or switches makes a difference.  The
>> > > > > > > software on the SD card included in the box appears to
>> > > > > > > work, so on a whim I took the SPL pre-loader from this
>> > > > > > > card and combined it with the main 2016.01 u-boot.  This
>> > > > > > > makes the detection succeed, despite Marek baulking at
>> > > > > > > this idea.  The "good" SPL identifies as "U-Boot SPL
>> > > > > > > 2013.01.01 (Dec 04 2014 - 08:59:41)" which is a different
>> > > > > > > build date than the main u-boot on the same SD card, so
>> > > > > > > which source code version it was built from is anyone's
>> > > > > > > guess.
>> > > > > > > 
>> > > > > > > What's interesting is that Marek's board works with u
>> > > > > > > -boot 2016.01 while mine fails even with the very same
>> > > > > > > binary.  The boards are different revisions (his
>> > > > > > > 100-0321003-C1, mine -E1), and the main Cyclone V chips
>> > > > > > > are also different (his 5CSXFC6D6F31C8NES, mine
>> > > > > > > 5CSXFC6D6F31C6N).
>> > > > > > > 
>> > > > > > > Any suggestions for what to try next?
>> > > > > >  v2016.01 release or to of tree?  If top of tree, try
>> > > > > > http://patchwork.ozlabs.org/patch/570009/
>> > > > >  Tried release, top of tree, and top of tree with that patch.
>> > > > > Nothing works.
>> > 
>> > Both part number is different in speed grade. This is first time I
>> > heard about this issue. A quick suspect might due to clock. Can you
>> > try to copy pll_config.h that is passing (from 2013.01.01) and
>> > replace
>> > the one in 2016?
>> 
>> That doesn't work at all.  Now it fails to detect the FPGA, then
>> hangs after printing the amount of DRAM.
>
> Can you share with me the pll_config for 2013.01.01 that is working for
> you?

I don't know that it is.  The only thing I've found to work is the
unidentified SPL on the SD card that came with the dev kit.

-- 
M?ns Rullg?rd

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Chin Liang See]

On Wed, 2016-01-27 at 14:18 +0000, M?ns Rullg?rd wrote:
> Chin Liang See <clsee@altera.com> writes:
> 
> > On Wed, 2016-01-27 at 13:46 +0000, M?ns Rullg?rd wrote:
> > > Chin Liang See <clsee@altera.com> writes:
> > > 
> > > > On Fri, 2016-01-22 at 10:35 -0600, Dinh Nguyen wrote:
> > > > > On 01/21/2016 10:31 AM, Marek Vasut wrote:
> > > > > > On Thursday, January 21, 2016 at 05:20:33 PM, M?ns Rullg?rd
> > > > > > wrote:
> > > > > > > Tom Rini <trini@konsulko.com> writes:
> > > > > > > > On Wed, Jan 20, 2016 at 08:31:30PM +0000, M?ns Rullg?rd
> > > > > > > > wrote:
> > > > > > > > > I'm having a problem with u-boot 2016.01 failing to
> > > > > > > > > detect the FPGA on my Altera Cyclone V SoC
> > > > > > > > > Development
> > > > > > > > > Kit.  On startup, it simply prints "FPGA: Not Altera
> > > > > > > > > chip
> > > > > > > > > ID" (the ID having been read as all -zero).  No
> > > > > > > > > amount of
> > > > > > > > > messing with jumpers or switches makes a difference. 
> > > > > > > > >  The
> > > > > > > > > software on the SD card included in the box appears
> > > > > > > > > to
> > > > > > > > > work, so on a whim I took the SPL pre-loader from
> > > > > > > > > this
> > > > > > > > > card and combined it with the main 2016.01 u-boot. 
> > > > > > > > >  This
> > > > > > > > > makes the detection succeed, despite Marek baulking
> > > > > > > > > at
> > > > > > > > > this idea.  The "good" SPL identifies as "U-Boot SPL
> > > > > > > > > 2013.01.01 (Dec 04 2014 - 08:59:41)" which is a
> > > > > > > > > different
> > > > > > > > > build date than the main u-boot on the same SD card,
> > > > > > > > > so
> > > > > > > > > which source code version it was built from is
> > > > > > > > > anyone's
> > > > > > > > > guess.
> > > > > > > > > 
> > > > > > > > > What's interesting is that Marek's board works with u
> > > > > > > > > -boot 2016.01 while mine fails even with the very
> > > > > > > > > same
> > > > > > > > > binary.  The boards are different revisions (his
> > > > > > > > > 100-0321003-C1, mine -E1), and the main Cyclone V
> > > > > > > > > chips
> > > > > > > > > are also different (his 5CSXFC6D6F31C8NES, mine
> > > > > > > > > 5CSXFC6D6F31C6N).
> > > > > > > > > 
> > > > > > > > > Any suggestions for what to try next?
> > > > > > > >  v2016.01 release or to of tree?  If top of tree, try
> > > > > > > > http://patchwork.ozlabs.org/patch/570009/
> > > > > > >  Tried release, top of tree, and top of tree with that
> > > > > > > patch.
> > > > > > > Nothing works.
> > > > 
> > > > Both part number is different in speed grade. This is first
> > > > time I
> > > > heard about this issue. A quick suspect might due to clock. Can
> > > > you
> > > > try to copy pll_config.h that is passing (from 2013.01.01) and
> > > > replace
> > > > the one in 2016?
> > > 
> > > That doesn't work at all.  Now it fails to detect the FPGA, then
> > > hangs after printing the amount of DRAM.
> > 
> > Can you share with me the pll_config for 2013.01.01 that is working
> > for
> > you?
> 
> I don't know that it is.  The only thing I've found to work is the
> unidentified SPL on the SD card that came with the dev kit.

Oh ok, that mean no modification from your side. Let me take a look
then on the pll_config. 

> 

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Marek Vasut]

On 01/27/2016 03:18 PM, M?ns Rullg?rd wrote:
> Chin Liang See <clsee@altera.com> writes:
> 
>> On Wed, 2016-01-27 at 13:46 +0000, M?ns Rullg?rd wrote:
>>> Chin Liang See <clsee@altera.com> writes:
>>>
>>>> On Fri, 2016-01-22 at 10:35 -0600, Dinh Nguyen wrote:
>>>>> On 01/21/2016 10:31 AM, Marek Vasut wrote:
>>>>>> On Thursday, January 21, 2016 at 05:20:33 PM, M?ns Rullg?rd
>>>>>> wrote:
>>>>>>> Tom Rini <trini@konsulko.com> writes:
>>>>>>>> On Wed, Jan 20, 2016 at 08:31:30PM +0000, M?ns Rullg?rd
>>>>>>>> wrote:
>>>>>>>>> I'm having a problem with u-boot 2016.01 failing to
>>>>>>>>> detect the FPGA on my Altera Cyclone V SoC Development
>>>>>>>>> Kit.  On startup, it simply prints "FPGA: Not Altera chip
>>>>>>>>> ID" (the ID having been read as all -zero).  No amount of
>>>>>>>>> messing with jumpers or switches makes a difference.  The
>>>>>>>>> software on the SD card included in the box appears to
>>>>>>>>> work, so on a whim I took the SPL pre-loader from this
>>>>>>>>> card and combined it with the main 2016.01 u-boot.  This
>>>>>>>>> makes the detection succeed, despite Marek baulking at
>>>>>>>>> this idea.  The "good" SPL identifies as "U-Boot SPL
>>>>>>>>> 2013.01.01 (Dec 04 2014 - 08:59:41)" which is a different
>>>>>>>>> build date than the main u-boot on the same SD card, so
>>>>>>>>> which source code version it was built from is anyone's
>>>>>>>>> guess.
>>>>>>>>>
>>>>>>>>> What's interesting is that Marek's board works with u
>>>>>>>>> -boot 2016.01 while mine fails even with the very same
>>>>>>>>> binary.  The boards are different revisions (his
>>>>>>>>> 100-0321003-C1, mine -E1), and the main Cyclone V chips
>>>>>>>>> are also different (his 5CSXFC6D6F31C8NES, mine
>>>>>>>>> 5CSXFC6D6F31C6N).
>>>>>>>>>
>>>>>>>>> Any suggestions for what to try next?
>>>>>>>>  v2016.01 release or to of tree?  If top of tree, try
>>>>>>>> http://patchwork.ozlabs.org/patch/570009/
>>>>>>>  Tried release, top of tree, and top of tree with that patch.
>>>>>>> Nothing works.
>>>>
>>>> Both part number is different in speed grade. This is first time I
>>>> heard about this issue. A quick suspect might due to clock. Can you
>>>> try to copy pll_config.h that is passing (from 2013.01.01) and
>>>> replace
>>>> the one in 2016?
>>>
>>> That doesn't work at all.  Now it fails to detect the FPGA, then
>>> hangs after printing the amount of DRAM.
>>
>> Can you share with me the pll_config for 2013.01.01 that is working for
>> you?
> 
> I don't know that it is.  The only thing I've found to work is the
> unidentified SPL on the SD card that came with the dev kit.

I pushed some DDR fixes into u-boot-socfpga/ddr branch [1], which fixed
DDR calibration issue on a board I have in here. Can you try them ? Thanks

[1]
http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/ddr

-- 
Best regards,
Marek Vasut

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Dinh Nguyen]

On Wed, Apr 6, 2016 at 10:07 AM, Marek Vasut <marek.vasut@gmail.com> wrote:
>
> I pushed some DDR fixes into u-boot-socfpga/ddr branch [1], which fixed
> DDR calibration issue on a board I have in here. Can you try them ? Thanks
>
> [1]
> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/ddr
>

I'll do it first thing when I get back from ELC.

Thanks,
Dinh

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Marek Vasut]

On 04/06/2016 05:29 PM, Dinh Nguyen wrote:
> On Wed, Apr 6, 2016 at 10:07 AM, Marek Vasut <marek.vasut@gmail.com> wrote:
>>
>> I pushed some DDR fixes into u-boot-socfpga/ddr branch [1], which fixed
>> DDR calibration issue on a board I have in here. Can you try them ? Thanks
>>
>> [1]
>> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/ddr
>>
> 
> I'll do it first thing when I get back from ELC.

Cool. I will do proper submission by then. I think Mans had a CV SoCDK
which didn't boot with the mainline SPL, so it'd be cool if he could try.

btw. I regret not being able to go to ELC quite a lot :'-(

-- 
Best regards,
Marek Vasut

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Måns Rullgård]

Marek Vasut <marex@denx.de> writes:

> On 04/06/2016 05:29 PM, Dinh Nguyen wrote:
>> On Wed, Apr 6, 2016 at 10:07 AM, Marek Vasut <marek.vasut@gmail.com> wrote:
>>>
>>> I pushed some DDR fixes into u-boot-socfpga/ddr branch [1], which fixed
>>> DDR calibration issue on a board I have in here. Can you try them ? Thanks
>>>
>>> [1]
>>> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/ddr
>>>
>> 
>> I'll do it first thing when I get back from ELC.
>
> Cool. I will do proper submission by then. I think Mans had a CV SoCDK
> which didn't boot with the mainline SPL, so it'd be cool if he could try.

I will when I get back from ELC.

-- 
M?ns Rullg?rd

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Marek Vasut]

On 04/06/2016 07:16 PM, M?ns Rullg?rd wrote:
> Marek Vasut <marex@denx.de> writes:
> 
>> On 04/06/2016 05:29 PM, Dinh Nguyen wrote:
>>> On Wed, Apr 6, 2016 at 10:07 AM, Marek Vasut <marek.vasut@gmail.com> wrote:
>>>>
>>>> I pushed some DDR fixes into u-boot-socfpga/ddr branch [1], which fixed
>>>> DDR calibration issue on a board I have in here. Can you try them ? Thanks
>>>>
>>>> [1]
>>>> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/ddr
>>>>
>>>
>>> I'll do it first thing when I get back from ELC.
>>
>> Cool. I will do proper submission by then. I think Mans had a CV SoCDK
>> which didn't boot with the mainline SPL, so it'd be cool if he could try.
> 
> I will when I get back from ELC.
> 
Thanks

-- 
Best regards,
Marek Vasut

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Dinh Nguyen]

On 04/06/2016 02:28 PM, Marek Vasut wrote:
> On 04/06/2016 07:16 PM, M?ns Rullg?rd wrote:
>> Marek Vasut <marex@denx.de> writes:
>>
>>> On 04/06/2016 05:29 PM, Dinh Nguyen wrote:
>>>> On Wed, Apr 6, 2016 at 10:07 AM, Marek Vasut <marek.vasut@gmail.com> wrote:
>>>>>
>>>>> I pushed some DDR fixes into u-boot-socfpga/ddr branch [1], which fixed
>>>>> DDR calibration issue on a board I have in here. Can you try them ? Thanks
>>>>>
>>>>> [1]
>>>>> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/ddr
>>>>>
>>>>
>>>> I'll do it first thing when I get back from ELC.
>>>
>>> Cool. I will do proper submission by then. I think Mans had a CV SoCDK
>>> which didn't boot with the mainline SPL, so it'd be cool if he could try.
>>
>> I will when I get back from ELC.

I tested your branch on an DE0-NANO(Atlas) board, and everything looks
great!

Dinh

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Marek Vasut]

On 04/12/2016 03:54 PM, Dinh Nguyen wrote:
> 
> 
> On 04/06/2016 02:28 PM, Marek Vasut wrote:
>> On 04/06/2016 07:16 PM, M?ns Rullg?rd wrote:
>>> Marek Vasut <marex@denx.de> writes:
>>>
>>>> On 04/06/2016 05:29 PM, Dinh Nguyen wrote:
>>>>> On Wed, Apr 6, 2016 at 10:07 AM, Marek Vasut <marek.vasut@gmail.com> wrote:
>>>>>>
>>>>>> I pushed some DDR fixes into u-boot-socfpga/ddr branch [1], which fixed
>>>>>> DDR calibration issue on a board I have in here. Can you try them ? Thanks
>>>>>>
>>>>>> [1]
>>>>>> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/ddr
>>>>>>
>>>>>
>>>>> I'll do it first thing when I get back from ELC.
>>>>
>>>> Cool. I will do proper submission by then. I think Mans had a CV SoCDK
>>>> which didn't boot with the mainline SPL, so it'd be cool if he could try.
>>>
>>> I will when I get back from ELC.
> 
> I tested your branch on an DE0-NANO(Atlas) board, and everything looks
> great!

High-five ! I'm applying those patches then ? :)

-- 
Best regards,
Marek Vasut

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Dinh Nguyen]

On 04/12/2016 09:00 AM, Marek Vasut wrote:
>>
>> I tested your branch on an DE0-NANO(Atlas) board, and everything looks
>> great!
> 
> High-five ! I'm applying those patches then ? :)
> 

Sure. Thanks,

Dinh

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Marek Vasut]

On 04/12/2016 04:17 PM, Dinh Nguyen wrote:
> 
> 
> On 04/12/2016 09:00 AM, Marek Vasut wrote:
>>>
>>> I tested your branch on an DE0-NANO(Atlas) board, and everything looks
>>> great!
>>
>> High-five ! I'm applying those patches then ? :)
>>
> 
> Sure. Thanks,

OK, done, thanks! The fixes will land in 2016.05-rc2 .

-- 
Best regards,
Marek Vasut

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Phil Reid]

On 6/04/2016 11:07 PM, Marek Vasut wrote:
> On 01/27/2016 03:18 PM, M?ns Rullg?rd wrote:
>> Chin Liang See <clsee@altera.com> writes:
>>
>>> On Wed, 2016-01-27 at 13:46 +0000, M?ns Rullg?rd wrote:
>>>> Chin Liang See <clsee@altera.com> writes:
>>>>
>>>>> On Fri, 2016-01-22 at 10:35 -0600, Dinh Nguyen wrote:
>>>>>> On 01/21/2016 10:31 AM, Marek Vasut wrote:
>>>>>>> On Thursday, January 21, 2016 at 05:20:33 PM, M?ns Rullg?rd
>>>>>>> wrote:
>>>>>>>> Tom Rini <trini@konsulko.com> writes:
>>>>>>>>> On Wed, Jan 20, 2016 at 08:31:30PM +0000, M?ns Rullg?rd
>>>>>>>>> wrote:
>>>>>>>>>> I'm having a problem with u-boot 2016.01 failing to
>>>>>>>>>> detect the FPGA on my Altera Cyclone V SoC Development
>>>>>>>>>> Kit.  On startup, it simply prints "FPGA: Not Altera chip
>>>>>>>>>> ID" (the ID having been read as all -zero).  No amount of
>>>>>>>>>> messing with jumpers or switches makes a difference.  The
>>>>>>>>>> software on the SD card included in the box appears to
>>>>>>>>>> work, so on a whim I took the SPL pre-loader from this
>>>>>>>>>> card and combined it with the main 2016.01 u-boot.  This
>>>>>>>>>> makes the detection succeed, despite Marek baulking at
>>>>>>>>>> this idea.  The "good" SPL identifies as "U-Boot SPL
>>>>>>>>>> 2013.01.01 (Dec 04 2014 - 08:59:41)" which is a different
>>>>>>>>>> build date than the main u-boot on the same SD card, so
>>>>>>>>>> which source code version it was built from is anyone's
>>>>>>>>>> guess.
>>>>>>>>>>
>>>>>>>>>> What's interesting is that Marek's board works with u
>>>>>>>>>> -boot 2016.01 while mine fails even with the very same
>>>>>>>>>> binary.  The boards are different revisions (his
>>>>>>>>>> 100-0321003-C1, mine -E1), and the main Cyclone V chips
>>>>>>>>>> are also different (his 5CSXFC6D6F31C8NES, mine
>>>>>>>>>> 5CSXFC6D6F31C6N).
>>>>>>>>>>
>>>>>>>>>> Any suggestions for what to try next?
>>>>>>>>>   v2016.01 release or to of tree?  If top of tree, try
>>>>>>>>> http://patchwork.ozlabs.org/patch/570009/
>>>>>>>>   Tried release, top of tree, and top of tree with that patch.
>>>>>>>> Nothing works.
>>>>>
>>>>> Both part number is different in speed grade. This is first time I
>>>>> heard about this issue. A quick suspect might due to clock. Can you
>>>>> try to copy pll_config.h that is passing (from 2013.01.01) and
>>>>> replace
>>>>> the one in 2016?
>>>>
>>>> That doesn't work at all.  Now it fails to detect the FPGA, then
>>>> hangs after printing the amount of DRAM.

This is sorta similar to what I see with my SocDK occasionally.
Sometimes rints ram and then hangs, other timmes fails to find mmc.
As I mentioned in other email.

>>>
>>> Can you share with me the pll_config for 2013.01.01 that is working for
>>> you?
>>
>> I don't know that it is.  The only thing I've found to work is the
>> unidentified SPL on the SD card that came with the dev kit.
>
> I pushed some DDR fixes into u-boot-socfpga/ddr branch [1], which fixed
> DDR calibration issue on a board I have in here. Can you try them ? Thanks
>
> [1]
> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/ddr
>


-- 
Regards
Phil Reid

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Dinh Nguyen]

On 01/22/2016 10:35 AM, Dinh Nguyen wrote:
> On 01/21/2016 10:31 AM, Marek Vasut wrote:
>> On Thursday, January 21, 2016 at 05:20:33 PM, M?ns Rullg?rd wrote:
>>> Tom Rini <trini@konsulko.com> writes:
>>>> On Wed, Jan 20, 2016 at 08:31:30PM +0000, M?ns Rullg?rd wrote:
>>>>> I'm having a problem with u-boot 2016.01 failing to detect the FPGA on
>>>>> my Altera Cyclone V SoC Development Kit.  On startup, it simply prints
>>>>> "FPGA: Not Altera chip ID" (the ID having been read as all-zero).  No
>>>>> amount of messing with jumpers or switches makes a difference.  The
>>>>> software on the SD card included in the box appears to work, so on a
>>>>> whim I took the SPL pre-loader from this card and combined it with the
>>>>> main 2016.01 u-boot.  This makes the detection succeed, despite Marek
>>>>> baulking at this idea.  The "good" SPL identifies as "U-Boot SPL
>>>>> 2013.01.01 (Dec 04 2014 - 08:59:41)" which is a different build date
>>>>> than the main u-boot on the same SD card, so which source code version
>>>>> it was built from is anyone's guess.
>>>>>
>>>>> What's interesting is that Marek's board works with u-boot 2016.01 while
>>>>> mine fails even with the very same binary.  The boards are different
>>>>> revisions (his 100-0321003-C1, mine -E1), and the main Cyclone V chips
>>>>> are also different (his 5CSXFC6D6F31C8NES, mine 5CSXFC6D6F31C6N).
>>>>>
>>>>> Any suggestions for what to try next?
>>>>
>>>> v2016.01 release or to of tree?  If top of tree, try
>>>> http://patchwork.ozlabs.org/patch/570009/
>>>
>>> Tried release, top of tree, and top of tree with that patch.  Nothing
>>> works.
>>
>> btw. you dropped Dinh from the CC .
>>
> 
> Sorry, but I haven't had a chance to take a look at this. I'll try to
> looking this in the following week.
> 

It seems to work on older Cyclone V chips. I have the latest devkit,
which has the 5CSXFC6D6F31C6N chip, and I cannot get an FPGA ID. My
older devkit has a 5CSXFC6D6F31C8NES chip, and I can get the FPGA's ID.

I'll have ask around on what changes were done with the later Cyclone V
chips.

Dinh

[U-Boot] FPGA detection failure on Cyclone V soc development kit

[Marek Vasut]

On Monday, February 01, 2016 at 11:25:46 PM, Dinh Nguyen wrote:
> On 01/22/2016 10:35 AM, Dinh Nguyen wrote:
> > On 01/21/2016 10:31 AM, Marek Vasut wrote:
> >> On Thursday, January 21, 2016 at 05:20:33 PM, M?ns Rullg?rd wrote:
> >>> Tom Rini <trini@konsulko.com> writes:
> >>>> On Wed, Jan 20, 2016 at 08:31:30PM +0000, M?ns Rullg?rd wrote:
> >>>>> I'm having a problem with u-boot 2016.01 failing to detect the FPGA
> >>>>> on my Altera Cyclone V SoC Development Kit.  On startup, it simply
> >>>>> prints "FPGA: Not Altera chip ID" (the ID having been read as
> >>>>> all-zero).  No amount of messing with jumpers or switches makes a
> >>>>> difference.  The software on the SD card included in the box appears
> >>>>> to work, so on a whim I took the SPL pre-loader from this card and
> >>>>> combined it with the main 2016.01 u-boot.  This makes the detection
> >>>>> succeed, despite Marek baulking at this idea.  The "good" SPL
> >>>>> identifies as "U-Boot SPL 2013.01.01 (Dec 04 2014 - 08:59:41)" which
> >>>>> is a different build date than the main u-boot on the same SD card,
> >>>>> so which source code version it was built from is anyone's guess.
> >>>>> 
> >>>>> What's interesting is that Marek's board works with u-boot 2016.01
> >>>>> while mine fails even with the very same binary.  The boards are
> >>>>> different revisions (his 100-0321003-C1, mine -E1), and the main
> >>>>> Cyclone V chips are also different (his 5CSXFC6D6F31C8NES, mine
> >>>>> 5CSXFC6D6F31C6N).
> >>>>> 
> >>>>> Any suggestions for what to try next?
> >>>> 
> >>>> v2016.01 release or to of tree?  If top of tree, try
> >>>> http://patchwork.ozlabs.org/patch/570009/
> >>> 
> >>> Tried release, top of tree, and top of tree with that patch.  Nothing
> >>> works.
> >> 
> >> btw. you dropped Dinh from the CC .
> > 
> > Sorry, but I haven't had a chance to take a look at this. I'll try to
> > looking this in the following week.
> 
> It seems to work on older Cyclone V chips. I have the latest devkit,
> which has the 5CSXFC6D6F31C6N chip, and I cannot get an FPGA ID. My
> older devkit has a 5CSXFC6D6F31C8NES chip, and I can get the FPGA's ID.

This indeed matches my observations. My CV SoCDK also has an older chip,
ES even, and I can detect the FPGA ID.

> I'll have ask around on what changes were done with the later Cyclone V
> chips.

Thanks!

Best regards,
Marek Vasut