From mboxrd@z Thu Jan  1 00:00:00 1970
From: York Sun <york.sun@nxp.com>
Date: Tue, 19 Apr 2016 09:32:39 -0700
Subject: [U-Boot] [PATCH] powerpc/mpc85xx: set L2PE in L2CSR0 before
 enabling L2 cache
In-Reply-To: <1461000513-15729-1-git-send-email-aneesh.bansal@nxp.com>
References: <1461000513-15729-1-git-send-email-aneesh.bansal@nxp.com>
Message-ID: <57165DA7.7060304@nxp.com>
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To: u-boot@lists.denx.de

On 04/18/2016 05:16 AM, Aneesh Bansal wrote:
> While enabling L2 cache, the value of L2PE (L2 cache parity/ECC
> error checking enable) must not be changed while the L2 cache is
> enabled.
> So, L2PE must be set before enabling L2 cache.

Aneesh,

The original code set L2PE and L2E together. The L2PE bit doesn't change after
that. Doesn't this satisfy the requirement? Did you observe any failure before
your patch?

York