From: York Sun <york.sun@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cache
Date: Wed, 20 Apr 2016 08:28:32 -0700 [thread overview]
Message-ID: <5717A020.8090002@nxp.com> (raw)
In-Reply-To: <AMXPR04MB135582C76B861AC0D334507FA6D0@AMXPR04MB135.eurprd04.prod.outlook.com>
On 04/20/2016 04:06 AM, Aneesh Bansal wrote:
>> -----Original Message-----
>> From: York Sun [mailto:york.sun at nxp.com]
>> Sent: Tuesday, April 19, 2016 10:03 PM
>> To: Aneesh Bansal <aneesh.bansal@nxp.com>; u-boot at lists.denx.de
>> Cc: Ruchika Gupta <ruchika.gupta@nxp.com>; Prabhakar Kushwaha
>> <prabhakar.kushwaha@nxp.com>
>> Subject: Re: [PATCH] powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2
>> cache
>>
>> On 04/18/2016 05:16 AM, Aneesh Bansal wrote:
>>> While enabling L2 cache, the value of L2PE (L2 cache parity/ECC error
>>> checking enable) must not be changed while the L2 cache is enabled.
>>> So, L2PE must be set before enabling L2 cache.
>>
>> Aneesh,
>>
>> The original code set L2PE and L2E together. The L2PE bit doesn't change after that.
>> Doesn't this satisfy the requirement? Did you observe any failure before your patch?
>>
>> York
>
> e6500 block guide states that "The value of L2PE must not be changed while the L2 cache is enabled"
> So, when both the bits are set together, it might lead to L2 cache getting enabled first and L2PE getting
> set after that. So L2PE is getting changed from 0 to 1 while L2 is still enabled which should not be done.
>
> In normal non-secure boot, U-Boot is the first to use L2 after reset but in case of secure boot, L2 is used
> by Bot ROM before U-Boot. If L2PE and L2E are done together, ECC errors are observed on L2
> (L2CAPTECC - L2 cache error capture ECC syndrome) and U-Boot crashes.
>
> I believe this is because of ECC/Parity checking not getting enabled properly and resulting into
> erroneous detection of errors
>
> When this is changed to setting L2PE before L2E, or not setting L2PE at all i.e. disabling ECC error checks,
> no ECC errors are observed and U-Boot works fine.
>
Aneesh,
You said for secure boot L2 cache was used by bootrom before U-Boot. Could the
L2 cache be left enabled when U-Boot runs? If true, that indeed sets L2PE bit
while L2E is enabled. Please confirm.
If L2E was left set by secure boot, your change actually fixes it, but the
commit message needs to be rewritten.
York
next prev parent reply other threads:[~2016-04-20 15:28 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-18 17:28 [U-Boot] [PATCH] powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cache Aneesh Bansal
2016-04-19 16:32 ` York Sun
2016-04-20 11:06 ` Aneesh Bansal
2016-04-20 15:28 ` York Sun [this message]
2016-04-20 16:27 ` Aneesh Bansal
2016-04-20 16:29 ` York Sun
2016-05-25 3:33 ` York Sun
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