From mboxrd@z Thu Jan 1 00:00:00 1970 From: Heiko Schocher Date: Tue, 3 May 2016 09:51:06 +0200 Subject: [U-Boot] [PATCH 03/18] bootm: Align cache flush end address correctly In-Reply-To: <1462257612-28746-4-git-send-email-sjg@chromium.org> References: <1462257612-28746-1-git-send-email-sjg@chromium.org> <1462257612-28746-4-git-send-email-sjg@chromium.org> Message-ID: <5728586A.3040700@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hello Simon, Am 03.05.2016 um 08:39 schrieb Simon Glass: > Flushing part of the cache should be done on cache boundaries. Trying to > flush part of a cache line is not supported and the request may be ignored > or print warnings. > > Adjust the bootm code to align the end address to prevent this problem. > > Signed-off-by: Simon Glass > --- > > common/bootm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Thanks! Reviewed-by: Heiko Schocher tested on the smartweb, corvus, taurus and axm board Tested-by: Heiko Schocher bye, Heiko > > diff --git a/common/bootm.c b/common/bootm.c > index c965326..7469c61 100644 > --- a/common/bootm.c > +++ b/common/bootm.c > @@ -435,7 +435,7 @@ static int bootm_load_os(bootm_headers_t *images, unsigned long *load_end, > bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE); > return err; > } > - flush_cache(load, *load_end - load); > + flush_cache(load, ALIGN(*load_end - load, ARCH_DMA_MINALIGN)); > > debug(" kernel loaded at 0x%08lx, end = 0x%08lx\n", load, *load_end); > bootstage_mark(BOOTSTAGE_ID_KERNEL_LOADED); > -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany