From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Wed, 04 May 2016 21:16:39 +0200 Subject: [U-Boot] [PATCH V2 1/2] mtd: cqspi: Simplify indirect write code In-Reply-To: <20160504190452.GB9986@amd> References: <1462296357-5921-1-git-send-email-marex@denx.de> <20160504190452.GB9986@amd> Message-ID: <572A4A97.9080008@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 05/04/2016 09:04 PM, Pavel Machek wrote: > Hi! > >> The indirect write code is buggy pile of nastiness which fails horribly >> when the system runs fast enough to saturate the controller. The failure >> results in some pages (256B) not being written to the flash. This can be >> observed on systems which run with Dcache enabled and L2 cache enabled, >> like the Altera SoCFPGA. >> >> This patch replaces the whole unmaintainable indirect write implementation >> with the one from upcoming Linux CQSPI driver, which went through multiple >> rounds of thorough review and testing. While this makes the patch look >> terrifying and violates all best-practices of software development, all >> the patch does is it plucks out duplicate ad-hoc code distributed across >> the driver and replaces it with more compact code doing exactly the same >> thing. > > Ok, sorry, I still don't understand the changelog. > > First, it describes the bug with L2 cache enabled, but then it says > that "all the patch does .. doing exactly the same thing". > > So I assume it does not do the same thing, but replaces duplicated > code in u-boot with working code from Linux? Ah right, the linux code also does FIFO level checking, so it doesn't overflow during the writes. > Thanks for doing this, > Pavel > > -- Best regards, Marek Vasut