From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Fri, 06 May 2016 19:12:51 +0200 Subject: [U-Boot] [PATCH 7/8] mips: ath79: Add AR934x support In-Reply-To: <572C80D2.7030906@gmail.com> References: <1462472097-6407-1-git-send-email-marex@denx.de> <1462472097-6407-7-git-send-email-marex@denx.de> <572C80D2.7030906@gmail.com> Message-ID: <572CD093.1030201@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 05/06/2016 01:32 PM, Daniel Schwierzeck wrote: > > > Am 05.05.2016 um 20:14 schrieb Marek Vasut: >> Add support for the Atheros AR934x WiSoCs. This patchs adds complete >> system init, including PLL and DRAM init, both of which happen from >> full C environment, since the AR934x has proper SRAM. >> >> Signed-off-by: Marek Vasut >> Cc: Daniel Schwierzeck >> Cc: Wills Wang >> --- >> arch/mips/dts/ar934x.dtsi | 94 +++++++ >> arch/mips/mach-ath79/Kconfig | 9 + >> arch/mips/mach-ath79/Makefile | 3 +- >> arch/mips/mach-ath79/ar934x/Makefile | 7 + >> arch/mips/mach-ath79/ar934x/clk.c | 336 ++++++++++++++++++++++++ >> arch/mips/mach-ath79/ar934x/cpu.c | 10 + >> arch/mips/mach-ath79/ar934x/ddr.c | 165 ++++++++++++ >> arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 43 +++ >> arch/mips/mach-ath79/include/mach/ath79.h | 3 + >> 9 files changed, 669 insertions(+), 1 deletion(-) >> create mode 100644 arch/mips/dts/ar934x.dtsi >> create mode 100644 arch/mips/mach-ath79/ar934x/Makefile >> create mode 100644 arch/mips/mach-ath79/ar934x/clk.c >> create mode 100644 arch/mips/mach-ath79/ar934x/cpu.c >> create mode 100644 arch/mips/mach-ath79/ar934x/ddr.c > > there are checkpatch.pl warnings: > > warning: arch/mips/mach-ath79/ar934x/clk.c,151: line over 80 characters > warning: arch/mips/mach-ath79/ar934x/clk.c,152: line over 80 characters > warning: arch/mips/mach-ath79/ar934x/clk.c,158: line over 80 characters > warning: arch/mips/mach-ath79/ar934x/clk.c,159: line over 80 characters > warning: arch/mips/mach-ath79/ar934x/clk.c,323: line over 80 characters > warning: arch/mips/mach-ath79/ar934x/ddr.c,141: line over 80 characters > warning: arch/mips/mach-ath79/ar934x/ddr.c,142: line over 80 characters Hm, I'm not fond of fixing lines which are 81 lines long and fixing them makes the code only more cryptic, but fixed. > error: arch/mips/mach-ath79/ar934x/ddr.c,158: do not use C99 // comments > error: arch/mips/mach-ath79/ar934x/ddr.c,159: do not use C99 // comments > error: arch/mips/mach-ath79/ar934x/ddr.c,160: do not use C99 // comments Oops, these should really be removed. Thanks for spotting that. > checkpatch.pl found 3 error(s), 8 warning(s), 0 checks(s) > > >> >> diff --git a/arch/mips/dts/ar934x.dtsi b/arch/mips/dts/ar934x.dtsi >> new file mode 100644 >> index 0000000..d62c447 >> --- /dev/null >> +++ b/arch/mips/dts/ar934x.dtsi >> @@ -0,0 +1,94 @@ >> +/* >> + * Copyright (C) 2016 Marek Vasut >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#include "skeleton.dtsi" >> + >> +/ { >> + compatible = "qca,ar934x"; >> + >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu at 0 { >> + device_type = "cpu"; >> + compatible = "mips,mips74Kc"; >> + reg = <0>; >> + }; >> + }; >> + >> + clocks { >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + xtal: xtal { >> + #clock-cells = <0>; >> + compatible = "fixed-clock"; >> + clock-output-names = "xtal"; >> + }; >> + }; >> + >> + ahb { >> + compatible = "simple-bus"; >> + ranges; >> + >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + apb { >> + compatible = "simple-bus"; >> + ranges; >> + >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + ehci0: ehci at 1b000100 { >> + compatible = "generic-ehci"; >> + reg = <0x1b000100 0x100>; >> + >> + status = "disabled"; >> + }; >> + >> + uart0: uart at 18020000 { >> + compatible = "ns16550"; >> + reg = <0x18020000 0x20>; >> + reg-shift = <2>; >> + >> + status = "disabled"; >> + }; >> + >> + gmac0: eth at 0x19000000 { >> + compatible = "qca,ag934x-mac"; >> + reg = <0x19000000 0x200>; >> + phy-mode = "rgmii"; >> + >> + status = "disabled"; >> + }; >> + >> + gmac1: eth at 0x1a000000 { >> + compatible = "qca,ag934x-mac"; >> + reg = <0x1a000000 0x200>; >> + phy-mode = "rgmii"; >> + >> + status = "disabled"; >> + }; >> + }; >> + >> + spi0: spi at 1f000000 { >> + compatible = "qca,ar7100-spi"; >> + reg = <0x1f000000 0x10>; >> + >> + status = "disabled"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + }; >> +}; >> diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig >> index f45403b..527960f 100644 >> --- a/arch/mips/mach-ath79/Kconfig >> +++ b/arch/mips/mach-ath79/Kconfig >> @@ -13,6 +13,15 @@ config SOC_AR933X >> help >> This supports QCA/Atheros ar933x family SOCs. >> >> +config SOC_AR934X >> + bool >> + select SUPPORTS_BIG_ENDIAN >> + select SUPPORTS_CPU_MIPS32_R1 >> + select SUPPORTS_CPU_MIPS32_R2 >> + select MIPS_TUNE_74KC > > MIPS_TUNE_74KC doesn't exist yet in arch/mips/Makefile and > arch/mips/Kconfig. You should add it with an extra patch. Done >> + help >> + This supports QCA/Atheros ar934x family SOCs. >> + >> config SOC_QCA953X >> bool >> select SUPPORTS_BIG_ENDIAN >> diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile >> index 160dfaa..d7e2666 100644 >> --- a/arch/mips/mach-ath79/Makefile >> +++ b/arch/mips/mach-ath79/Makefile >> @@ -7,4 +7,5 @@ obj-y += cpu.o >> obj-y += dram.o >> >> obj-$(CONFIG_SOC_AR933X) += ar933x/ >> -obj-$(CONFIG_SOC_QCA953X) += qca953x/ >> \ No newline at end of file >> +obj-$(CONFIG_SOC_AR934X) += ar934x/ >> +obj-$(CONFIG_SOC_QCA953X) += qca953x/ >> diff --git a/arch/mips/mach-ath79/ar934x/Makefile b/arch/mips/mach-ath79/ar934x/Makefile >> new file mode 100644 >> index 0000000..348c65b >> --- /dev/null >> +++ b/arch/mips/mach-ath79/ar934x/Makefile >> @@ -0,0 +1,7 @@ >> +# >> +# SPDX-License-Identifier: GPL-2.0+ >> +# >> + >> +obj-y += cpu.o >> +obj-y += clk.o >> +obj-y += ddr.o >> diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c >> new file mode 100644 >> index 0000000..6611b8d >> --- /dev/null >> +++ b/arch/mips/mach-ath79/ar934x/clk.c >> @@ -0,0 +1,336 @@ >> +/* >> + * Copyright (C) 2016 Marek Vasut >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +DECLARE_GLOBAL_DATA_PTR; >> + >> +/* >> + * The math for calculating PLL: >> + * NFRAC * 2^8 >> + * NINT + ------------- >> + * XTAL [MHz] 2^(18 - 1) >> + * PLL [MHz] = ------------ * ---------------------- >> + * REFDIV 2^OUTDIV >> + * >> + * Unfortunatelly, there is no way to reliably compute the variables. >> + * The vendor U-Boot port contains macros for various combinations of >> + * CPU PLL / DDR PLL / AHB bus speed and there is no obvious pattern >> + * in those numbers. >> + */ >> +struct ar934x_pll_config { >> + u8 range; >> + u8 refdiv; >> + u8 outdiv; >> + /* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */ >> + u8 nint[2]; >> +}; >> + >> +struct ar934x_clock_config { >> + u16 cpu_freq; >> + u16 ddr_freq; >> + u16 ahb_freq; >> + >> + struct ar934x_pll_config cpu_pll; >> + struct ar934x_pll_config ddr_pll; >> +}; >> + >> +static const struct ar934x_clock_config ar934x_clock_config[] = { >> + { 300, 300, 150, { 1, 1, 1, { 24, 15 } }, { 1, 1, 1, { 24, 15 } } }, >> + { 400, 200, 200, { 1, 1, 1, { 32, 20 } }, { 1, 1, 2, { 32, 20 } } }, >> + { 400, 400, 200, { 0, 1, 1, { 32, 20 } }, { 0, 1, 1, { 32, 20 } } }, >> + { 500, 400, 200, { 1, 1, 0, { 20, 12 } }, { 0, 1, 1, { 32, 20 } } }, >> + { 533, 400, 200, { 1, 1, 0, { 21, 13 } }, { 0, 1, 1, { 32, 20 } } }, >> + { 533, 500, 250, { 1, 1, 0, { 21, 13 } }, { 0, 1, 0, { 20, 12 } } }, >> + { 560, 480, 240, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 12 } } }, >> + { 566, 400, 200, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 16, 10 } } }, >> + { 566, 450, 225, { 1, 1, 0, { 22, 14 } }, { 0, 1, 1, { 36, 22 } } }, >> + { 566, 475, 237, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 11 } } }, >> + { 566, 500, 250, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 20, 12 } } }, >> + { 566, 525, 262, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 21, 13 } } }, >> + { 566, 550, 275, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 22, 13 } } }, >> + { 600, 266, 133, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } }, >> + { 600, 266, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } }, >> + { 600, 300, 150, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 24, 15 } } }, >> + { 600, 332, 166, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } }, >> + { 600, 332, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } }, >> + { 600, 400, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 32, 20 } } }, >> + { 600, 450, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 18, 20 } } }, >> + { 600, 500, 250, { 0, 1, 0, { 24, 15 } }, { 1, 1, 0, { 20, 12 } } }, >> + { 600, 525, 262, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 21, 20 } } }, >> + { 600, 550, 275, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 22, 20 } } }, >> + { 600, 575, 287, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 23, 14 } } }, >> + { 600, 600, 300, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 24, 20 } } }, >> + { 600, 650, 325, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 26, 20 } } }, >> + { 650, 600, 300, { 0, 1, 0, { 26, 15 } }, { 0, 1, 0, { 24, 20 } } }, >> + { 700, 400, 200, { 3, 1, 0, { 28, 17 } }, { 0, 1, 1, { 32, 20 } } }, >> +}; >> + >> +static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) >> +{ >> + u32 reg; >> + do { >> + writel(0x10810f00, pll_reg_base + 0x4); >> + writel(srif_val, pll_reg_base + 0x0); >> + writel(0xd0810f00, pll_reg_base + 0x4); >> + writel(0x03000000, pll_reg_base + 0x8); >> + writel(0xd0800f00, pll_reg_base + 0x4); >> + >> + clrbits_be32(pll_reg_base + 0x8, BIT(30)); >> + udelay(5); >> + setbits_be32(pll_reg_base + 0x8, BIT(30)); >> + udelay(5); >> + >> + wait_for_bit("clk", pll_reg_base + 0xc, BIT(3), 1, 10, 0); >> + >> + clrbits_be32(pll_reg_base + 0x8, BIT(30)); >> + udelay(5); >> + >> + /* Check if CPU SRIF PLL locked. */ >> + reg = readl(pll_reg_base + 0x8); >> + reg = (reg & 0x7ffff8) >> 3; >> + } while (reg >= 0x40000); >> +} >> + >> +void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz) >> +{ >> + void __iomem *srif_regs = map_physmem(AR934X_SRIF_BASE, >> + AR934X_SRIF_SIZE, MAP_NOCACHE); >> + void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE, >> + AR71XX_RESET_SIZE, MAP_NOCACHE); >> + void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, >> + AR71XX_PLL_SIZE, MAP_NOCACHE); >> + const struct ar934x_pll_config *pll_cfg; >> + int i, xtal_40 = 0; >> + u32 reg, cpu_pll, cpu_srif, ddr_pll, ddr_srif; >> + >> + /* Register remap failed, hang. */ >> + if (!srif_regs || !reset_regs || !pll_regs) >> + hang(); > > map_physmem() is never NULL unless you implement plat_ioremap(). Thus > those checks aren't necessary. Removed [...] Thanks! Best regards, Marek Vasut