From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Wed, 11 May 2016 13:25:27 +0200
Subject: [U-Boot] [PATCH 03/10] usb: dwc3: add UniPhier specific glue
	layer
In-Reply-To: <1462962515-13181-4-git-send-email-yamada.masahiro@socionext.com>
References: <1462962515-13181-1-git-send-email-yamada.masahiro@socionext.com>
 <1462962515-13181-4-git-send-email-yamada.masahiro@socionext.com>
Message-ID: <573316A7.2070808@denx.de>
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To: u-boot@lists.denx.de

On 05/11/2016 12:28 PM, Masahiro Yamada wrote:
> Add UniPhier platform specific glue layer to support USB3 Host mode
> on Synopsys DWC3 IP.
> 
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Reviewed-by: Marek Vasut <marex@denx.de>

> ---
> 
>  drivers/usb/host/Kconfig         |   7 +++
>  drivers/usb/host/Makefile        |   1 +
>  drivers/usb/host/dwc3-uniphier.c | 110 +++++++++++++++++++++++++++++++++++++++
>  3 files changed, 118 insertions(+)
>  create mode 100644 drivers/usb/host/dwc3-uniphier.c
> 
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index d2363c8..b9eb5ed 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -24,6 +24,13 @@ config USB_XHCI_UNIPHIER
>  	---help---
>  	  Enables support for the on-chip xHCI controller on UniPhier SoCs.
>  
> +config USB_DWC3_UNIPHIER
> +	bool "DesignWare USB3 Host Support on UniPhier Platforms"
> +	depends on ARCH_UNIPHIER
> +	help
> +	  Support of USB2/3 functionality in Socionext UniPhier platforms.
> +	  Say 'Y' here if you have one such device.
> +
>  endif
>  
>  config USB_OHCI_GENERIC
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index 507519e..cc8b584 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -56,6 +56,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
>  # xhci
>  obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
>  obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
> +obj-$(CONFIG_USB_DWC3_UNIPHIER) += dwc3-uniphier.o
>  obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o
>  obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
>  obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
> diff --git a/drivers/usb/host/dwc3-uniphier.c b/drivers/usb/host/dwc3-uniphier.c
> new file mode 100644
> index 0000000..0571c6e
> --- /dev/null
> +++ b/drivers/usb/host/dwc3-uniphier.c
> @@ -0,0 +1,110 @@
> +/*
> + * UniPhier Specific Glue Layer for DWC3
> + *
> + * Copyright (C) 2016 Socionext Inc.
> + *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <mapmem.h>
> +#include <dm/device.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/sizes.h>
> +
> +#define UNIPHIER_PRO4_DWC3_RESET	0x40
> +#define   UNIPHIER_PRO4_DWC3_RESET_XIOMMU	BIT(5)
> +#define   UNIPHIER_PRO4_DWC3_RESET_XLINK	BIT(4)
> +
> +#define UNIPHIER_PRO5_DWC3_RESET	0x00
> +#define   UNIPHIER_PRO5_DWC3_RESET_XLINK	BIT(15)
> +#define   UNIPHIER_PRO5_DWC3_RESET_XIOMMU	BIT(14)
> +
> +#define UNIPHIER_PXS2_DWC3_RESET	0x00
> +#define   UNIPHIER_PXS2_DWC3_RESET_XLINK	BIT(15)
> +
> +static int uniphier_pro4_dwc3_init(void __iomem *regs)
> +{
> +	u32 tmp;
> +
> +	tmp = readl(regs + UNIPHIER_PRO4_DWC3_RESET);
> +	tmp |= UNIPHIER_PRO4_DWC3_RESET_XIOMMU | UNIPHIER_PRO4_DWC3_RESET_XLINK;
> +	writel(tmp, regs + UNIPHIER_PRO4_DWC3_RESET);
> +
> +	return 0;
> +}
> +
> +static int uniphier_pro5_dwc3_init(void __iomem *regs)
> +{
> +	u32 tmp;
> +
> +	tmp = readl(regs + UNIPHIER_PRO5_DWC3_RESET);
> +	tmp |= UNIPHIER_PRO5_DWC3_RESET_XLINK | UNIPHIER_PRO5_DWC3_RESET_XIOMMU;
> +	writel(tmp, regs + UNIPHIER_PRO5_DWC3_RESET);

I like how the bits doing exactly the same thing are always placed
elsewhere :-)

> +	return 0;
> +}
> +
> +
> +static int uniphier_pxs2_dwc3_init(void __iomem *regs)
> +{
> +	u32 tmp;
> +
> +	tmp = readl(regs + UNIPHIER_PXS2_DWC3_RESET);
> +	tmp |= UNIPHIER_PXS2_DWC3_RESET_XLINK | UNIPHIER_PXS2_DWC3_RESET_XIOMMU;
> +	writel(tmp, regs + UNIPHIER_PXS2_DWC3_RESET);
> +
> +	return 0;
> +}
> +
> +static int uniphier_dwc3_probe(struct udevice *dev)
> +{
> +	fdt_addr_t base;
> +	void __iomem *regs;
> +	int (*init)(void __iomem *regs);
> +	int ret;
> +
> +	base = dev_get_addr(dev);
> +	if (base == FDT_ADDR_T_NONE)
> +		return -EINVAL;
> +
> +	regs = map_sysmem(base, SZ_32K);
> +	if (!regs)
> +		return -ENOMEM;
> +
> +	init = (int (*)(void __iomem *regs))dev_get_driver_data(dev);
> +	ret = init(regs);
> +
> +	unmap_sysmem(regs);
> +
> +	return 0;
> +}
> +
> +static const struct udevice_id uniphier_dwc3_match[] = {
> +	{
> +		.compatible = "socionext,uniphier-pro4-dwc3",
> +		.data = (ulong)uniphier_pro4_dwc3_init,
> +	},
> +	{
> +		.compatible = "socionext,uniphier-pro5-dwc3",
> +		.data = (ulong)uniphier_pro5_dwc3_init,
> +	},
> +	{
> +		.compatible = "socionext,uniphier-pxs2-dwc3",
> +		.data = (ulong)uniphier_pxs2_dwc3_init,
> +	},
> +	{
> +		.compatible = "socionext,uniphier-ld20-dwc3",
> +		.data = (ulong)uniphier_pxs2_dwc3_init,
> +	},
> +	{ /* sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(usb_xhci) = {
> +	.name	= "uniphier-dwc3",
> +	.id	= UCLASS_SIMPLE_BUS,
> +	.of_match = uniphier_dwc3_match,
> +	.probe = uniphier_dwc3_probe,
> +};
> 


-- 
Best regards,
Marek Vasut