From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Mon, 16 May 2016 09:55:10 -0700 Subject: [U-Boot] [PATCH 1/2] drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl In-Reply-To: <1462328422-37229-1-git-send-email-Shengzhou.Liu@nxp.com> References: <1462328422-37229-1-git-send-email-Shengzhou.Liu@nxp.com> Message-ID: <5739FB6E.1020306@nxp.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 05/03/2016 07:30 PM, Shengzhou Liu wrote: > The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series, > but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs. > We should update it to adapt the case that clk_adjust is odd data. > > Signed-off-by: Shengzhou Liu > --- > drivers/ddr/fsl/ctrl_regs.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c > index 9073917..b26269c 100644 > --- a/drivers/ddr/fsl/ctrl_regs.c > +++ b/drivers/ddr/fsl/ctrl_regs.c > @@ -1835,10 +1835,17 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, > /* Per FSL Application Note: AN2805 */ > ss_en = 1; > #endif > - clk_adjust = popts->clk_adjust; > + if (fsl_ddr_get_version(0) >= 0x40701) { > + /* clk_adjust in 5-bits on T-series and LS-series */ > + clk_adjust = (popts->clk_adjust & 0x1F) << 22; > + } else { > + /* clk_adjust in 4-bits on earlier MPC85xx and P-series */ > + clk_adjust = (popts->clk_adjust & 0xF) << 23; > + } > + > ddr->ddr_sdram_clk_cntl = (0 > | ((ss_en & 0x1) << 31) > - | ((clk_adjust & 0xF) << 23) > + | clk_adjust > ); > debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); > } > Shengzhou, Your understanding is correct. However, we have done analysis that the additional bit is not used for finer adjustment. So unless you have a case requiring values in the middle, I suggest to keep current code. York