* [U-Boot] [PATCH 1/3] arm64: optimize __asm_{flush, invalidate}_dcache_all
2016-05-17 7:38 [U-Boot] [PATCH 0/3] arm64: minor fixes of cache operation routine Masahiro Yamada
@ 2016-05-17 7:38 ` Masahiro Yamada
2016-05-17 15:32 ` York Sun
2016-05-30 18:05 ` [U-Boot] [U-Boot, " Tom Rini
2016-05-17 7:38 ` [U-Boot] [PATCH 2/3] arm64: fix comment "flush & invalidate" Masahiro Yamada
2016-05-17 7:38 ` [U-Boot] [PATCH 3/3] arm64: rename __asm_flush_dcache_level to __asm_dcache_level Masahiro Yamada
2 siblings, 2 replies; 8+ messages in thread
From: Masahiro Yamada @ 2016-05-17 7:38 UTC (permalink / raw)
To: u-boot
__asm_dcache_all can directly return to the caller of
__asm_{flush,invalidate}_dcache_all.
We do not have to waste x16 register here.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/cpu/armv8/cache.S | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index a9f4fec..1c71a2f 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -104,19 +104,13 @@ finished:
ENDPROC(__asm_dcache_all)
ENTRY(__asm_flush_dcache_all)
- mov x16, lr
mov x0, #0
- bl __asm_dcache_all
- mov lr, x16
- ret
+ b __asm_dcache_all
ENDPROC(__asm_flush_dcache_all)
ENTRY(__asm_invalidate_dcache_all)
- mov x16, lr
mov x0, #0x1
- bl __asm_dcache_all
- mov lr, x16
- ret
+ b __asm_dcache_all
ENDPROC(__asm_invalidate_dcache_all)
/*
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [U-Boot] [PATCH 1/3] arm64: optimize __asm_{flush, invalidate}_dcache_all
2016-05-17 7:38 ` [U-Boot] [PATCH 1/3] arm64: optimize __asm_{flush, invalidate}_dcache_all Masahiro Yamada
@ 2016-05-17 15:32 ` York Sun
2016-05-30 18:05 ` [U-Boot] [U-Boot, " Tom Rini
1 sibling, 0 replies; 8+ messages in thread
From: York Sun @ 2016-05-17 15:32 UTC (permalink / raw)
To: u-boot
On 05/17/2016 12:37 AM, Masahiro Yamada wrote:
> __asm_dcache_all can directly return to the caller of
> __asm_{flush,invalidate}_dcache_all.
>
> We do not have to waste x16 register here.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> ---
>
> arch/arm/cpu/armv8/cache.S | 10 ++--------
> 1 file changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
> index a9f4fec..1c71a2f 100644
> --- a/arch/arm/cpu/armv8/cache.S
> +++ b/arch/arm/cpu/armv8/cache.S
> @@ -104,19 +104,13 @@ finished:
> ENDPROC(__asm_dcache_all)
>
> ENTRY(__asm_flush_dcache_all)
> - mov x16, lr
> mov x0, #0
> - bl __asm_dcache_all
> - mov lr, x16
> - ret
> + b __asm_dcache_all
> ENDPROC(__asm_flush_dcache_all)
>
> ENTRY(__asm_invalidate_dcache_all)
> - mov x16, lr
> mov x0, #0x1
> - bl __asm_dcache_all
> - mov lr, x16
> - ret
> + b __asm_dcache_all
> ENDPROC(__asm_invalidate_dcache_all)
>
> /*
>
It is a smart solution.
Reviewed-by: York Sun <york.sun@nxp.com>
^ permalink raw reply [flat|nested] 8+ messages in thread* [U-Boot] [U-Boot, 1/3] arm64: optimize __asm_{flush, invalidate}_dcache_all
2016-05-17 7:38 ` [U-Boot] [PATCH 1/3] arm64: optimize __asm_{flush, invalidate}_dcache_all Masahiro Yamada
2016-05-17 15:32 ` York Sun
@ 2016-05-30 18:05 ` Tom Rini
1 sibling, 0 replies; 8+ messages in thread
From: Tom Rini @ 2016-05-30 18:05 UTC (permalink / raw)
To: u-boot
On Tue, May 17, 2016 at 04:38:06PM +0900, Masahiro Yamada wrote:
> __asm_dcache_all can directly return to the caller of
> __asm_{flush,invalidate}_dcache_all.
>
> We do not have to waste x16 register here.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> Reviewed-by: York Sun <york.sun@nxp.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 2/3] arm64: fix comment "flush & invalidate"
2016-05-17 7:38 [U-Boot] [PATCH 0/3] arm64: minor fixes of cache operation routine Masahiro Yamada
2016-05-17 7:38 ` [U-Boot] [PATCH 1/3] arm64: optimize __asm_{flush, invalidate}_dcache_all Masahiro Yamada
@ 2016-05-17 7:38 ` Masahiro Yamada
2016-05-30 18:05 ` [U-Boot] [U-Boot,2/3] " Tom Rini
2016-05-17 7:38 ` [U-Boot] [PATCH 3/3] arm64: rename __asm_flush_dcache_level to __asm_dcache_level Masahiro Yamada
2 siblings, 1 reply; 8+ messages in thread
From: Masahiro Yamada @ 2016-05-17 7:38 UTC (permalink / raw)
To: u-boot
We should say "clean & invalidate", or simply "flush".
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/cpu/armv8/cache.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index 1c71a2f..6aaecf3 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -19,7 +19,7 @@
* clean and invalidate one level cache.
*
* x0: cache level
- * x1: 0 flush & invalidate, 1 invalidate only
+ * x1: 0 clean & invalidate, 1 invalidate only
* x2~x9: clobbered
*/
ENTRY(__asm_flush_dcache_level)
@@ -62,7 +62,7 @@ ENDPROC(__asm_flush_dcache_level)
/*
* void __asm_flush_dcache_all(int invalidate_only)
*
- * x0: 0 flush & invalidate, 1 invalidate only
+ * x0: 0 clean & invalidate, 1 invalidate only
*
* clean and invalidate all data cache by SET/WAY.
*/
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [U-Boot] [PATCH 3/3] arm64: rename __asm_flush_dcache_level to __asm_dcache_level
2016-05-17 7:38 [U-Boot] [PATCH 0/3] arm64: minor fixes of cache operation routine Masahiro Yamada
2016-05-17 7:38 ` [U-Boot] [PATCH 1/3] arm64: optimize __asm_{flush, invalidate}_dcache_all Masahiro Yamada
2016-05-17 7:38 ` [U-Boot] [PATCH 2/3] arm64: fix comment "flush & invalidate" Masahiro Yamada
@ 2016-05-17 7:38 ` Masahiro Yamada
2016-05-30 18:06 ` [U-Boot] [U-Boot, " Tom Rini
2 siblings, 1 reply; 8+ messages in thread
From: Masahiro Yamada @ 2016-05-17 7:38 UTC (permalink / raw)
To: u-boot
Since 1e6ad55c0582 ("armv8/cache: Change cache invalidate and flush
function"), this routine can be used for both cache flushing and
cache invalidation. So, it is better to not include "flush" in
this routine name.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/cpu/armv8/cache.S | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index 6aaecf3..46f25e6 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -14,15 +14,15 @@
#include <linux/linkage.h>
/*
- * void __asm_flush_dcache_level(level)
+ * void __asm_dcache_level(level)
*
- * clean and invalidate one level cache.
+ * flush or invalidate one level cache.
*
* x0: cache level
* x1: 0 clean & invalidate, 1 invalidate only
* x2~x9: clobbered
*/
-ENTRY(__asm_flush_dcache_level)
+ENTRY(__asm_dcache_level)
lsl x12, x0, #1
msr csselr_el1, x12 /* select cache level */
isb /* sync change of cssidr_el1 */
@@ -57,14 +57,14 @@ loop_way:
b.ge loop_set
ret
-ENDPROC(__asm_flush_dcache_level)
+ENDPROC(__asm_dcache_level)
/*
* void __asm_flush_dcache_all(int invalidate_only)
*
* x0: 0 clean & invalidate, 1 invalidate only
*
- * clean and invalidate all data cache by SET/WAY.
+ * flush or invalidate all data cache by SET/WAY.
*/
ENTRY(__asm_dcache_all)
mov x1, x0
@@ -87,7 +87,7 @@ loop_level:
and x12, x12, #7 /* x12 <- cache type */
cmp x12, #2
b.lt skip /* skip if no cache or icache */
- bl __asm_flush_dcache_level /* x1 = 0 flush, 1 invalidate */
+ bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */
skip:
add x0, x0, #1 /* increment cache level */
cmp x11, x0
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread