From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Tue, 17 May 2016 09:52:09 -0700 Subject: [U-Boot] [u-boot-release] [PATCH 06/10][v3] armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC In-Reply-To: References: <1463214680-11037-1-git-send-email-prabhakar.kushwaha@nxp.com> <1463214680-11037-7-git-send-email-prabhakar.kushwaha@nxp.com> Message-ID: <573B4C39.2080609@nxp.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 05/17/2016 09:35 AM, Edward L Swarthout wrote: > From: Prabhakar Kushwaha: >> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c >> unsigned int cpu; >> + unsigned int svr, ver; >> const u8 core_cplx_pll[8] = { > ... >> - FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK; >> + svr = gur_in32(&gur->svr); >> + ver = SVR_SOC_VER(svr); >> + if (ver == SVR_LS1012) { >> + sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> >> + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & >> + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; >> + } else { >> + sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> >> + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & >> + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; > > Why introduce a run-time check for every board when this could be handled at compile time? > Ed, Do you mean the platform PLL is fixed and not controlled by RCW? York