[U-Boot] [PATCH 3/3] driver/ddr/fsl: Add workaround for erratum A-009801

York Sun
2016-05-24T17:24:40Z

> The initial training for the DDRC may provide results that are not
> optimized. The workaround provides better read timing margins.
>
> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
> ---
> arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
> drivers/ddr/fsl/fsl_ddr_gen4.c | 7 +++++++
> include/fsl_ddr_sdram.h | 4 ++++
> 3 files changed, 12 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> index 6ec7e50..ba06465 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> @@ -119,6 +119,7 @@
> #define CONFIG_SYS_FSL_ERRATUM_A008751
> #define CONFIG_SYS_FSL_ERRATUM_A009635
> #define CONFIG_SYS_FSL_ERRATUM_A009663
> +#define CONFIG_SYS_FSL_ERRATUM_A009801
> #define CONFIG_SYS_FSL_ERRATUM_A009803
> #define CONFIG_SYS_FSL_ERRATUM_A009942
>
> diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
> index 7cdb700..1dc0631 100644
> --- a/drivers/ddr/fsl/fsl_ddr_gen4.c
> +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
> @@ -251,6 +251,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
> }
> #endif
>
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A009801
> + temp32 = ddr_in32(&ddr->debug[25]);
> + temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK;
> + temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT;
> + ddr_out32(&ddr->debug[25], temp32);
> +#endif
> +

Shengzhou,

Please examine workaround for A008511. This workaround has been included, but
wasn't named as A009801. You can move out that code and put under A009801 if like.

York