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From: York Sun <york.sun@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2] armv8/ls2080ardb: Update DDR timing to support more UDIMMs
Date: Tue, 24 May 2016 10:06:45 -0700	[thread overview]
Message-ID: <57448A25.7080709@nxp.com> (raw)
In-Reply-To: <1460011290-28704-1-git-send-email-Shengzhou.Liu@nxp.com>

On 04/06/2016 11:50 PM, Shengzhou Liu wrote:
> Optimize DDR timing for good margins to support new Transcend
> and Apacer DDR4 UDIMM besides current Micron UDIMM.
> 
> Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with
> following UDIMM on LS2080ARDB.
>  - Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z
>  - Apacer UDIMM: 78.C1GM4.AF10B
>  - Transcend UDIMM: TS1GLH72V1H
> 
> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
> ---
> v2: verified lower rate, for 1333MT/s no changes are necessary. 
> 
>  board/freescale/ls2080ardb/ddr.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Applied to u-boot-fsl-qoriq master, awaiting upstream.

Thanks.

York

      parent reply	other threads:[~2016-05-24 17:06 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-07  6:41 [U-Boot] [PATCH v2] armv8/ls2080ardb: Update DDR timing to support more UDIMMs Shengzhou Liu
2016-05-05 19:29 ` York Sun
2016-05-17 16:25   ` York Sun
2016-05-18 20:27     ` York Sun
2016-05-27 11:28       ` Shengzhou Liu
2016-05-24 17:06 ` York Sun [this message]

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