From mboxrd@z Thu Jan  1 00:00:00 1970
From: York Sun <york.sun@nxp.com>
Date: Tue, 24 May 2016 20:33:11 -0700
Subject: [U-Boot] [PATCH] powerpc/mpc85xx: set L2PE in L2CSR0 before
 enabling L2 cache
In-Reply-To: <1461000513-15729-1-git-send-email-aneesh.bansal@nxp.com>
References: <1461000513-15729-1-git-send-email-aneesh.bansal@nxp.com>
Message-ID: <57451CF7.2080706@nxp.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

On 04/18/2016 05:16 AM, Aneesh Bansal wrote:
> While enabling L2 cache, the value of L2PE (L2 cache parity/ECC
> error checking enable) must not be changed while the L2 cache is
> enabled.
> So, L2PE must be set before enabling L2 cache.
> 
> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
> ---
>  arch/powerpc/cpu/mpc85xx/start.S | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)


Applied to u-boot-mpc85xx master branch, awaiting upstream.

Thanks.

York