From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Tue, 31 May 2016 02:51:38 +0200
Subject: [U-Boot] [PATCH 4/6] mips: ath79: Add support for ungating USB
 and ethernet on qca953x
In-Reply-To: <BLU436-SMTP235E7AA2B94785DEDA0EE21FF460@phx.gbl>
References: <1464620095-4333-1-git-send-email-wills.wang@live.com>
 <BLU436-SMTP240D823286F8E3B0E37ECB6FF450@phx.gbl> <574C59A9.3030202@denx.de>
 <BLU436-SMTP235E7AA2B94785DEDA0EE21FF460@phx.gbl>
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On 05/31/2016 02:35 AM, Wills Wang wrote:
> 
> 
> On 05/30/2016 11:18 PM, Marek Vasut wrote:
>> On 05/30/2016 04:54 PM, Wills Wang wrote:
>>> Add code to ungate USB and ethernet controller on qca953x
>> Is this code coming from mainline Linux ?
> 
> No, i refer to u-boot code from QSDK.

Oh ok. I'd suggest to pick the code from mainline Linux when possible,
it's far more maintained than the ancient LSDK/QSDK.

>>> Signed-off-by: Wills Wang <wills.wang@live.com>
>>> ---
>>>
>>>   arch/mips/mach-ath79/reset.c | 50
>>> ++++++++++++++++++++++++++++++++++++++++++++
>>>   1 file changed, 50 insertions(+)
>>>
>>> diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
>>> index 33bf979..a5ee141 100644
>>> --- a/arch/mips/mach-ath79/reset.c
>>> +++ b/arch/mips/mach-ath79/reset.c
>>> @@ -136,6 +136,23 @@ static int eth_init_ar934x(void)
>>>       return 0;
>>>   }
>>>   +static int eth_init_qca953x(void)
>>> +{
>>> +    void __iomem *rregs = map_physmem(AR71XX_RESET_BASE,
>>> AR71XX_RESET_SIZE,
>>> +                      MAP_NOCACHE);
>>> +    const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO |
>>> +             QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO |
>>> +             QCA953X_RESET_ETH_SWITCH_ANALOG |
>>> +             QCA953X_RESET_ETH_SWITCH;
>>> +
>>> +    setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
>>> +    mdelay(1);
>>> +    clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
>>> +    mdelay(1);
>>> +
>>> +    return 0;
>>> +}
>>> +
>>>   int ath79_eth_reset(void)
>>>   {
>>>       /*
>>> @@ -146,6 +163,8 @@ int ath79_eth_reset(void)
>>>           return eth_init_ar933x();
>>>       if (soc_is_ar934x())
>>>           return eth_init_ar934x();
>>> +    if (soc_is_qca953x())
>>> +        return eth_init_qca953x();
>>>         return -EINVAL;
>>>   }
>>> @@ -185,6 +204,35 @@ static int usb_reset_ar934x(void __iomem
>>> *reset_regs)
>>>       return 0;
>>>   }
>>>   +static int usb_reset_qca953x(void __iomem *reset_regs)
>>> +{
>>> +    void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
>>> +                      MAP_NOCACHE);
>>> +
>>> +    clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
>>> +            0xf00, 0x200);

Do you know what these magic numbers mean ?

>>> +    mdelay(10);
>>> +
>>> +    /* Ungate the USB block */
>>> +    setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>> +             QCA953X_RESET_USBSUS_OVERRIDE);
>>> +    mdelay(1);
>>> +    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>> +             QCA953X_RESET_USB_PHY);
>>> +    mdelay(1);
>>> +    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>> +             QCA953X_RESET_USB_PHY_ANALOG);
>>> +    mdelay(1);
>>> +    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>> +             QCA953X_RESET_USB_HOST);
>>> +    mdelay(1);
>>> +    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>> +             QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
>>> +    mdelay(1);
>>> +
>>> +    return 0;
>>> +}
>>> +
>>>   int ath79_usb_reset(void)
>>>   {
>>>       void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
>>> @@ -204,6 +252,8 @@ int ath79_usb_reset(void)
>>>           return usb_reset_ar933x(reset_regs);
>>>       if (soc_is_ar934x())
>>>           return usb_reset_ar934x(reset_regs);
>>> +    if (soc_is_qca953x())
>>> +        return usb_reset_qca953x(reset_regs);
>>>         return -EINVAL;
>>>   }
>>>
>>
> 


-- 
Best regards,
Marek Vasut