* [U-Boot] [PATCH 2/6] mips: ath79: ap121: Enable ethernet
[not found] <1464620095-4333-1-git-send-email-wills.wang@live.com>
@ 2016-05-30 14:54 ` Wills Wang
2016-05-31 9:39 ` Daniel Schwierzeck
2016-05-30 14:54 ` [U-Boot] [PATCH 3/6] mips: ath79: Use 8MB flash profile for mtd partition by default Wills Wang
` (3 subsequent siblings)
4 siblings, 1 reply; 16+ messages in thread
From: Wills Wang @ 2016-05-30 14:54 UTC (permalink / raw)
To: u-boot
This patch enable network function for ap121 board.
Signed-off-by: Wills Wang <wills.wang@live.com>
Acked-by: Marek Vasut <marex@denx.de>
---
arch/mips/dts/ap121.dts | 5 +++++
arch/mips/dts/ar933x.dtsi | 4 ++--
board/qca/ap121/ap121.c | 2 ++
configs/ap121_defconfig | 9 +++++++--
4 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/arch/mips/dts/ap121.dts b/arch/mips/dts/ap121.dts
index e31f601..a934a58 100644
--- a/arch/mips/dts/ap121.dts
+++ b/arch/mips/dts/ap121.dts
@@ -41,3 +41,8 @@
reg = <0>;
};
};
+
+&gmac0 {
+ phy-mode = "rmii";
+ status = "okay";
+};
diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi
index 00896b2..971f13e 100644
--- a/arch/mips/dts/ar933x.dtsi
+++ b/arch/mips/dts/ar933x.dtsi
@@ -75,7 +75,7 @@
};
gmac0: eth at 0x19000000 {
- compatible = "qca,ag7240-mac";
+ compatible = "qca,ag933x-mac";
reg = <0x19000000 0x200>;
phy = <&phy0>;
phy-mode = "rmii";
@@ -92,7 +92,7 @@
};
gmac1: eth at 0x1a000000 {
- compatible = "qca,ag7240-mac";
+ compatible = "qca,ag933x-mac";
reg = <0x1a000000 0x200>;
phy = <&phy0>;
phy-mode = "rgmii";
diff --git a/board/qca/ap121/ap121.c b/board/qca/ap121/ap121.c
index d6c60fe..e245faa 100644
--- a/board/qca/ap121/ap121.c
+++ b/board/qca/ap121/ap121.c
@@ -10,6 +10,7 @@
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
#include <mach/ddr.h>
+#include <mach/ath79.h>
#include <debug_uart.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -46,5 +47,6 @@ int board_early_init_f(void)
debug_uart_init();
#endif
ddr_init();
+ ath79_eth_reset();
return 0;
}
diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig
index 7604e2e..91fa734 100644
--- a/configs/ap121_defconfig
+++ b/configs/ap121_defconfig
@@ -19,8 +19,13 @@ CONFIG_SYS_PROMPT="ap121 # "
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
+CONFIG_CMD_NET=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_ETH=y
+CONFIG_AG7XXX=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_ATMEL=y
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [U-Boot] [PATCH 3/6] mips: ath79: Use 8MB flash profile for mtd partition by default
[not found] <1464620095-4333-1-git-send-email-wills.wang@live.com>
2016-05-30 14:54 ` [U-Boot] [PATCH 2/6] mips: ath79: ap121: Enable ethernet Wills Wang
@ 2016-05-30 14:54 ` Wills Wang
2016-05-31 9:40 ` Daniel Schwierzeck
2016-05-30 14:54 ` [U-Boot] [PATCH 4/6] mips: ath79: Add support for ungating USB and ethernet on qca953x Wills Wang
` (2 subsequent siblings)
4 siblings, 1 reply; 16+ messages in thread
From: Wills Wang @ 2016-05-30 14:54 UTC (permalink / raw)
To: u-boot
Change bootm flash address and mtd partition table for 8MB flash profile.
Signed-off-by: Wills Wang <wills.wang@live.com>
---
include/configs/ap121.h | 4 ++--
include/configs/ap143.h | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
index 6f69f31..9537034 100644
--- a/include/configs/ap121.h
+++ b/include/configs/ap121.h
@@ -45,13 +45,13 @@
"rootfstype=squashfs"
#define CONFIG_BOOTCOMMAND "sf probe;" \
"mtdparts default;" \
- "bootm 0x9f300000"
+ "bootm 0x9f650000"
#define CONFIG_LZMA
#define MTDIDS_DEFAULT "nor0=spi-flash.0"
#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \
"256k(u-boot),64k(u-boot-env)," \
- "2752k(rootfs),896k(uImage)," \
+ "6144k(rootfs),1600k(uImage)," \
"64k(NVRAM),64k(ART)"
#define CONFIG_ENV_SPI_MAX_HZ 25000000
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
index f907c02..6f19829 100644
--- a/include/configs/ap143.h
+++ b/include/configs/ap143.h
@@ -49,14 +49,14 @@
"rootfstype=squashfs"
#define CONFIG_BOOTCOMMAND "sf probe;" \
"mtdparts default;" \
- "bootm 0x9f300000"
+ "bootm 0x9f680000"
#define CONFIG_LZMA
#define MTDIDS_DEFAULT "nor0=spi-flash.0"
#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \
"256k(u-boot),64k(u-boot-env)," \
- "2752k(rootfs),896k(uImage)," \
- "64k(NVRAM),64k(ART)"
+ "6336k(rootfs),1472k(uImage)," \
+ "64k(ART)"
#define CONFIG_ENV_SPI_MAX_HZ 25000000
#define CONFIG_ENV_IS_IN_SPI_FLASH
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [U-Boot] [PATCH 4/6] mips: ath79: Add support for ungating USB and ethernet on qca953x
[not found] <1464620095-4333-1-git-send-email-wills.wang@live.com>
2016-05-30 14:54 ` [U-Boot] [PATCH 2/6] mips: ath79: ap121: Enable ethernet Wills Wang
2016-05-30 14:54 ` [U-Boot] [PATCH 3/6] mips: ath79: Use 8MB flash profile for mtd partition by default Wills Wang
@ 2016-05-30 14:54 ` Wills Wang
2016-05-30 15:18 ` Marek Vasut
2016-05-31 9:40 ` Daniel Schwierzeck
2016-05-30 14:54 ` [U-Boot] [PATCH 5/6] mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro define Wills Wang
2016-05-30 14:54 ` [U-Boot] [PATCH 6/6] mips: ath79: ap143: Reset ethernet on boot Wills Wang
4 siblings, 2 replies; 16+ messages in thread
From: Wills Wang @ 2016-05-30 14:54 UTC (permalink / raw)
To: u-boot
Add code to ungate USB and ethernet controller on qca953x
Signed-off-by: Wills Wang <wills.wang@live.com>
---
arch/mips/mach-ath79/reset.c | 50 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index 33bf979..a5ee141 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -136,6 +136,23 @@ static int eth_init_ar934x(void)
return 0;
}
+static int eth_init_qca953x(void)
+{
+ void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+ MAP_NOCACHE);
+ const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO |
+ QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO |
+ QCA953X_RESET_ETH_SWITCH_ANALOG |
+ QCA953X_RESET_ETH_SWITCH;
+
+ setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+ mdelay(1);
+ clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+ mdelay(1);
+
+ return 0;
+}
+
int ath79_eth_reset(void)
{
/*
@@ -146,6 +163,8 @@ int ath79_eth_reset(void)
return eth_init_ar933x();
if (soc_is_ar934x())
return eth_init_ar934x();
+ if (soc_is_qca953x())
+ return eth_init_qca953x();
return -EINVAL;
}
@@ -185,6 +204,35 @@ static int usb_reset_ar934x(void __iomem *reset_regs)
return 0;
}
+static int usb_reset_qca953x(void __iomem *reset_regs)
+{
+ void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+ MAP_NOCACHE);
+
+ clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
+ 0xf00, 0x200);
+ mdelay(10);
+
+ /* Ungate the USB block */
+ setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+ QCA953X_RESET_USBSUS_OVERRIDE);
+ mdelay(1);
+ clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+ QCA953X_RESET_USB_PHY);
+ mdelay(1);
+ clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+ QCA953X_RESET_USB_PHY_ANALOG);
+ mdelay(1);
+ clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+ QCA953X_RESET_USB_HOST);
+ mdelay(1);
+ clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+ QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
+ mdelay(1);
+
+ return 0;
+}
+
int ath79_usb_reset(void)
{
void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
@@ -204,6 +252,8 @@ int ath79_usb_reset(void)
return usb_reset_ar933x(reset_regs);
if (soc_is_ar934x())
return usb_reset_ar934x(reset_regs);
+ if (soc_is_qca953x())
+ return usb_reset_qca953x(reset_regs);
return -EINVAL;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [U-Boot] [PATCH 4/6] mips: ath79: Add support for ungating USB and ethernet on qca953x
2016-05-30 14:54 ` [U-Boot] [PATCH 4/6] mips: ath79: Add support for ungating USB and ethernet on qca953x Wills Wang
@ 2016-05-30 15:18 ` Marek Vasut
2016-05-31 0:35 ` Wills Wang
2016-05-31 9:40 ` Daniel Schwierzeck
1 sibling, 1 reply; 16+ messages in thread
From: Marek Vasut @ 2016-05-30 15:18 UTC (permalink / raw)
To: u-boot
On 05/30/2016 04:54 PM, Wills Wang wrote:
> Add code to ungate USB and ethernet controller on qca953x
Is this code coming from mainline Linux ?
> Signed-off-by: Wills Wang <wills.wang@live.com>
> ---
>
> arch/mips/mach-ath79/reset.c | 50 ++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 50 insertions(+)
>
> diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
> index 33bf979..a5ee141 100644
> --- a/arch/mips/mach-ath79/reset.c
> +++ b/arch/mips/mach-ath79/reset.c
> @@ -136,6 +136,23 @@ static int eth_init_ar934x(void)
> return 0;
> }
>
> +static int eth_init_qca953x(void)
> +{
> + void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
> + MAP_NOCACHE);
> + const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO |
> + QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO |
> + QCA953X_RESET_ETH_SWITCH_ANALOG |
> + QCA953X_RESET_ETH_SWITCH;
> +
> + setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
> + mdelay(1);
> + clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
> + mdelay(1);
> +
> + return 0;
> +}
> +
> int ath79_eth_reset(void)
> {
> /*
> @@ -146,6 +163,8 @@ int ath79_eth_reset(void)
> return eth_init_ar933x();
> if (soc_is_ar934x())
> return eth_init_ar934x();
> + if (soc_is_qca953x())
> + return eth_init_qca953x();
>
> return -EINVAL;
> }
> @@ -185,6 +204,35 @@ static int usb_reset_ar934x(void __iomem *reset_regs)
> return 0;
> }
>
> +static int usb_reset_qca953x(void __iomem *reset_regs)
> +{
> + void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
> + MAP_NOCACHE);
> +
> + clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
> + 0xf00, 0x200);
> + mdelay(10);
> +
> + /* Ungate the USB block */
> + setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
> + QCA953X_RESET_USBSUS_OVERRIDE);
> + mdelay(1);
> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
> + QCA953X_RESET_USB_PHY);
> + mdelay(1);
> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
> + QCA953X_RESET_USB_PHY_ANALOG);
> + mdelay(1);
> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
> + QCA953X_RESET_USB_HOST);
> + mdelay(1);
> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
> + QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
> + mdelay(1);
> +
> + return 0;
> +}
> +
> int ath79_usb_reset(void)
> {
> void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
> @@ -204,6 +252,8 @@ int ath79_usb_reset(void)
> return usb_reset_ar933x(reset_regs);
> if (soc_is_ar934x())
> return usb_reset_ar934x(reset_regs);
> + if (soc_is_qca953x())
> + return usb_reset_qca953x(reset_regs);
>
> return -EINVAL;
> }
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 16+ messages in thread* [U-Boot] [PATCH 4/6] mips: ath79: Add support for ungating USB and ethernet on qca953x
2016-05-30 15:18 ` Marek Vasut
@ 2016-05-31 0:35 ` Wills Wang
2016-05-31 0:51 ` Marek Vasut
0 siblings, 1 reply; 16+ messages in thread
From: Wills Wang @ 2016-05-31 0:35 UTC (permalink / raw)
To: u-boot
On 05/30/2016 11:18 PM, Marek Vasut wrote:
> On 05/30/2016 04:54 PM, Wills Wang wrote:
>> Add code to ungate USB and ethernet controller on qca953x
> Is this code coming from mainline Linux ?
No, i refer to u-boot code from QSDK.
>> Signed-off-by: Wills Wang <wills.wang@live.com>
>> ---
>>
>> arch/mips/mach-ath79/reset.c | 50 ++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 50 insertions(+)
>>
>> diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
>> index 33bf979..a5ee141 100644
>> --- a/arch/mips/mach-ath79/reset.c
>> +++ b/arch/mips/mach-ath79/reset.c
>> @@ -136,6 +136,23 @@ static int eth_init_ar934x(void)
>> return 0;
>> }
>>
>> +static int eth_init_qca953x(void)
>> +{
>> + void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
>> + MAP_NOCACHE);
>> + const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO |
>> + QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO |
>> + QCA953X_RESET_ETH_SWITCH_ANALOG |
>> + QCA953X_RESET_ETH_SWITCH;
>> +
>> + setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
>> + mdelay(1);
>> + clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
>> + mdelay(1);
>> +
>> + return 0;
>> +}
>> +
>> int ath79_eth_reset(void)
>> {
>> /*
>> @@ -146,6 +163,8 @@ int ath79_eth_reset(void)
>> return eth_init_ar933x();
>> if (soc_is_ar934x())
>> return eth_init_ar934x();
>> + if (soc_is_qca953x())
>> + return eth_init_qca953x();
>>
>> return -EINVAL;
>> }
>> @@ -185,6 +204,35 @@ static int usb_reset_ar934x(void __iomem *reset_regs)
>> return 0;
>> }
>>
>> +static int usb_reset_qca953x(void __iomem *reset_regs)
>> +{
>> + void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
>> + MAP_NOCACHE);
>> +
>> + clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
>> + 0xf00, 0x200);
>> + mdelay(10);
>> +
>> + /* Ungate the USB block */
>> + setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>> + QCA953X_RESET_USBSUS_OVERRIDE);
>> + mdelay(1);
>> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>> + QCA953X_RESET_USB_PHY);
>> + mdelay(1);
>> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>> + QCA953X_RESET_USB_PHY_ANALOG);
>> + mdelay(1);
>> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>> + QCA953X_RESET_USB_HOST);
>> + mdelay(1);
>> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>> + QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
>> + mdelay(1);
>> +
>> + return 0;
>> +}
>> +
>> int ath79_usb_reset(void)
>> {
>> void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
>> @@ -204,6 +252,8 @@ int ath79_usb_reset(void)
>> return usb_reset_ar933x(reset_regs);
>> if (soc_is_ar934x())
>> return usb_reset_ar934x(reset_regs);
>> + if (soc_is_qca953x())
>> + return usb_reset_qca953x(reset_regs);
>>
>> return -EINVAL;
>> }
>>
>
--
Best Regards
Wills
^ permalink raw reply [flat|nested] 16+ messages in thread* [U-Boot] [PATCH 4/6] mips: ath79: Add support for ungating USB and ethernet on qca953x
2016-05-31 0:35 ` Wills Wang
@ 2016-05-31 0:51 ` Marek Vasut
2016-05-31 8:50 ` Piotr Dymacz
0 siblings, 1 reply; 16+ messages in thread
From: Marek Vasut @ 2016-05-31 0:51 UTC (permalink / raw)
To: u-boot
On 05/31/2016 02:35 AM, Wills Wang wrote:
>
>
> On 05/30/2016 11:18 PM, Marek Vasut wrote:
>> On 05/30/2016 04:54 PM, Wills Wang wrote:
>>> Add code to ungate USB and ethernet controller on qca953x
>> Is this code coming from mainline Linux ?
>
> No, i refer to u-boot code from QSDK.
Oh ok. I'd suggest to pick the code from mainline Linux when possible,
it's far more maintained than the ancient LSDK/QSDK.
>>> Signed-off-by: Wills Wang <wills.wang@live.com>
>>> ---
>>>
>>> arch/mips/mach-ath79/reset.c | 50
>>> ++++++++++++++++++++++++++++++++++++++++++++
>>> 1 file changed, 50 insertions(+)
>>>
>>> diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
>>> index 33bf979..a5ee141 100644
>>> --- a/arch/mips/mach-ath79/reset.c
>>> +++ b/arch/mips/mach-ath79/reset.c
>>> @@ -136,6 +136,23 @@ static int eth_init_ar934x(void)
>>> return 0;
>>> }
>>> +static int eth_init_qca953x(void)
>>> +{
>>> + void __iomem *rregs = map_physmem(AR71XX_RESET_BASE,
>>> AR71XX_RESET_SIZE,
>>> + MAP_NOCACHE);
>>> + const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO |
>>> + QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO |
>>> + QCA953X_RESET_ETH_SWITCH_ANALOG |
>>> + QCA953X_RESET_ETH_SWITCH;
>>> +
>>> + setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
>>> + mdelay(1);
>>> + clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
>>> + mdelay(1);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> int ath79_eth_reset(void)
>>> {
>>> /*
>>> @@ -146,6 +163,8 @@ int ath79_eth_reset(void)
>>> return eth_init_ar933x();
>>> if (soc_is_ar934x())
>>> return eth_init_ar934x();
>>> + if (soc_is_qca953x())
>>> + return eth_init_qca953x();
>>> return -EINVAL;
>>> }
>>> @@ -185,6 +204,35 @@ static int usb_reset_ar934x(void __iomem
>>> *reset_regs)
>>> return 0;
>>> }
>>> +static int usb_reset_qca953x(void __iomem *reset_regs)
>>> +{
>>> + void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
>>> + MAP_NOCACHE);
>>> +
>>> + clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
>>> + 0xf00, 0x200);
Do you know what these magic numbers mean ?
>>> + mdelay(10);
>>> +
>>> + /* Ungate the USB block */
>>> + setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>> + QCA953X_RESET_USBSUS_OVERRIDE);
>>> + mdelay(1);
>>> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>> + QCA953X_RESET_USB_PHY);
>>> + mdelay(1);
>>> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>> + QCA953X_RESET_USB_PHY_ANALOG);
>>> + mdelay(1);
>>> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>> + QCA953X_RESET_USB_HOST);
>>> + mdelay(1);
>>> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>> + QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
>>> + mdelay(1);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> int ath79_usb_reset(void)
>>> {
>>> void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
>>> @@ -204,6 +252,8 @@ int ath79_usb_reset(void)
>>> return usb_reset_ar933x(reset_regs);
>>> if (soc_is_ar934x())
>>> return usb_reset_ar934x(reset_regs);
>>> + if (soc_is_qca953x())
>>> + return usb_reset_qca953x(reset_regs);
>>> return -EINVAL;
>>> }
>>>
>>
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 16+ messages in thread* [U-Boot] [PATCH 4/6] mips: ath79: Add support for ungating USB and ethernet on qca953x
2016-05-31 0:51 ` Marek Vasut
@ 2016-05-31 8:50 ` Piotr Dymacz
2016-05-31 11:38 ` Marek Vasut
2016-05-31 14:24 ` Wills Wang
0 siblings, 2 replies; 16+ messages in thread
From: Piotr Dymacz @ 2016-05-31 8:50 UTC (permalink / raw)
To: u-boot
Hello,
2016-05-31 2:51 GMT+02:00 Marek Vasut <marex@denx.de>:
> On 05/31/2016 02:35 AM, Wills Wang wrote:
[snip]
>>>> +static int usb_reset_qca953x(void __iomem *reset_regs)
>>>> +{
>>>> + void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
>>>> + MAP_NOCACHE);
>>>> +
>>>> + clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
>>>> + 0xf00, 0x200);
>
> Do you know what these magic numbers mean ?
I can help here.
This register is common for (almost) all modern QC/A WiSOCs, with
similar structure, at least for AR934x, QCA953x, QCA955x and QCA956x
(please take a look at [1]).
I have seen it (SDK, datasheets) under two different names:
SWITCH_CLOCK_SPARE and SWITCH_CLOCK_CONTROL, on different addresses
(offset +/- 1), depending on the SOC.
The bit field [8:11] is "USB_REFCLK_FREQ_SEL" and it's the same for
all above SOCs. Value (dec) 2 is for 25 MHz, value 5 for 40 MHz.
I'm going to provide some patches for ath79 in future, which will make
code more universal for all QC/A WiSOCs.
--
Regards,
Piotr Dymacz
[1] http://postimg.org/image/tyrkhkw57/full/
>>>> + mdelay(10);
>>>> +
>>>> + /* Ungate the USB block */
>>>> + setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>>> + QCA953X_RESET_USBSUS_OVERRIDE);
>>>> + mdelay(1);
>>>> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>>> + QCA953X_RESET_USB_PHY);
>>>> + mdelay(1);
>>>> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>>> + QCA953X_RESET_USB_PHY_ANALOG);
>>>> + mdelay(1);
>>>> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>>> + QCA953X_RESET_USB_HOST);
>>>> + mdelay(1);
>>>> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>>> + QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
>>>> + mdelay(1);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> int ath79_usb_reset(void)
>>>> {
>>>> void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
>>>> @@ -204,6 +252,8 @@ int ath79_usb_reset(void)
>>>> return usb_reset_ar933x(reset_regs);
>>>> if (soc_is_ar934x())
>>>> return usb_reset_ar934x(reset_regs);
>>>> + if (soc_is_qca953x())
>>>> + return usb_reset_qca953x(reset_regs);
>>>> return -EINVAL;
>>>> }
>>>>
>>>
>>
>
>
> --
> Best regards,
> Marek Vasut
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
^ permalink raw reply [flat|nested] 16+ messages in thread* [U-Boot] [PATCH 4/6] mips: ath79: Add support for ungating USB and ethernet on qca953x
2016-05-31 8:50 ` Piotr Dymacz
@ 2016-05-31 11:38 ` Marek Vasut
2016-05-31 14:24 ` Wills Wang
1 sibling, 0 replies; 16+ messages in thread
From: Marek Vasut @ 2016-05-31 11:38 UTC (permalink / raw)
To: u-boot
On 05/31/2016 10:50 AM, Piotr Dymacz wrote:
> Hello,
>
> 2016-05-31 2:51 GMT+02:00 Marek Vasut <marex@denx.de>:
>> On 05/31/2016 02:35 AM, Wills Wang wrote:
>
> [snip]
>
>>>>> +static int usb_reset_qca953x(void __iomem *reset_regs)
>>>>> +{
>>>>> + void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
>>>>> + MAP_NOCACHE);
>>>>> +
>>>>> + clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
>>>>> + 0xf00, 0x200);
>>
>> Do you know what these magic numbers mean ?
>
> I can help here.
>
> This register is common for (almost) all modern QC/A WiSOCs, with
> similar structure, at least for AR934x, QCA953x, QCA955x and QCA956x
> (please take a look at [1]).
> I have seen it (SDK, datasheets) under two different names:
> SWITCH_CLOCK_SPARE and SWITCH_CLOCK_CONTROL, on different addresses
> (offset +/- 1), depending on the SOC.
>
> The bit field [8:11] is "USB_REFCLK_FREQ_SEL" and it's the same for
> all above SOCs. Value (dec) 2 is for 25 MHz, value 5 for 40 MHz.
>
> I'm going to provide some patches for ath79 in future, which will make
> code more universal for all QC/A WiSOCs.
Oh, very cool, thanks!
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 16+ messages in thread* [U-Boot] [PATCH 4/6] mips: ath79: Add support for ungating USB and ethernet on qca953x
2016-05-31 8:50 ` Piotr Dymacz
2016-05-31 11:38 ` Marek Vasut
@ 2016-05-31 14:24 ` Wills Wang
1 sibling, 0 replies; 16+ messages in thread
From: Wills Wang @ 2016-05-31 14:24 UTC (permalink / raw)
To: u-boot
On 05/31/2016 04:50 PM, Piotr Dymacz wrote:
> Hello,
>
> 2016-05-31 2:51 GMT+02:00 Marek Vasut <marex@denx.de>:
>> On 05/31/2016 02:35 AM, Wills Wang wrote:
> [snip]
>
>>>>> +static int usb_reset_qca953x(void __iomem *reset_regs)
>>>>> +{
>>>>> + void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
>>>>> + MAP_NOCACHE);
>>>>> +
>>>>> + clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
>>>>> + 0xf00, 0x200);
>> Do you know what these magic numbers mean ?
> I can help here.
>
> This register is common for (almost) all modern QC/A WiSOCs, with
> similar structure, at least for AR934x, QCA953x, QCA955x and QCA956x
> (please take a look at [1]).
> I have seen it (SDK, datasheets) under two different names:
> SWITCH_CLOCK_SPARE and SWITCH_CLOCK_CONTROL, on different addresses
> (offset +/- 1), depending on the SOC.
>
> The bit field [8:11] is "USB_REFCLK_FREQ_SEL" and it's the same for
> all above SOCs. Value (dec) 2 is for 25 MHz, value 5 for 40 MHz.
You are right, i found the same description in ar9341 data sheet.
> I'm going to provide some patches for ath79 in future, which will make
> code more universal for all QC/A WiSOCs.
You are always welcome.
> --
> Regards,
> Piotr Dymacz
>
> [1] http://postimg.org/image/tyrkhkw57/full/
>
>>>>> + mdelay(10);
>>>>> +
>>>>> + /* Ungate the USB block */
>>>>> + setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>>>> + QCA953X_RESET_USBSUS_OVERRIDE);
>>>>> + mdelay(1);
>>>>> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>>>> + QCA953X_RESET_USB_PHY);
>>>>> + mdelay(1);
>>>>> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>>>> + QCA953X_RESET_USB_PHY_ANALOG);
>>>>> + mdelay(1);
>>>>> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>>>> + QCA953X_RESET_USB_HOST);
>>>>> + mdelay(1);
>>>>> + clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
>>>>> + QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
>>>>> + mdelay(1);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> int ath79_usb_reset(void)
>>>>> {
>>>>> void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
>>>>> @@ -204,6 +252,8 @@ int ath79_usb_reset(void)
>>>>> return usb_reset_ar933x(reset_regs);
>>>>> if (soc_is_ar934x())
>>>>> return usb_reset_ar934x(reset_regs);
>>>>> + if (soc_is_qca953x())
>>>>> + return usb_reset_qca953x(reset_regs);
>>>>> return -EINVAL;
>>>>> }
>>>>>
>>
>> --
>> Best regards,
>> Marek Vasut
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
--
Best Regards
Wills
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 4/6] mips: ath79: Add support for ungating USB and ethernet on qca953x
2016-05-30 14:54 ` [U-Boot] [PATCH 4/6] mips: ath79: Add support for ungating USB and ethernet on qca953x Wills Wang
2016-05-30 15:18 ` Marek Vasut
@ 2016-05-31 9:40 ` Daniel Schwierzeck
1 sibling, 0 replies; 16+ messages in thread
From: Daniel Schwierzeck @ 2016-05-31 9:40 UTC (permalink / raw)
To: u-boot
Am 30.05.2016 um 16:54 schrieb Wills Wang:
> Add code to ungate USB and ethernet controller on qca953x
>
> Signed-off-by: Wills Wang <wills.wang@live.com>
> ---
>
> arch/mips/mach-ath79/reset.c | 50 ++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 50 insertions(+)
applied to u-boot-mips, thanks!
--
- Daniel
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^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 5/6] mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro define
[not found] <1464620095-4333-1-git-send-email-wills.wang@live.com>
` (2 preceding siblings ...)
2016-05-30 14:54 ` [U-Boot] [PATCH 4/6] mips: ath79: Add support for ungating USB and ethernet on qca953x Wills Wang
@ 2016-05-30 14:54 ` Wills Wang
2016-05-31 9:40 ` Daniel Schwierzeck
2016-05-30 14:54 ` [U-Boot] [PATCH 6/6] mips: ath79: ap143: Reset ethernet on boot Wills Wang
4 siblings, 1 reply; 16+ messages in thread
From: Wills Wang @ 2016-05-30 14:54 UTC (permalink / raw)
To: u-boot
Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip.
Signed-off-by: Wills Wang <wills.wang@live.com>
---
arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1 +
arch/mips/mach-ath79/reset.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index dabcad0..7b48524 100644
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -331,6 +331,7 @@
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLK_CTRL_REG 0x08
#define AR933X_PLL_DITHER_FRAC_REG 0x10
+#define AR933X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index a5ee141..073a179 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -89,7 +89,7 @@ static int eth_init_ar933x(void)
mdelay(10);
/* Get Atheros S26 PHY out of reset. */
- clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG,
+ clrsetbits_be32(pregs + AR933X_PLL_SWITCH_CLOCK_CONTROL_REG,
0x1f, 0x10);
mdelay(10);
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [U-Boot] [PATCH 6/6] mips: ath79: ap143: Reset ethernet on boot
[not found] <1464620095-4333-1-git-send-email-wills.wang@live.com>
` (3 preceding siblings ...)
2016-05-30 14:54 ` [U-Boot] [PATCH 5/6] mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro define Wills Wang
@ 2016-05-30 14:54 ` Wills Wang
2016-05-31 9:41 ` Daniel Schwierzeck
4 siblings, 1 reply; 16+ messages in thread
From: Wills Wang @ 2016-05-30 14:54 UTC (permalink / raw)
To: u-boot
This patch reset the ethernet controller for ap143 board
Signed-off-by: Wills Wang <wills.wang@live.com>
---
board/qca/ap143/ap143.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/qca/ap143/ap143.c b/board/qca/ap143/ap143.c
index 1572472..e921ea5 100644
--- a/board/qca/ap143/ap143.c
+++ b/board/qca/ap143/ap143.c
@@ -10,6 +10,7 @@
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
#include <mach/ddr.h>
+#include <mach/ath79.h>
#include <debug_uart.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -62,5 +63,6 @@ int board_early_init_f(void)
debug_uart_init();
#endif
ddr_init();
+ ath79_eth_reset();
return 0;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread