From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Schwierzeck Date: Tue, 31 May 2016 10:03:08 +0200 Subject: [U-Boot] [PATCH v2 2/3] MIPS: Split I & D cache line size config In-Reply-To: <20160527132806.24134-3-paul.burton@imgtec.com> References: <20160527132806.24134-1-paul.burton@imgtec.com> <20160527132806.24134-3-paul.burton@imgtec.com> Message-ID: <574D453C.9000102@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Am 27.05.2016 um 15:28 schrieb Paul Burton: > Allow L1 Icache & L1 Dcache line size to be specified separately, since > there's no architectural mandate that they be the same. The > [id]cache_line_size functions are tidied up to take advantage of the > fact that the Kconfig entries are always present to simply check them > for zero rather than needing to #ifdef on their presence. > > Signed-off-by: Paul Burton > > --- > > Changes in v2: > - Provide CONFIG_SYS_CACHELINE_SIZE as a synonym for ARCH_DMA_MINALIGN to avoid breaking drivers that use it for now. > > arch/mips/Kconfig | 12 +++++++++--- > arch/mips/include/asm/cache.h | 7 +++++++ > arch/mips/lib/cache.c | 22 +++++++--------------- > arch/mips/lib/cache_init.S | 4 ++-- > board/dbau1x00/Kconfig | 5 ++++- > board/micronas/vct/Kconfig | 5 ++++- > board/pb1x00/Kconfig | 5 ++++- > board/qca/ap121/Kconfig | 5 ++++- > board/qca/ap143/Kconfig | 5 ++++- > board/qemu-mips/Kconfig | 5 ++++- > board/tplink/wdr4300/Kconfig | 5 ++++- > 11 files changed, 53 insertions(+), 27 deletions(-) > applied to u-boot-mips, thanks! -- - Daniel -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 473 bytes Desc: OpenPGP digital signature URL: