* [U-Boot] [PATCH 01/11][v4] armv8: fsl-layerscape: Put SMMU config code in SMMU_BASE
2016-05-31 15:15 [U-Boot] [PATCH 00/11] [v4] armv8: fsl-layerscape: Add support of LS1012A SoC and platform Prabhakar Kushwaha
@ 2016-05-31 15:15 ` Prabhakar Kushwaha
2016-05-31 15:15 ` [U-Boot] [PATCH 02/11][v4] armv8: fsl-layerscape: Avoid LS1043A specifc defines Prabhakar Kushwaha
` (9 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Prabhakar Kushwaha @ 2016-05-31 15:15 UTC (permalink / raw)
To: u-boot
It is not mandatory for Layerscape SoCs to have SMMU. SoCs like
LS1012A are layerscape SoC without SMMU IP.
So put SMMU configuration code under SMMU_BASE.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---
Changes for v2: Sending as it is
Changes for v3: Sending as it is
Changes for v4: Sending as it is
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 04831ca..d743ffe 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -94,11 +94,13 @@ ENTRY(lowlevel_init)
bl ccn504_set_qos
#endif
+#ifdef SMMU_BASE
/* Set the SMMU page size in the sACR register */
ldr x1, =SMMU_BASE
ldr w0, [x1, #0x10]
orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
str w0, [x1, #0x10]
+#endif
/* Initialize GIC Secure Bank Status */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [PATCH 02/11][v4] armv8: fsl-layerscape: Avoid LS1043A specifc defines
2016-05-31 15:15 [U-Boot] [PATCH 00/11] [v4] armv8: fsl-layerscape: Add support of LS1012A SoC and platform Prabhakar Kushwaha
2016-05-31 15:15 ` [U-Boot] [PATCH 01/11][v4] armv8: fsl-layerscape: Put SMMU config code in SMMU_BASE Prabhakar Kushwaha
@ 2016-05-31 15:15 ` Prabhakar Kushwaha
2016-05-31 15:15 ` [U-Boot] [PATCH 03/11][v4] driver: mtd: spi: Adding support for QSPI flash Prabhakar Kushwaha
` (8 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Prabhakar Kushwaha @ 2016-05-31 15:15 UTC (permalink / raw)
To: u-boot
Other than LS1043A, LS1012A also Chassis Gen2 Architecture compliant.
So Avoid LS1043A specific defines in arch/arm
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---
Changes for v2: Sending as it is
Changes for v3: Sending as it is
Changes for v4: Sending as it is
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +-
arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 0fb5c7f..0ae61d6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -224,7 +224,7 @@ int sata_init(void)
}
#endif
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_FSL_LSCH2)
#ifdef CONFIG_SCSI_AHCI_PLAT
int sata_init(void)
{
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index f71c2c1..c4fb7c9 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -55,7 +55,7 @@ enum srds {
FSL_SRDS_1 = 0,
FSL_SRDS_2 = 1,
};
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_FSL_LSCH2)
enum srds_prtcl {
NONE = 0,
PCIE1,
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [PATCH 03/11][v4] driver: mtd: spi: Adding support for QSPI flash
2016-05-31 15:15 [U-Boot] [PATCH 00/11] [v4] armv8: fsl-layerscape: Add support of LS1012A SoC and platform Prabhakar Kushwaha
2016-05-31 15:15 ` [U-Boot] [PATCH 01/11][v4] armv8: fsl-layerscape: Put SMMU config code in SMMU_BASE Prabhakar Kushwaha
2016-05-31 15:15 ` [U-Boot] [PATCH 02/11][v4] armv8: fsl-layerscape: Avoid LS1043A specifc defines Prabhakar Kushwaha
@ 2016-05-31 15:15 ` Prabhakar Kushwaha
2016-05-31 15:15 ` [U-Boot] [PATCH 04/11][v4] armv8: fsl-layerscape: fix compile warning "rcw_tmp" Prabhakar Kushwaha
` (7 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Prabhakar Kushwaha @ 2016-05-31 15:15 UTC (permalink / raw)
To: u-boot
Serial number, vendor id and page size are added for QSPI flash
common on both LS1012AQDS and LS1012ARDB i.e. S25FS512SDSMFI011.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---
Changes for v2: Sending as it is
Changes for v3: Sending as it is
Changes for v4: Sending as it is
drivers/mtd/spi/sf_params.c | 1 +
drivers/mtd/spi/spi_flash.c | 5 +++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 4f37e33..c577d9e 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -67,6 +67,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
{"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP},
{"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL, WR_QPP},
{"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
+ {"S25FS512S", 0x010220, 0x4D00, 128 * 1024, 512, RD_FULL, WR_QPP},
{"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP},
{"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP},
{"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP},
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index fa0e799..64d4e0f 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1072,7 +1072,8 @@ int spi_flash_scan(struct spi_flash *flash)
* sector that is not overlaid by the parameter sectors.
* The uniform sector erase command has no effect on parameter sectors.
*/
- if (jedec == 0x0219 && (ext_jedec & 0xff00) == 0x4d00) {
+ if ((jedec == 0x0219 || (jedec == 0x0220)) &&
+ (ext_jedec & 0xff00) == 0x4d00) {
int ret;
u8 id[6];
@@ -1146,7 +1147,7 @@ int spi_flash_scan(struct spi_flash *flash)
* have 256b pages.
*/
if (ext_jedec == 0x4d00) {
- if ((jedec == 0x0215) || (jedec == 0x216))
+ if ((jedec == 0x0215) || (jedec == 0x216) || (jedec == 0x220))
flash->page_size = 256;
else
flash->page_size = 512;
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [PATCH 04/11][v4] armv8: fsl-layerscape: fix compile warning "rcw_tmp"
2016-05-31 15:15 [U-Boot] [PATCH 00/11] [v4] armv8: fsl-layerscape: Add support of LS1012A SoC and platform Prabhakar Kushwaha
` (2 preceding siblings ...)
2016-05-31 15:15 ` [U-Boot] [PATCH 03/11][v4] driver: mtd: spi: Adding support for QSPI flash Prabhakar Kushwaha
@ 2016-05-31 15:15 ` Prabhakar Kushwaha
2016-05-31 15:15 ` [U-Boot] [PATCH 05/11][v4] armv8: fsl-layerscape: Organize SoC overview at common location Prabhakar Kushwaha
` (6 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Prabhakar Kushwaha @ 2016-05-31 15:15 UTC (permalink / raw)
To: u-boot
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c: In function
?get_sys_info?:
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c:29:6: warning:
unused variable ?rcw_tmp? [-Wunused-variable]
u32 rcw_tmp;
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---
Changes for v2: Sending as it is
Changes for v3: Sending as it is
Changes for v4: Sending as it is
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 453a93d..4fc3186 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -25,7 +25,10 @@ void get_sys_info(struct sys_info *sys_info)
struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
u32 ccr;
#endif
-#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
+#if (defined(CONFIG_FSL_ESDHC) &&\
+ defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
+ defined(CONFIG_SYS_DPAA_FMAN)
+
u32 rcw_tmp;
#endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [PATCH 05/11][v4] armv8: fsl-layerscape: Organize SoC overview at common location
2016-05-31 15:15 [U-Boot] [PATCH 00/11] [v4] armv8: fsl-layerscape: Add support of LS1012A SoC and platform Prabhakar Kushwaha
` (3 preceding siblings ...)
2016-05-31 15:15 ` [U-Boot] [PATCH 04/11][v4] armv8: fsl-layerscape: fix compile warning "rcw_tmp" Prabhakar Kushwaha
@ 2016-05-31 15:15 ` Prabhakar Kushwaha
2016-05-31 15:15 ` [U-Boot] [PATCH 06/11][v4] armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC Prabhakar Kushwaha
` (5 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Prabhakar Kushwaha @ 2016-05-31 15:15 UTC (permalink / raw)
To: u-boot
SoC overviews are getting repeated across board folders.
So, Organize SoC overview at common location i.e. fsl-layerscape/doc
Also move README.lsch2 and README.lsch3 in same folder.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---
Changes for v3: New patch in the list
Changes for v4: Sending as it is
.../armv8/fsl-layerscape/{ => doc}/README.lsch2 | 0
.../armv8/fsl-layerscape/{ => doc}/README.lsch3 | 0
arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 86 ++++++++++++++++++++++
board/freescale/ls1043aqds/README | 37 +---------
board/freescale/ls1043ardb/README | 37 +---------
board/freescale/ls2080aqds/README | 45 +----------
board/freescale/ls2080ardb/README | 45 +----------
7 files changed, 96 insertions(+), 154 deletions(-)
rename arch/arm/cpu/armv8/fsl-layerscape/{ => doc}/README.lsch2 (100%)
rename arch/arm/cpu/armv8/fsl-layerscape/{ => doc}/README.lsch3 (100%)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
similarity index 100%
rename from arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
rename to arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
similarity index 100%
rename from arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
rename to arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
new file mode 100644
index 0000000..a4130ce
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -0,0 +1,86 @@
+SoC overview
+
+ 1. LS1043A
+ 2. LS2080A
+
+LS1043A
+---------
+The LS1043A integrated multicore processor combines four ARM Cortex-A53
+processor cores with datapath acceleration optimized for L2/3 packet
+processing, single pass security offload and robust traffic management
+and quality of service.
+
+The LS1043A SoC includes the following function and features:
+ - Four 64-bit ARM Cortex-A53 CPUs
+ - 1 MB unified L2 Cache
+ - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
+ support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
+ the following functions:
+ - Packet parsing, classification, and distribution (FMan)
+ - Queue management for scheduling, packet sequencing, and congestion
+ management (QMan)
+ - Hardware buffer management for buffer allocation and de-allocation (BMan)
+ - Cryptography acceleration (SEC)
+ - Ethernet interfaces by FMan
+ - Up to 1 x XFI supporting 10G interface
+ - Up to 1 x QSGMII
+ - Up to 4 x SGMII supporting 1000Mbps
+ - Up to 2 x SGMII supporting 2500Mbps
+ - Up to 2 x RGMII supporting 1000Mbps
+ - High-speed peripheral interfaces
+ - Three PCIe 2.0 controllers, one supporting x4 operation
+ - One serial ATA (SATA 3.0) controllers
+ - Additional peripheral interfaces
+ - Three high-speed USB 3.0 controllers with integrated PHY
+ - Enhanced secure digital host controller (eSDXC/eMMC)
+ - Quad Serial Peripheral Interface (QSPI) Controller
+ - Serial peripheral interface (SPI) controller
+ - Four I2C controllers
+ - Two DUARTs
+ - Integrated flash controller supporting NAND and NOR flash
+ - QorIQ platform's trust architecture 2.1
+
+LS2080A
+--------
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
+processor cores with high-performance data path acceleration logic and network
+and peripheral bus interfaces required for networking, telecom/datacom,
+wireless infrastructure, and mil/aerospace applications.
+
+The LS2080A SoC includes the following function and features:
+
+ - Eight 64-bit ARM Cortex-A57 CPUs
+ - 1 MB platform cache with ECC
+ - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
+ - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
+ the AIOP
+ - Data path acceleration architecture (DPAA2) incorporating acceleration for
+ the following functions:
+ - Packet parsing, classification, and distribution (WRIOP)
+ - Queue and Hardware buffer management for scheduling, packet sequencing, and
+ congestion management, buffer allocation and de-allocation (QBMan)
+ - Cryptography acceleration (SEC) at up to 10 Gbps
+ - RegEx pattern matching acceleration (PME) at up to 10 Gbps
+ - Decompression/compression acceleration (DCE) at up to 20 Gbps
+ - Accelerated I/O processing (AIOP) at up to 20 Gbps
+ - QDMA engine
+ - 16 SerDes lanes at up to 10.3125 GHz
+ - Ethernet interfaces
+ - Up to eight 10 Gbps Ethernet MACs
+ - Up to eight 1 / 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+ - Four PCIe 3.0 controllers, one supporting SR-IOV
+ - Additional peripheral interfaces
+ - Two serial ATA (SATA 3.0) controllers
+ - Two high-speed USB 3.0 controllers with integrated PHY
+ - Enhanced secure digital host controller (eSDXC/eMMC)
+ - Serial peripheral interface (SPI) controller
+ - Quad Serial Peripheral Interface (QSPI) Controller
+ - Four I2C controllers
+ - Two DUARTs
+ - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ platform's trust architecture 3.0
+ - Service processor (SP) provides pre-boot initialization and secure-boot
+ capabilities
diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README
index a6fd7a3..913537d 100644
--- a/board/freescale/ls1043aqds/README
+++ b/board/freescale/ls1043aqds/README
@@ -8,41 +8,8 @@ debugging environment.
LS1043A SoC Overview
--------------------
-The LS1043A integrated multicore processor combines four ARM Cortex-A53
-processor cores with datapath acceleration optimized for L2/3 packet
-processing, single pass security offload and robust traffic management
-and quality of service.
-
-The LS1043A SoC includes the following function and features:
- - Four 64-bit ARM Cortex-A53 CPUs
- - 1 MB unified L2 Cache
- - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
- support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
- the following functions:
- - Packet parsing, classification, and distribution (FMan)
- - Queue management for scheduling, packet sequencing, and congestion
- management (QMan)
- - Hardware buffer management for buffer allocation and de-allocation (BMan)
- - Cryptography acceleration (SEC)
- - Ethernet interfaces by FMan
- - Up to 1 x XFI supporting 10G interface
- - Up to 1 x QSGMII
- - Up to 4 x SGMII supporting 1000Mbps
- - Up to 2 x SGMII supporting 2500Mbps
- - Up to 2 x RGMII supporting 1000Mbps
- - High-speed peripheral interfaces
- - Three PCIe 2.0 controllers, one supporting x4 operation
- - One serial ATA (SATA 3.0) controllers
- - Additional peripheral interfaces
- - Three high-speed USB 3.0 controllers with integrated PHY
- - Enhanced secure digital host controller (eSDXC/eMMC)
- - Quad Serial Peripheral Interface (QSPI) Controller
- - Serial peripheral interface (SPI) controller
- - Four I2C controllers
- - Two DUARTs
- - Integrated flash controller supporting NAND and NOR flash
- - QorIQ platform's trust architecture 2.1
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
+SoC overview.
LS1043AQDS board Overview
-----------------------
diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README
index 0556e73..709ddbb 100644
--- a/board/freescale/ls1043ardb/README
+++ b/board/freescale/ls1043ardb/README
@@ -8,41 +8,8 @@ debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
LS1043A SoC Overview
--------------------
-The LS1043A integrated multicore processor combines four ARM Cortex-A53
-processor cores with datapath acceleration optimized for L2/3 packet
-processing, single pass security offload and robust traffic management
-and quality of service.
-
-The LS1043A SoC includes the following function and features:
- - Four 64-bit ARM Cortex-A53 CPUs
- - 1 MB unified L2 Cache
- - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
- support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
- the following functions:
- - Packet parsing, classification, and distribution (FMan)
- - Queue management for scheduling, packet sequencing, and congestion
- management (QMan)
- - Hardware buffer management for buffer allocation and de-allocation (BMan)
- - Cryptography acceleration (SEC)
- - Ethernet interfaces by FMan
- - Up to 1 x XFI supporting 10G interface
- - Up to 1 x QSGMII
- - Up to 4 x SGMII supporting 1000Mbps
- - Up to 2 x SGMII supporting 2500Mbps
- - Up to 2 x RGMII supporting 1000Mbps
- - High-speed peripheral interfaces
- - Three PCIe 2.0 controllers, one supporting x4 operation
- - One serial ATA (SATA 3.0) controllers
- - Additional peripheral interfaces
- - Three high-speed USB 3.0 controllers with integrated PHY
- - Enhanced secure digital host controller (eSDXC/eMMC)
- - Quad Serial Peripheral Interface (QSPI) Controller
- - Serial peripheral interface (SPI) controller
- - Four I2C controllers
- - Two DUARTs
- - Integrated flash controller supporting NAND and NOR flash
- - QorIQ platform's trust architecture 2.1
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
+SoC overview.
LS1043ARDB board Overview
-----------------------
diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README
index 6ddad92..5c98866 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -7,48 +7,9 @@ SW development platform for the Freescale LS2080A processor series, with
a complete debugging environment.
LS2080A SoC Overview
-------------------
-The LS2080A integrated multicore processor combines eight ARM Cortex-A57
-processor cores with high-performance data path acceleration logic and network
-and peripheral bus interfaces required for networking, telecom/datacom,
-wireless infrastructure, and mil/aerospace applications.
-
-The LS2080A SoC includes the following function and features:
-
- - Eight 64-bit ARM Cortex-A57 CPUs
- - 1 MB platform cache with ECC
- - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
- the AIOP
- - Data path acceleration architecture (DPAA2) incorporating acceleration for
- the following functions:
- - Packet parsing, classification, and distribution (WRIOP)
- - Queue and Hardware buffer management for scheduling, packet sequencing, and
- congestion management, buffer allocation and de-allocation (QBMan)
- - Cryptography acceleration (SEC) at up to 10 Gbps
- - RegEx pattern matching acceleration (PME) at up to 10 Gbps
- - Decompression/compression acceleration (DCE) at up to 20 Gbps
- - Accelerated I/O processing (AIOP) at up to 20 Gbps
- - QDMA engine
- - 16 SerDes lanes at up to 10.3125 GHz
- - Ethernet interfaces
- - Up to eight 10 Gbps Ethernet MACs
- - Up to eight 1 / 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
- - Four PCIe 3.0 controllers, one supporting SR-IOV
- - Additional peripheral interfaces
- - Two serial ATA (SATA 3.0) controllers
- - Two high-speed USB 3.0 controllers with integrated PHY
- - Enhanced secure digital host controller (eSDXC/eMMC)
- - Serial peripheral interface (SPI) controller
- - Quad Serial Peripheral Interface (QSPI) Controller
- - Four I2C controllers
- - Two DUARTs
- - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ platform's trust architecture 3.0
- - Service processor (SP) provides pre-boot initialization and secure-boot
- capabilities
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
LS2080AQDS board Overview
-----------------------
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index 6708ca9..b1613ba 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -5,48 +5,9 @@ evaluation, and development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
LS2080A SoC Overview
-------------------
-The LS2080A integrated multicore processor combines eight ARM Cortex-A57
-processor cores with high-performance data path acceleration logic and network
-and peripheral bus interfaces required for networking, telecom/datacom,
-wireless infrastructure, and mil/aerospace applications.
-
-The LS2080A SoC includes the following function and features:
-
- - Eight 64-bit ARM Cortex-A57 CPUs
- - 1 MB platform cache with ECC
- - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
- the AIOP
- - Data path acceleration architecture (DPAA2) incorporating acceleration for
- the following functions:
- - Packet parsing, classification, and distribution (WRIOP)
- - Queue and Hardware buffer management for scheduling, packet sequencing, and
- congestion management, buffer allocation and de-allocation (QBMan)
- - Cryptography acceleration (SEC) at up to 10 Gbps
- - RegEx pattern matching acceleration (PME) at up to 10 Gbps
- - Decompression/compression acceleration (DCE) at up to 20 Gbps
- - Accelerated I/O processing (AIOP) at up to 20 Gbps
- - QDMA engine
- - 16 SerDes lanes at up to 10.3125 GHz
- - Ethernet interfaces
- - Up to eight 10 Gbps Ethernet MACs
- - Up to eight 1 / 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
- - Four PCIe 3.0 controllers, one supporting SR-IOV
- - Additional peripheral interfaces
- - Two serial ATA (SATA 3.0) controllers
- - Two high-speed USB 3.0 controllers with integrated PHY
- - Enhanced secure digital host controller (eSDXC/eMMC)
- - Serial peripheral interface (SPI) controller
- - Quad Serial Peripheral Interface (QSPI) Controller
- - Four I2C controllers
- - Two DUARTs
- - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ platform's trust architecture 3.0
- - Service processor (SP) provides pre-boot initialization and secure-boot
- capabilities
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
LS2080ARDB board Overview
-----------------------
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [PATCH 06/11][v4] armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC
2016-05-31 15:15 [U-Boot] [PATCH 00/11] [v4] armv8: fsl-layerscape: Add support of LS1012A SoC and platform Prabhakar Kushwaha
` (4 preceding siblings ...)
2016-05-31 15:15 ` [U-Boot] [PATCH 05/11][v4] armv8: fsl-layerscape: Organize SoC overview at common location Prabhakar Kushwaha
@ 2016-05-31 15:15 ` Prabhakar Kushwaha
2016-05-31 15:43 ` York Sun
2016-05-31 15:15 ` [U-Boot] [PATCH 07/11][v4] board: freescale: common: Conditionally compile IFC QXIS func Prabhakar Kushwaha
` (4 subsequent siblings)
10 siblings, 1 reply; 13+ messages in thread
From: Prabhakar Kushwaha @ 2016-05-31 15:15 UTC (permalink / raw)
To: u-boot
The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
This patch add support of LS1012A SoC along with
- Update platform & DDR clock read logic as per SVR
- Define MMDC controller register set.
- Update LUT base address for PCIe
- Avoid L3 platform cache compilation
- Update USB address, errata
- SerDes table
- Added CSU IDs for SDHC2, SAI-1 to SAI-4
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---
Changes for v2: Sending as it is
Changes for v3: Incorporated York's comments
- Placed SoC overview in README.soc
Changes for v4
- Incorporated Edward L Swarthout's comments
- Updated DDR speed
- Added defines for MMDC controller
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 +
arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 43 ++++++
.../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 11 ++
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 +
arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c | 74 ++++++++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +
arch/arm/include/asm/arch-fsl-layerscape/config.h | 29 ++++
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 1 +
.../include/asm/arch-fsl-layerscape/fsl_serdes.h | 1 +
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 +
.../include/asm/arch-fsl-layerscape/ns_access.h | 10 ++
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 +
include/fsl_mmdc.h | 164 +++++++++++++++++++++
include/linux/usb/xhci-fsl.h | 6 +-
14 files changed, 351 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
create mode 100644 include/fsl_mmdc.h
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 5f86ef9..eb2cbc3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -28,3 +28,7 @@ endif
ifneq ($(CONFIG_LS1043A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
endif
+
+ifneq ($(CONFIG_LS1012A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
+endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
index a4130ce..8eee016 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -2,6 +2,7 @@ SoC overview
1. LS1043A
2. LS2080A
+ 3. LS1012A
LS1043A
---------
@@ -84,3 +85,45 @@ The LS2080A SoC includes the following function and features:
- QorIQ platform's trust architecture 3.0
- Service processor (SP) provides pre-boot initialization and secure-boot
capabilities
+
+LS1012A
+--------
+The LS1012A features an advanced 64-bit ARM v8 Cortex-
+A53 processor, with 32 KB of parity protected L1-I cache,
+32 KB of ECC protected L1-D cache, as well as 256 KB of
+ECC protected L2 cache.
+
+The LS1012A SoC includes the following function and features:
+ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
+ - ARM v8 cryptography extensions
+ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
+ 16-/8-bit operation (no ECC support)
+ - ARM core-link CCI-400 cache coherent interconnect
+ - Packet Forwarding Engine (PFE)
+ - Cryptography acceleration (SEC)
+ - Ethernet interfaces supported by PFE:
+ - One Configurable x3 SerDes:
+ Two Serdes PLLs supported for usage by any SerDes data lane
+ Support for up to 6 GBaud operation
+ - High-speed peripheral interfaces:
+ - One PCI Express Gen2 controller, supporting x1 operation
+ - One serial ATA (SATA Gen 3.0) controller
+ - One USB 3.0/2.0 controller with integrated PHY
+ - One USB 2.0 controller with ULPI interface. .
+ - Additional peripheral interfaces:
+ - One quad serial peripheral interface (QuadSPI) controller
+ - One serial peripheral interface (SPI) controller
+ - Two enhanced secure digital host controllers
+ - Two I2C controllers
+ - One 16550 compliant DUART (two UART interfaces)
+ - Two general purpose IOs (GPIO)
+ - Two FlexTimers
+ - Five synchronous audio interfaces (SAI)
+ - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
+ - Single-source clocking solution enabling generation of core, platform,
+ DDR, SerDes, and USB clocks from a single external crystal and internal
+ crystaloscillator
+ - Thermal monitor unit (TMU) with +/- 3C accuracy
+ - Two WatchDog timers
+ - ARM generic timer
+ - QorIQ platform's trust architecture 2.1
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 4fc3186..3a77b21 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -59,12 +59,18 @@ void get_sys_info(struct sys_info *sys_info)
sys_info->freq_ddrbus = sysclk;
#endif
+#ifdef CONFIG_LS1012A
+ sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
+ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+#else
sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
+#endif
for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
@@ -83,6 +89,11 @@ void get_sys_info(struct sys_info *sys_info)
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
}
+#ifdef CONFIG_LS1012A
+ sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
+ sys_info->freq_ddrbus *= 2;
+#endif
+
#define HWA_CGA_M1_CLK_SEL 0xe0000000
#define HWA_CGA_M1_CLK_SHIFT 29
#ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index d743ffe..5af6b73 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -183,6 +183,7 @@ ENTRY(lowlevel_init)
ret
ENDPROC(lowlevel_init)
+#ifdef CONFIG_FSL_LSCH3
hnf_pstate_poll:
/* x0 has the desired status, return 0 for success, 1 for timeout
* clobber x1, x2, x3, x4, x6, x7
@@ -260,6 +261,7 @@ ENTRY(__asm_flush_l3_cache)
mov lr, x29
ret
ENDPROC(__asm_flush_l3_cache)
+#endif
#ifdef CONFIG_MP
/* Keep literals not used by the secondary boot code outside it */
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
new file mode 100644
index 0000000..ff0903c
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/immap_lsch2.h>
+
+struct serdes_config {
+ u32 protocol;
+ u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+ {0x2208, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, SATA1} },
+ {0x0008, {NONE, NONE, NONE, SATA1} },
+ {0x3508, {SGMII_FM1_DTSEC1, PCIE1, NONE, SATA1} },
+ {0x3305, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
+ {0x2205, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, PCIE1} },
+ {0x2305, {SGMII_2500_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
+ {0x9508, {TX_CLK, PCIE1, NONE, SATA1} },
+ {0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} },
+ {0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} },
+ {}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+ serdes1_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == cfg)
+ return ptr->lanes[lane];
+ ptr++;
+ }
+
+ return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+ int i;
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == prtcl)
+ break;
+ ptr++;
+ }
+
+ if (!ptr->protocol)
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (ptr->lanes[i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 0ae61d6..dd633f3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -12,8 +12,10 @@
#include <asm/io.h>
#include <asm/global_data.h>
#include <asm/arch-fsl-layerscape/config.h>
+#ifdef CONFIG_SYS_FSL_DDR
#include <fsl_ddr_sdram.h>
#include <fsl_ddr.h>
+#endif
#ifdef CONFIG_CHAIN_OF_TRUST
#include <fsl_validate.h>
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index fbdaa52..44fe0c0 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -14,8 +14,11 @@
#else
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
#endif
+
+#ifndef CONFIG_LS1012A
#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
+#endif
/*
* Reserve secure memory
@@ -200,6 +203,32 @@
#define CONFIG_SYS_FSL_ERRATUM_A009942
#define CONFIG_SYS_FSL_ERRATUM_A009660
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+#elif defined(CONFIG_LS1012A)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
+#define CONFIG_SYS_FSL_SEC_COMPAT 5
+#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
+
+#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
+#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */
+
+#define GICD_BASE 0x01401000
+#define GICC_BASE 0x01402000
+
+#define CONFIG_SYS_FSL_CCSR_GUR_BE
+#define CONFIG_SYS_FSL_CCSR_SCFG_BE
+#define CONFIG_SYS_FSL_ESDHC_BE
+#define CONFIG_SYS_FSL_WDOG_BE
+#define CONFIG_SYS_FSL_DSPI_BE
+#define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_PEX_LUT_BE
+
+#define SRDS_MAX_LANES 4
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_SEC_BE
#else
#error SoC not defined
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 702b9fa..1cebe2f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -14,6 +14,7 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS1043, LS1043, 4),
CPU_TYPE_ENTRY(LS1023, LS1023, 2),
CPU_TYPE_ENTRY(LS2040, LS2040, 4),
+ CPU_TYPE_ENTRY(LS1012, LS1012, 1),
};
#ifndef CONFIG_SYS_DCACHE_OFF
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index c4fb7c9..487cba8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -134,6 +134,7 @@ enum srds_prtcl {
SGMII_2500_FM2_DTSEC6,
SGMII_2500_FM2_DTSEC9,
SGMII_2500_FM2_DTSEC10,
+ TX_CLK,
SERDES_PRCTL_COUNT
};
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 57b99d4..e98e055 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -60,7 +60,11 @@
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
/* LUT registers */
+#ifdef CONFIG_LS1012A
+#define PCIE_LUT_BASE 0xC0000
+#else
#define PCIE_LUT_BASE 0x10000
+#endif
#define PCIE_LUT_LCTRL0 0x7F8
#define PCIE_LUT_DBG 0x7FC
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index a3ccdb0..db76066 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -69,7 +69,12 @@ enum csu_cslx_ind {
CSU_CSLX_IIC4 = 77,
CSU_CSLX_WDT4,
CSU_CSLX_WDT3,
+ CSU_CSLX_ESDHC2 = 80,
CSU_CSLX_WDT5 = 81,
+ CSU_CSLX_SAI2,
+ CSU_CSLX_SAI1,
+ CSU_CSLX_SAI4,
+ CSU_CSLX_SAI3,
CSU_CSLX_FTM2 = 86,
CSU_CSLX_FTM1,
CSU_CSLX_FTM4,
@@ -143,7 +148,12 @@ static struct csu_ns_dev ns_dev[] = {
{CSU_CSLX_IIC4, CSU_ALL_RW},
{CSU_CSLX_WDT4, CSU_ALL_RW},
{CSU_CSLX_WDT3, CSU_ALL_RW},
+ {CSU_CSLX_ESDHC2, CSU_ALL_RW},
{CSU_CSLX_WDT5, CSU_ALL_RW},
+ {CSU_CSLX_SAI2, CSU_ALL_RW},
+ {CSU_CSLX_SAI1, CSU_ALL_RW},
+ {CSU_CSLX_SAI4, CSU_ALL_RW},
+ {CSU_CSLX_SAI3, CSU_ALL_RW},
{CSU_CSLX_FTM2, CSU_ALL_RW},
{CSU_CSLX_FTM1, CSU_ALL_RW},
{CSU_CSLX_FTM4, CSU_ALL_RW},
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 831d817..02ecc62 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -41,6 +41,7 @@ struct cpu_type {
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
#define SVR_WO_E 0xFFFFFE
+#define SVR_LS1012 0x870400
#define SVR_LS1043 0x879200
#define SVR_LS1023 0x879208
#define SVR_LS2045 0x870120
diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
new file mode 100644
index 0000000..31411f7
--- /dev/null
+++ b/include/fsl_mmdc.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef FSL_MMDC_H
+#define FSL_MMDC_H
+
+#define CONFIG_SYS_MMDC_CORE_ODT_TIMING 0x12554000
+#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_0 0xbabf7954
+#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1 0xff328f64
+#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2 0x01ff00db
+
+#define CONFIG_SYS_MMDC_CORE_MISC 0x00000680
+#define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT 0x00000800
+#define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY 0x00002000
+#define CONFIG_SYS_MMDC_PHY_ODT_CTRL 0x0000022a
+
+#define CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY 0x00bf1023
+
+#define CONFIG_SYS_MMDC_CORE_ADDR_PARTITION 0x0000007f
+
+#define CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL 0xa1390003
+
+#define FORCE_ZQ_AUTO_CALIBRATION (0x1 << 16)
+
+/* PHY Write Leveling Configuration and Error Status (MPWLGCR) */
+#define WR_LVL_HW_EN 0x00000001
+
+/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
+#define MPR_COMPARE_EN 0x00000001
+
+#define CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG 0x40404040
+
+/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
+#define AUTO_RD_DQS_GATING_CALIBRATION_EN 0x10000000
+
+/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
+#define AUTO_RD_CALIBRATION_EN 0x00000010
+
+#define CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL 0x00030035
+
+#define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT 0x00001067
+
+#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x103e8000
+
+#define START_REFRESH 0x00000001
+
+/* MMDC Core Special Command Register (MDSCR) */
+#define CMD_ADDR_MSB_0x4 (0x4 << 24)
+#define CMD_ADDR_MSB_0x19 (0x19 << 24)
+
+#define CMD_ADDR_LSB_0x84 (0x84 << 16)
+#define CMD_ADDR_LSB_0x8 (0x8 << 16)
+#define CMD_ADDR_LSB_0x4 (0x4 << 16)
+#define CMD_ADDR_LSB_0x30 (0x30 << 16)
+
+#define DISABLE_CFG_REQ 0x0
+#define CONFIGURATION_REQ (0x1 << 15)
+#define WL_EN (0x1 << 9)
+
+#define CMD_NORMAL (0x0 << 4)
+#define CMD_PRECHARGE (0x1 << 4)
+#define CMD_AUTO_REFRESH (0x2 << 4)
+#define CMD_LOAD_MODE_REG (0x3 << 4)
+#define CMD_ZQ_CALIBRATION (0x4 << 4)
+#define CMD_PRECHARGE_BANK_OPEN (0x5 << 4)
+#define CMD_MRR (0x6 << 4)
+
+#define CMD_BANK_ADDR_0 0x0
+#define CMD_BANK_ADDR_1 0x1
+#define CMD_BANK_ADDR_2 0x2
+#define CMD_BANK_ADDR_3 0x3
+#define CMD_BANK_ADDR_4 0x4
+#define CMD_BANK_ADDR_5 0x5
+#define CMD_BANK_ADDR_6 0x6
+#define CMD_BANK_ADDR_7 0x7
+
+/* MMDC Registers */
+struct mmdc_p_regs {
+ u32 mdctl;
+ u32 mdpdc;
+ u32 mdotc;
+ u32 mdcfg0;
+ u32 mdcfg1;
+ u32 mdcfg2;
+ u32 mdmisc;
+ u32 mdscr;
+ u32 mdref;
+ u32 res1[2];
+ u32 mdrwd;
+ u32 mdor;
+ u32 mdmrr;
+ u32 mdcfg3lp;
+ u32 mdmr4;
+ u32 mdasp;
+ u32 res2[239];
+ u32 maarcr;
+ u32 mapsr;
+ u32 maexidr0;
+ u32 maexidr1;
+ u32 madpcr0;
+ u32 madpcr1;
+ u32 madpsr0;
+ u32 madpsr1;
+ u32 madpsr2;
+ u32 madpsr3;
+ u32 madpsr4;
+ u32 madpsr5;
+ u32 masbs0;
+ u32 masbs1;
+ u32 res3[2];
+ u32 magenp;
+ u32 res4[239];
+ u32 mpzqhwctrl;
+ u32 mpzqswctrl;
+ u32 mpwlgcr;
+ u32 mpwldectrl0;
+ u32 mpwldectrl1;
+ u32 mpwldlst;
+ u32 mpodtctrl;
+ u32 mprddqby0dl;
+ u32 mprddqby1dl;
+ u32 mprddqby2dl;
+ u32 mprddqby3dl;
+ u32 res5[4];
+ u32 mpdgctrl0;
+ u32 mpdgctrl1;
+ u32 mpdgdlst0;
+ u32 mprddlctl;
+ u32 mprddlst;
+ u32 mpwrdlctl;
+ u32 mpwrdlst;
+ u32 mpsdctrl;
+ u32 mpzqlp2ctl;
+ u32 mprddlhwctl;
+ u32 mpwrdlhwctl;
+ u32 mprddlhwst0;
+ u32 mprddlhwst1;
+ u32 mpwrdlhwst0;
+ u32 mpwrdlhwst1;
+ u32 mpwlhwerr;
+ u32 mpdghwst0;
+ u32 mpdghwst1;
+ u32 mpdghwst2;
+ u32 mpdghwst3;
+ u32 mppdcmpr1;
+ u32 mppdcmpr2;
+ u32 mpswdar0;
+ u32 mpswdrdr0;
+ u32 mpswdrdr1;
+ u32 mpswdrdr2;
+ u32 mpswdrdr3;
+ u32 mpswdrdr4;
+ u32 mpswdrdr5;
+ u32 mpswdrdr6;
+ u32 mpswdrdr7;
+ u32 mpmur0;
+ u32 mpwrcadl;
+ u32 mpdccr;
+};
+
+#endif /* FSL_MMDC_H */
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index c5e42e6..253eddf 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -59,10 +59,14 @@ struct fsl_xhci {
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
+#elif defined(CONFIG_LS1012A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
#endif
#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [PATCH 06/11][v4] armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC
2016-05-31 15:15 ` [U-Boot] [PATCH 06/11][v4] armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC Prabhakar Kushwaha
@ 2016-05-31 15:43 ` York Sun
0 siblings, 0 replies; 13+ messages in thread
From: York Sun @ 2016-05-31 15:43 UTC (permalink / raw)
To: u-boot
On 05/31/2016 08:17 AM, Prabhakar Kushwaha wrote:
> The QorIQ LS1012A processor, optimized for battery-backed or
> USB-powered, integrates a single ARM Cortex-A53 core with a hardware
> packet forwarding engine and high-speed interfaces to deliver
> line-rate networking performance.
>
> This patch add support of LS1012A SoC along with
> - Update platform & DDR clock read logic as per SVR
> - Define MMDC controller register set.
> - Update LUT base address for PCIe
> - Avoid L3 platform cache compilation
> - Update USB address, errata
> - SerDes table
> - Added CSU IDs for SDHC2, SAI-1 to SAI-4
>
> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
> ---
> Changes for v2: Sending as it is
> Changes for v3: Incorporated York's comments
> - Placed SoC overview in README.soc
> Changes for v4
> - Incorporated Edward L Swarthout's comments
> - Updated DDR speed
> - Added defines for MMDC controller
<snip>
> diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
> new file mode 100644
> index 0000000..31411f7
> --- /dev/null
> +++ b/include/fsl_mmdc.h
> @@ -0,0 +1,164 @@
> +/*
> + * Copyright 2016 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef FSL_MMDC_H
> +#define FSL_MMDC_H
> +
> +#define CONFIG_SYS_MMDC_CORE_ODT_TIMING 0x12554000
> +#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_0 0xbabf7954
> +#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1 0xff328f64
> +#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2 0x01ff00db
> +
> +#define CONFIG_SYS_MMDC_CORE_MISC 0x00000680
> +#define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT 0x00000800
> +#define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY 0x00002000
> +#define CONFIG_SYS_MMDC_PHY_ODT_CTRL 0x0000022a
> +
> +#define CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY 0x00bf1023
> +
> +#define CONFIG_SYS_MMDC_CORE_ADDR_PARTITION 0x0000007f
> +
> +#define CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL 0xa1390003
> +
> +#define FORCE_ZQ_AUTO_CALIBRATION (0x1 << 16)
> +
> +/* PHY Write Leveling Configuration and Error Status (MPWLGCR) */
> +#define WR_LVL_HW_EN 0x00000001
> +
> +/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
> +#define MPR_COMPARE_EN 0x00000001
> +
> +#define CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG 0x40404040
> +
> +/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
> +#define AUTO_RD_DQS_GATING_CALIBRATION_EN 0x10000000
> +
> +/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
> +#define AUTO_RD_CALIBRATION_EN 0x00000010
> +
> +#define CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL 0x00030035
> +
> +#define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT 0x00001067
> +
> +#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x103e8000
> +
> +#define START_REFRESH 0x00000001
Are these values board-specific?
York
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH 07/11][v4] board: freescale: common: Conditionally compile IFC QXIS func
2016-05-31 15:15 [U-Boot] [PATCH 00/11] [v4] armv8: fsl-layerscape: Add support of LS1012A SoC and platform Prabhakar Kushwaha
` (5 preceding siblings ...)
2016-05-31 15:15 ` [U-Boot] [PATCH 06/11][v4] armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC Prabhakar Kushwaha
@ 2016-05-31 15:15 ` Prabhakar Kushwaha
2016-05-31 15:15 ` [U-Boot] [PATCH 08/11][v4] board: freescale: common: Add flag for LBMAP brdcfg reg offset Prabhakar Kushwaha
` (3 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Prabhakar Kushwaha @ 2016-05-31 15:15 UTC (permalink / raw)
To: u-boot
From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Check if qixis supports memory-mapped read/write
before compiling IFC based qixis read/write functions.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---
Chages for v2: New patch in this patch-set
Chages for v3: Sending as it is
Chages for v4: Sending as it is
board/freescale/common/qixis.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 113295f..2e35d41 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -27,6 +27,7 @@ void qixis_write_i2c(unsigned int reg, u8 value)
}
#endif
+#ifdef QIXIS_BASE
u8 qixis_read(unsigned int reg)
{
void *p = (void *)QIXIS_BASE;
@@ -40,6 +41,7 @@ void qixis_write(unsigned int reg, u8 value)
out_8(p + reg, value);
}
+#endif
u16 qixis_read_minor(void)
{
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [PATCH 08/11][v4] board: freescale: common: Add flag for LBMAP brdcfg reg offset
2016-05-31 15:15 [U-Boot] [PATCH 00/11] [v4] armv8: fsl-layerscape: Add support of LS1012A SoC and platform Prabhakar Kushwaha
` (6 preceding siblings ...)
2016-05-31 15:15 ` [U-Boot] [PATCH 07/11][v4] board: freescale: common: Conditionally compile IFC QXIS func Prabhakar Kushwaha
@ 2016-05-31 15:15 ` Prabhakar Kushwaha
2016-05-31 15:15 ` [U-Boot] [PATCH 09/11][v4] armv8: ls1012a: Add support of ls1012aqds board Prabhakar Kushwaha
` (2 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Prabhakar Kushwaha @ 2016-05-31 15:15 UTC (permalink / raw)
To: u-boot
From: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Add QIXIS_LBMAP_BRDCFG_REG to the save offset of LBMAP
configuration register instead of hardcoding it in
set_lbmap() function.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---
Chages for v2: New patch in this patch-set
Chages for v3: Sending as it is
Chages for v4: Sending as it is
board/freescale/common/qixis.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 2e35d41..0db0ed6 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -14,6 +14,13 @@
#include <i2c.h>
#include "qixis.h"
+#ifndef QIXIS_LBMAP_BRDCFG_REG
+/*
+ * For consistency with existing platforms
+ */
+#define QIXIS_LBMAP_BRDCFG_REG 0x00
+#endif
+
#ifdef CONFIG_SYS_I2C_FPGA_ADDR
u8 qixis_read_i2c(unsigned int reg)
{
@@ -144,9 +151,9 @@ static void __maybe_unused set_lbmap(int lbmap)
{
u8 reg;
- reg = QIXIS_READ(brdcfg[0]);
+ reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
- QIXIS_WRITE(brdcfg[0], reg);
+ QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
}
static void __maybe_unused set_rcw_src(int rcw_src)
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [PATCH 09/11][v4] armv8: ls1012a: Add support of ls1012aqds board
2016-05-31 15:15 [U-Boot] [PATCH 00/11] [v4] armv8: fsl-layerscape: Add support of LS1012A SoC and platform Prabhakar Kushwaha
` (7 preceding siblings ...)
2016-05-31 15:15 ` [U-Boot] [PATCH 08/11][v4] board: freescale: common: Add flag for LBMAP brdcfg reg offset Prabhakar Kushwaha
@ 2016-05-31 15:15 ` Prabhakar Kushwaha
2016-05-31 15:15 ` [U-Boot] [PATCH 10/11][v4] armv8: ls1012a: Add support of ls1012ardb board Prabhakar Kushwaha
2016-05-31 15:15 ` [U-Boot] [PATCH 11/11][v4] armv8: ls1012a: Add support of ls1012afrdm board Prabhakar Kushwaha
10 siblings, 0 replies; 13+ messages in thread
From: Prabhakar Kushwaha @ 2016-05-31 15:15 UTC (permalink / raw)
To: u-boot
QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---
Changes for v2:
- Added support of qixis over i2c
- print fpga, board info using qixis
Changes for v3: Incorporated York's comments
Changes for v4: Incorporated Alex and York's comments
- Removed ddr magic number
- updated license
- move PCie, SATA, SDHC define from common to qds.h
- use arch_fixup_fdt
arch/arm/Kconfig | 10 ++
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/fsl-ls1012a-qds.dts | 14 ++
arch/arm/dts/fsl-ls1012a-qds.dtsi | 123 ++++++++++++++
arch/arm/dts/fsl-ls1012a.dtsi | 119 +++++++++++++
board/freescale/ls1012aqds/Kconfig | 15 ++
board/freescale/ls1012aqds/MAINTAINERS | 6 +
board/freescale/ls1012aqds/Makefile | 7 +
board/freescale/ls1012aqds/README | 59 +++++++
board/freescale/ls1012aqds/ls1012aqds.c | 233 ++++++++++++++++++++++++++
board/freescale/ls1012aqds/ls1012aqds_qixis.h | 35 ++++
configs/ls1012aqds_qspi_defconfig | 32 ++++
include/configs/ls1012a_common.h | 145 ++++++++++++++++
include/configs/ls1012aqds.h | 191 +++++++++++++++++++++
14 files changed, 991 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dts
create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dtsi
create mode 100644 arch/arm/dts/fsl-ls1012a.dtsi
create mode 100644 board/freescale/ls1012aqds/Kconfig
create mode 100644 board/freescale/ls1012aqds/MAINTAINERS
create mode 100644 board/freescale/ls1012aqds/Makefile
create mode 100644 board/freescale/ls1012aqds/README
create mode 100644 board/freescale/ls1012aqds/ls1012aqds.c
create mode 100644 board/freescale/ls1012aqds/ls1012aqds_qixis.h
create mode 100644 configs/ls1012aqds_qspi_defconfig
create mode 100644 include/configs/ls1012a_common.h
create mode 100644 include/configs/ls1012aqds.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7a77b6a..30fc32a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -696,6 +696,15 @@ config TARGET_HIKEY
Support for HiKey 96boards platform. It features a HI6220
SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
+config TARGET_LS1012AQDS
+ bool "Support ls1012aqds"
+ select ARM64
+ help
+ Support for Freescale LS1012AQDS platform.
+ The LS1012A Development System (QDS) is a high-performance
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select CPU_V7
@@ -852,6 +861,7 @@ source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
source "board/freescale/ls1043ardb/Kconfig"
+source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/mx23evk/Kconfig"
source "board/freescale/mx25pdk/Kconfig"
source "board/freescale/mx28evk/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 92c7545..47ec7a2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -120,7 +120,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
- fsl-ls1043a-rdb.dtb
+ fsl-ls1043a-rdb.dtb \
+ fsl-ls1012a-qds.dtb
dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dts b/arch/arm/dts/fsl-ls1012a-qds.dts
new file mode 100644
index 0000000..76db36c
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-qds.dts
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-qds.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &duart0;
+ };
+};
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi
new file mode 100644
index 0000000..dde7134
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A QDS Board";
+ aliases {
+ spi0 = &qspi;
+ spi1 = &dspi0;
+ };
+};
+
+&dspi0 {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash0: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <1000000>; /* input clock */
+ };
+
+ dflash1: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3500000>;
+ reg = <1>;
+ };
+
+ dflash2: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3500000>;
+ reg = <2>;
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fl128s at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ pca9547 at 77 {
+ compatible = "philips,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+
+ rtc at 68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ /* IRQ10_B */
+ interrupts = <0 150 0x4>;
+ };
+ };
+
+ i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+
+ ina220 at 40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+
+ ina220 at 41 {
+ compatible = "ti,ina220";
+ reg = <0x41>;
+ shunt-resistor = <1000>;
+ };
+ };
+
+ i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ eeprom at 56 {
+ compatible = "at24,24c512";
+ reg = <0x56>;
+ };
+
+ eeprom at 57 {
+ compatible = "at24,24c512";
+ reg = <0x57>;
+ };
+
+ adt7461a at 4c {
+ compatible = "adt7461a";
+ reg = <0x4c>;
+ };
+ };
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
new file mode 100644
index 0000000..546a87a
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "skeleton64.dtsi"
+
+/ {
+ compatible = "fsl,ls1012a";
+ interrupt-parent = <&gic>;
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ };
+
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+
+ gic: interrupt-controller at 1400000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x1401000 0 0x1000>, /* GICD */
+ <0x0 0x1402000 0 0x2000>, /* GICC */
+ <0x0 0x1404000 0 0x2000>, /* GICH */
+ <0x0 0x1406000 0 0x2000>; /* GICV */
+ interrupts = <1 9 0xf08>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clockgen: clocking at 1ee1000 {
+ compatible = "fsl,ls1012a-clockgen";
+ reg = <0x0 0x1ee1000 0x0 0x1000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ };
+
+ dspi0: dspi at 2100000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <0 64 0x4>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ num-cs = <6>;
+ big-endian;
+ status = "disabled";
+ };
+
+
+ i2c0: i2c at 2180000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <0 56 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at 2190000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <0 57 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ duart0: serial at 21c0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0500 0x0 0x100>;
+ interrupts = <0 54 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart1: serial at 21c0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0600 0x0 0x100>;
+ interrupts = <0 54 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ qspi: quadspi at 1550000 {
+ compatible = "fsl,vf610-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x1550000 0x0 0x10000>,
+ <0x0 0x40000000 0x0 0x4000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ num-cs = <2>;
+ big-endian;
+ status = "disabled";
+ };
+
+ };
+};
diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
new file mode 100644
index 0000000..1257ec8
--- /dev/null
+++ b/board/freescale/ls1012aqds/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1012AQDS
+
+config SYS_BOARD
+ default "ls1012aqds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1012aqds"
+
+endif
diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS
new file mode 100644
index 0000000..27c4aff
--- /dev/null
+++ b/board/freescale/ls1012aqds/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1012AQDS BOARD
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S: Maintained
+F: board/freescale/ls1012aqds/
+F: include/configs/ls1012aqds.h
+F: configs/ls1012aqds_qspi_defconfig
diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile
new file mode 100644
index 0000000..0b813f9
--- /dev/null
+++ b/board/freescale/ls1012aqds/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls1012aqds.o
diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README
new file mode 100644
index 0000000..dee4b30
--- /dev/null
+++ b/board/freescale/ls1012aqds/README
@@ -0,0 +1,59 @@
+Overview
+--------
+QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012AQDS board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A
+SoC overview.
+
+LS1012AQDS board Overview
+-----------------------
+ - SERDES Connections, 4 lanes supporting:
+ - PCI Express - 3.0
+ - SGMII, SGMII 2.5
+ - SATA 3.0
+ - DDR Controller
+ - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ - QSPI Controller
+ - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+ signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
+ emulator
+ - USB 3.0
+ - One USB 3.0 controller with integrated PHY
+ - One high-speed USB 3.0 port
+ - USB 2.0
+ - One USB 2.0 controller with ULPI interface
+ - Two enhanced secure digital host controllers:
+ - SDHC1 controller can be connected to onboard SDHC connector
+ - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - 5 SAI
+ - One SAI port with audio codec SGTL5000:
+ ? Provides MIC bias
+ ? Provides headphone and line output
+ - One SAI port terminated at 2x6 header
+ - Three SAI Tx/Rx ports terminated at 2x3 headers
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash Emu Boot
+b) QSPI Flash 1
+c) QSPI Flash 2
+
+QSPI flash map
+--------------
+Images | Size |QSPI Flash Address
+------------------------------------------
+RCW + PBI | 1MB | 0x4000_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4020_0000
+PPA FIT image | 2MB | 0x4050_0000
+Linux ITB | ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
new file mode 100644
index 0000000..e4e02cb
--- /dev/null
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -0,0 +1,233 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
+#include <ahci.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_mmdc.h>
+#include <spl.h>
+#include <netdev.h>
+
+#include "../common/qixis.h"
+#include "ls1012aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+ int timeout = 1000;
+
+ out_be32(ptr, value);
+
+ while (in_be32(ptr) & bits) {
+ udelay(100);
+ timeout--;
+ }
+ if (timeout <= 0)
+ puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ u8 sw;
+
+ sw = QIXIS_READ(arch);
+ printf("Board Arch: V%d, ", sw >> 4);
+ printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+ sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
+
+ if (sw & QIXIS_LBMAP_ALTBANK)
+ printf("flash: 2\n");
+ else
+ printf("flash: 1\n");
+
+ printf("FPGA: v%d (%s), build %d",
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
+
+ /* the timestamp string contains "\n" at the end */
+ printf(" on %s", qixis_read_time(buf));
+ return 0;
+}
+
+void mmdc_init(void)
+{
+ struct mmdc_p_regs *mmdc =
+ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+ /* configure timing parms */
+ out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+ out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+ out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+ out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+ /* other parms */
+ out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
+ out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+ out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+ out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+ /* out of reset delays */
+ out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+ /* physical parms */
+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+ out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+ /* Enable MMDC */
+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+ /* dram init sequence: update MRs */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x8 | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x4 | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_0x19 | CMD_ADDR_LSB_0x30 |
+ CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_0));
+
+ /* dram init sequence: ZQCL */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_0x4 | CONFIGURATION_REQ |
+ CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+ CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+ FORCE_ZQ_AUTO_CALIBRATION);
+
+ /* Calibrations now: wr lvl */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x84 | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+ set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+ mdelay(1);
+
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x4 | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+ mdelay(1);
+
+ /* Calibrations now: Read DQS gating calibration */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_0x4 | CONFIGURATION_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x4 | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+ out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+ set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* Calibrations now: Read calibration */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_0x4 | CONFIGURATION_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x4 | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+ set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+ AUTO_RD_CALIBRATION_EN,
+ AUTO_RD_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* PD, SR */
+ out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+ out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+ /* refresh scheme */
+ set_wait_for_bits_clear(&mmdc->mdref,
+ CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+ START_REFRESH);
+
+ /* disable CON_REQ */
+ out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+ mmdc_init();
+
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch2_early_init_f();
+
+ return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ u8 mux_sdhc_cd = 0x80;
+
+ i2c_set_bus_num(0);
+
+ i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
+ CONFIG_SYS_CCI400_ADDR;
+
+ /* Set CCI-400 control override register to enable barrier
+ * transaction */
+ out_le32(&cci->ctrl_ord,
+ CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ arch_fixup_fdt(blob);
+
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
new file mode 100644
index 0000000..584f604
--- /dev/null
+++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1043AQDS_QIXIS_H__
+#define __LS1043AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1043AQDS */
+
+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK 0xe0
+#define BRDCFG4_EMISEL_SHIFT 5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66 0x0
+#define QIXIS_SYSCLK_83 0x1
+#define QIXIS_SYSCLK_100 0x2
+#define QIXIS_SYSCLK_125 0x3
+#define QIXIS_SYSCLK_133 0x4
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66 0x0
+#define QIXIS_DDRCLK_100 0x1
+#define QIXIS_DDRCLK_125 0x2
+#define QIXIS_DDRCLK_133 0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100 0x0
+#define QIXIS_SDCLK1_125 0x1
+#define QIXIS_SDCLK1_165 0x2
+#define QIXIS_SDCLK1_100_SP 0x3
+
+#endif
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
new file mode 100644
index 0000000..2bc178c
--- /dev/null
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AQDS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
new file mode 100644
index 0000000..ccd94ec
--- /dev/null
+++ b/include/configs/ls1012a_common.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1012A_COMMON_H
+#define __LS1012A_COMMON_H
+
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_FSL_LSCH2
+#define CONFIG_LS1012A
+#define CONFIG_GICV2
+
+#define CONFIG_SYS_HAS_SERDES
+
+#include <asm/arch/config.h>
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#define CONFIG_SYS_TEXT_BASE 0x40100000
+
+#define CONFIG_SYS_FSL_CLK
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 125000000
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F 1
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 /* 25MHz */
+
+/* CSU */
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+
+/*SPI device */
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 1000000
+#define CONFIG_ENV_SPI_MODE 0x03
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_FSL_SPI_INTERFACE
+#define CONFIG_SF_DATAFLASH
+
+#define CONFIG_FSL_QSPI
+#define QSPI0_AMBA_BASE 0x40000000
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_BAR
+
+#define FSL_QSPI_FLASH_SIZE (1 << 24)
+#define FSL_QSPI_FLASH_NUM 2
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE 0x40000 /* 256KB */
+#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */
+#define CONFIG_ENV_SECT_SIZE 0x40000
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* Command line configuration */
+#define CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE 128
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "initrd_high=0xffffffff\0" \
+ "verify=no\0" \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "loadaddr=0x80100000\0" \
+ "kernel_addr=0x100000\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0xa00000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "console=ttyAMA0,38400n8\0"
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
+ "earlycon=uart8250,mmio,0x21c0500"
+#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
+ "$kernel_start $kernel_size && "\
+ "bootm $kernel_load"
+#define CONFIG_BOOTDELAY 10
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS 64 /* max command args */
+
+#define CONFIG_PANIC_HANG
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1012A_COMMON_H */
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
new file mode 100644
index 0000000..2d84095
--- /dev/null
+++ b/include/configs/ls1012aqds.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1012AQDS_H__
+#define __LS1012AQDS_H__
+
+#include "ls1012a_common.h"
+
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define QIXIS_LBMAP_BRDCFG_REG 0x04
+#define QIXIS_LBMAP_SWITCH 6
+#define QIXIS_LBMAP_MASK 0xf7
+#define QIXIS_LBMAP_SHIFT 0
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x08
+#define QIXIS_RST_CTL_RESET 0x41
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#endif
+
+/*
+ * I2C bus multiplexer
+ */
+#define I2C_MUX_PCA_ADDR_PRI 0x77
+#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR 0x18
+#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_CH7301 0xC
+#define I2C_MUX_CH5 0xD
+#define I2C_MUX_CH7 0xF
+
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+
+/*
+* RTC configuration
+*/
+#define RTC
+#define CONFIG_RTC_PCF8563 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
+#define CONFIG_CMD_DATE
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
+/* DSPI */
+#define CONFIG_FSL_DSPI1
+#define CONFIG_DEFAULT_SPI_BUS 1
+
+#define CONFIG_CMD_SPI
+#define MMAP_DSPI DSPI1_BASE_ADDR
+
+#define CONFIG_SYS_DSPI_CTAR0 1
+
+#define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
+ DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_SST /* cs1 */
+
+#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+ DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
+ DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
+
+#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
+ DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_EON /* cs3 */
+
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_BUS 1
+#define CONFIG_SF_DEFAULT_CS 0
+
+/*
+* USB
+*/
+/* EHCI Support - disbaled by default */
+/*#define CONFIG_HAS_FSL_DR_USB*/
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+/*XHCI Support - enabled by default*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE
+#endif
+
+/* MMC */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controller 1 */
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+#define CONFIG_MISC_INIT_R
+
+#endif /* __LS1012AQDS_H__ */
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [PATCH 10/11][v4] armv8: ls1012a: Add support of ls1012ardb board
2016-05-31 15:15 [U-Boot] [PATCH 00/11] [v4] armv8: fsl-layerscape: Add support of LS1012A SoC and platform Prabhakar Kushwaha
` (8 preceding siblings ...)
2016-05-31 15:15 ` [U-Boot] [PATCH 09/11][v4] armv8: ls1012a: Add support of ls1012aqds board Prabhakar Kushwaha
@ 2016-05-31 15:15 ` Prabhakar Kushwaha
2016-05-31 15:15 ` [U-Boot] [PATCH 11/11][v4] armv8: ls1012a: Add support of ls1012afrdm board Prabhakar Kushwaha
10 siblings, 0 replies; 13+ messages in thread
From: Prabhakar Kushwaha @ 2016-05-31 15:15 UTC (permalink / raw)
To: u-boot
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---
Changes for v2: Sending as it is
Changes for v3: Incorporated York's comments
Changes for v4: Incorporated Alex and York's comments
- removed ddr init magic numbers
- updated file license
- define pcie, sata, sdhc define in rdb.h
- use arch_fixup_fdt
arch/arm/Kconfig | 10 ++
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/fsl-ls1012a-rdb.dts | 16 +++
arch/arm/dts/fsl-ls1012a-rdb.dtsi | 39 ++++++
board/freescale/ls1012ardb/Kconfig | 15 +++
board/freescale/ls1012ardb/MAINTAINERS | 6 +
board/freescale/ls1012ardb/Makefile | 7 +
board/freescale/ls1012ardb/README | 54 ++++++++
board/freescale/ls1012ardb/ls1012ardb.c | 223 ++++++++++++++++++++++++++++++++
configs/ls1012ardb_qspi_defconfig | 32 +++++
include/configs/ls1012ardb.h | 107 +++++++++++++++
11 files changed, 511 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dts
create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dtsi
create mode 100644 board/freescale/ls1012ardb/Kconfig
create mode 100644 board/freescale/ls1012ardb/MAINTAINERS
create mode 100644 board/freescale/ls1012ardb/Makefile
create mode 100644 board/freescale/ls1012ardb/README
create mode 100644 board/freescale/ls1012ardb/ls1012ardb.c
create mode 100644 configs/ls1012ardb_qspi_defconfig
create mode 100644 include/configs/ls1012ardb.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 30fc32a..9be8c2b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -705,6 +705,15 @@ config TARGET_LS1012AQDS
development platform that supports the QorIQ LS1012A
Layerscape Architecture processor.
+config TARGET_LS1012ARDB
+ bool "Support ls1012ardb"
+ select ARM64
+ help
+ Support for Freescale LS1012ARDB platform.
+ The LS1012A Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select CPU_V7
@@ -862,6 +871,7 @@ source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
source "board/freescale/ls1043ardb/Kconfig"
source "board/freescale/ls1012aqds/Kconfig"
+source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/mx23evk/Kconfig"
source "board/freescale/mx25pdk/Kconfig"
source "board/freescale/mx28evk/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 47ec7a2..f021699 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -121,7 +121,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
- fsl-ls1012a-qds.dtb
+ fsl-ls1012a-qds.dtb \
+ fsl-ls1012a-rdb.dtb
dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dts b/arch/arm/dts/fsl-ls1012a-rdb.dts
new file mode 100644
index 0000000..f683812
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-rdb.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-rdb.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &duart0;
+ };
+};
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
new file mode 100644
index 0000000..bf407ae
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A RDB Board";
+ aliases {
+ spi0 = &qspi;
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fl128s at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&duart0 {
+ status = "okay";
+};
diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
new file mode 100644
index 0000000..3f67c28
--- /dev/null
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1012ARDB
+
+config SYS_BOARD
+ default "ls1012ardb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1012ardb"
+
+endif
diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS
new file mode 100644
index 0000000..79a2a7d
--- /dev/null
+++ b/board/freescale/ls1012ardb/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1012ARDB BOARD
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S: Maintained
+F: board/freescale/ls1012ardb/
+F: include/configs/ls1012ardb.h
+F: configs/ls1012ardb_qspi_defconfig
diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
new file mode 100644
index 0000000..05fa9d9
--- /dev/null
+++ b/board/freescale/ls1012ardb/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls1012ardb.o
diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README
new file mode 100644
index 0000000..453b432
--- /dev/null
+++ b/board/freescale/ls1012ardb/README
@@ -0,0 +1,54 @@
+Overview
+--------
+QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012ARDB board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
+
+LS1012ARDB board Overview
+-----------------------
+ - SERDES Connections, 4 lanes supporting:
+ - PCI Express - 3.0
+ - SGMII, SGMII 2.5
+ - SATA 3.0
+ - DDR Controller
+ - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+ signals to
+ - QSPI NOR flash memory (2 virtual banks)
+ - the QSPI emulator.s
+ - USB 3.0
+ - one high-speed USB 2.0/3.0 port.
+ - Two enhanced secure digital host controllers:
+ - SDHC1 controller can be connected to onboard SDHC connector
+ - SDHC2 controller: Three dual 1:4 mux/demux devices,
+ 74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
+ SDIO WiFi, SPI, and Ardiuno shield
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - The LS1012A processor consists of two UART controllers,
+ out of which only UART1 is used on RDB.
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash Emu Boot
+b) QSPI Flash 1
+c) QSPI Flash 2
+
+QSPI flash map
+--------------
+Images | Size |QSPI Flash Address
+------------------------------------------
+RCW + PBI | 1MB | 0x4000_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4020_0000
+PPA FIT image | 2MB | 0x4050_0000
+Linux ITB | ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
new file mode 100644
index 0000000..ceb550a
--- /dev/null
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <ahci.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <environment.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+ int timeout = 1000;
+
+ out_be32(ptr, value);
+
+ while (in_be32(ptr) & bits) {
+ udelay(100);
+ timeout--;
+ }
+ if (timeout <= 0)
+ puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+ u8 in1;
+
+ puts("Board: LS1012ARDB ");
+
+ /* Initialize i2c early for Serial flash bank information */
+ i2c_set_bus_num(0);
+
+ if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
+ printf("Error reading i2c boot information!\n");
+ return 0; /* Don't want to hang() on this error */
+ }
+
+ puts("Version");
+ if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
+ puts(": RevA");
+ else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
+ puts(": RevB");
+ else
+ puts(": unknown");
+
+ printf(", boot from QSPI");
+ if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
+ puts(": emu\n");
+ else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
+ puts(": bank1\n");
+ else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
+ puts(": bank2\n");
+ else
+ puts("unknown\n");
+
+ return 0;
+}
+
+void mmdc_init(void)
+{
+ struct mmdc_p_regs *mmdc =
+ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+ /* configure timing parms */
+ out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+ out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+ out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+ out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+ /* other parms */
+ out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
+ out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+ out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+ out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+ /* out of reset delays */
+ out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+ /* physical parms */
+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+ out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+ /* Enable MMDC */
+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+ /* dram init sequence: update MRs */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x8 | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x4 | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_0x19 | CMD_ADDR_LSB_0x30 |
+ CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_0));
+
+ /* dram init sequence: ZQCL */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_0x4 | CONFIGURATION_REQ |
+ CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+ CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+ FORCE_ZQ_AUTO_CALIBRATION);
+
+ /* Calibrations now: wr lvl */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x84 | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+ set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+ mdelay(1);
+
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x4 | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+ mdelay(1);
+
+ /* Calibrations now: Read DQS gating calibration */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_0x4 | CONFIGURATION_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x4 | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+ out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+ set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* Calibrations now: Read calibration */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_0x4 | CONFIGURATION_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x4 | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+ set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+ AUTO_RD_CALIBRATION_EN,
+ AUTO_RD_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* PD, SR */
+ out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+ out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+ /* refresh scheme */
+ set_wait_for_bits_clear(&mmdc->mdref,
+ CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+ START_REFRESH);
+
+ /* disable CON_REQ */
+ out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+ mmdc_init();
+
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch2_early_init_f();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ /*
+ * Set CCI-400 control override register to enable barrier
+ * transaction
+ */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ arch_fixup_fdt(blob);
+
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
new file mode 100644
index 0000000..456eebd
--- /dev/null
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012ARDB=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
new file mode 100644
index 0000000..f63c66a
--- /dev/null
+++ b/include/configs/ls1012ardb.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1012ARDB_H__
+#define __LS1012ARDB_H__
+
+#include "ls1012a_common.h"
+
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE
+#endif
+
+/*
+ * I2C IO expander
+ */
+
+#define I2C_MUX_IO1_ADDR 0x24
+#define __SW_BOOT_MASK 0xFC
+#define __SW_BOOT_EMU 0x10
+#define __SW_BOOT_BANK1 0x00
+#define __SW_BOOT_BANK2 0x01
+#define __SW_REV_MASK 0x07
+#define __SW_REV_A 0xF8
+#define __SW_REV_B 0xF0
+
+/* MMC */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controller 1 */
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+#endif /* __LS1012ARDB_H__ */
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [U-Boot] [PATCH 11/11][v4] armv8: ls1012a: Add support of ls1012afrdm board
2016-05-31 15:15 [U-Boot] [PATCH 00/11] [v4] armv8: fsl-layerscape: Add support of LS1012A SoC and platform Prabhakar Kushwaha
` (9 preceding siblings ...)
2016-05-31 15:15 ` [U-Boot] [PATCH 10/11][v4] armv8: ls1012a: Add support of ls1012ardb board Prabhakar Kushwaha
@ 2016-05-31 15:15 ` Prabhakar Kushwaha
10 siblings, 0 replies; 13+ messages in thread
From: Prabhakar Kushwaha @ 2016-05-31 15:15 UTC (permalink / raw)
To: u-boot
QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance
development platform, with a complete debugging environment.
The LS1012AFRDM board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---
Changes for v4: New patch in this patch-set
arch/arm/Kconfig | 10 ++
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/fsl-ls1012a-frdm.dts | 16 +++
arch/arm/dts/fsl-ls1012a-frdm.dtsi | 37 ++++++
board/freescale/ls1012afrdm/Kconfig | 15 +++
board/freescale/ls1012afrdm/MAINTAINERS | 6 +
board/freescale/ls1012afrdm/Makefile | 7 ++
board/freescale/ls1012afrdm/README | 58 +++++++++
board/freescale/ls1012afrdm/ls1012afrdm.c | 191 ++++++++++++++++++++++++++++++
configs/ls1012afrdm_qspi_defconfig | 29 +++++
include/configs/ls1012afrdm.h | 44 +++++++
11 files changed, 415 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dts
create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dtsi
create mode 100644 board/freescale/ls1012afrdm/Kconfig
create mode 100644 board/freescale/ls1012afrdm/MAINTAINERS
create mode 100644 board/freescale/ls1012afrdm/Makefile
create mode 100644 board/freescale/ls1012afrdm/README
create mode 100644 board/freescale/ls1012afrdm/ls1012afrdm.c
create mode 100644 configs/ls1012afrdm_qspi_defconfig
create mode 100644 include/configs/ls1012afrdm.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9be8c2b..71169b2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -714,6 +714,15 @@ config TARGET_LS1012ARDB
development platform that supports the QorIQ LS1012A
Layerscape Architecture processor.
+config TARGET_LS1012AFRDM
+ bool "Support ls1012afrdm"
+ select ARM64
+ help
+ Support for Freescale LS1012AFRDM platform.
+ The LS1012A Freedom board (FRDM) is a high-performance
+ development platform that supports the QorIQ LS1012A
+ Layerscape Architecture processor.
+
config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select CPU_V7
@@ -872,6 +881,7 @@ source "board/freescale/ls1021atwr/Kconfig"
source "board/freescale/ls1043ardb/Kconfig"
source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
+source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/mx23evk/Kconfig"
source "board/freescale/mx25pdk/Kconfig"
source "board/freescale/mx28evk/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f021699..e8ad6c6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -122,7 +122,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
fsl-ls1012a-qds.dtb \
- fsl-ls1012a-rdb.dtb
+ fsl-ls1012a-rdb.dtb \
+ fsl-ls1012a-frdm.dtb
dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dts b/arch/arm/dts/fsl-ls1012a-frdm.dts
new file mode 100644
index 0000000..983e599
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-frdm.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-frdm.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &duart0;
+ };
+};
diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
new file mode 100644
index 0000000..25dcdd2
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
@@ -0,0 +1,37 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A FREEDOM Board";
+ aliases {
+ spi0 = &qspi;
+ };
+};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fl128s at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&duart0 {
+ status = "okay";
+};
diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
new file mode 100644
index 0000000..a34521c
--- /dev/null
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1012AFRDM
+
+config SYS_BOARD
+ default "ls1012afrdm"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1012afrdm"
+
+endif
diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS
new file mode 100644
index 0000000..842f86f
--- /dev/null
+++ b/board/freescale/ls1012afrdm/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1012AFRDM BOARD
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S: Maintained
+F: board/freescale/ls1012afrdm/
+F: include/configs/ls1012afrdm.h
+F: configs/ls1012afrdm_qspi_defconfig
diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
new file mode 100644
index 0000000..dbfa2ce
--- /dev/null
+++ b/board/freescale/ls1012afrdm/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls1012afrdm.o
diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README
new file mode 100644
index 0000000..181c461
--- /dev/null
+++ b/board/freescale/ls1012afrdm/README
@@ -0,0 +1,58 @@
+Overview
+--------
+QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development
+platform, with a complete debugging environment. The LS1012AFRDM board
+supports the QorIQ LS1012A processor and is optimized to support the
+high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
+
+ LS1012AFRDM board Overview
+ -----------------------
+ - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
+ - 2 SGMII 1G PHYs
+ - DDR Controller
+ - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ operating at 1.35 V
+ - QSPI
+ - Onboard 512 Mbit QSPI flash memory running at speed up
+ to 108/54 MHz
+ - One high-speed USB 2.0/3.0 port, one USB 2.0 port
+ - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
+ Micro-AB connector.
+ - USB 2.0 port is a debug port (CMSIS DAP) and is configured
+ as a Micro-AB device.
+ - I2C controller
+ - One I2C bus with connectivity to Arduino headers
+ - UART
+ - UART (Console): UART1 (Without flow control) for console
+ - ARM JTAG support
+ - ARM Cortex? 10-pin JTAG connector for LS1012A
+ - CMSIS DAP through K20 microcontroller
+ - SAI Audio interface
+ - One SAI port, SAI 2 with full duplex support
+ - Clocks
+ - 25 MHz crystal for LS1012A
+ - 8 MHz Crystal for K20
+ - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
+ - Power Supplies
+ - 5 V input supply from USB
+ - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
+ other board interfaces
+
+Booting Options
+---------------
+QSPI Flash 1
+
+QSPI flash map
+--------------
+Images | Size |QSPI Flash Address
+------------------------------------------
+RCW + PBI | 1MB | 0x4000_0000
+U-boot | 1MB | 0x4010_0000
+U-boot Env | 1MB | 0x4020_0000
+PPA FIT image | 2MB | 0x4050_0000
+Linux ITB | ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
new file mode 100644
index 0000000..9985cf6
--- /dev/null
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <fsl_csu.h>
+#include <environment.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+ int timeout = 1000;
+
+ out_be32(ptr, value);
+
+ while (in_be32(ptr) & bits) {
+ udelay(100);
+ timeout--;
+ }
+ if (timeout <= 0)
+ puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+ puts("Board: LS1012AFRDM ");
+
+ return 0;
+}
+
+void mmdc_init(void)
+{
+ struct mmdc_p_regs *mmdc =
+ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+ /* configure timing parms */
+ out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+ out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+ out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+ out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+ /* other parms */
+ out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
+ out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+ out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+ out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+ /* out of reset delays */
+ out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+ /* physical parms */
+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+ out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+ /* Enable MMDC */
+ out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+ /* dram init sequence: update MRs */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x8 | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x4 | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_0x19 | CMD_ADDR_LSB_0x30 |
+ CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_0));
+
+ /* dram init sequence: ZQCL */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_0x4 | CONFIGURATION_REQ |
+ CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+ CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+ FORCE_ZQ_AUTO_CALIBRATION);
+
+ /* Calibrations now: wr lvl */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x84 | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+ set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+ mdelay(1);
+
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x4 | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+ out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+ mdelay(1);
+
+ /* Calibrations now: Read DQS gating calibration */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_0x4 | CONFIGURATION_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x4 | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+ out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+ set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* Calibrations now: Read calibration */
+ out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_0x4 | CONFIGURATION_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+ out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_0x4 | CONFIGURATION_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+ out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+ set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+ AUTO_RD_CALIBRATION_EN,
+ AUTO_RD_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* PD, SR */
+ out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+ out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+ /* refresh scheme */
+ set_wait_for_bits_clear(&mmdc->mdref,
+ CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+ START_REFRESH);
+
+ /* disable CON_REQ */
+ out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+ mmdc_init();
+
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch2_early_init_f();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ /*
+ * Set CCI-400 control override register to enable barrier
+ * transaction
+ */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ arch_fixup_fdt(blob);
+
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
new file mode 100644
index 0000000..349758b
--- /dev/null
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AFRDM=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_SYS_NS16550=y
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
new file mode 100644
index 0000000..3e7c430
--- /dev/null
+++ b/include/configs/ls1012afrdm.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1012ARDB_H__
+#define __LS1012ARDB_H__
+
+#include "ls1012a_common.h"
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x04180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x84180000
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE
+#endif
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+#endif /* __LS1012ARDB_H__ */
--
1.9.1
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