[U-Boot] [PATCH v2 00/11] sunxi: PSCI implementation rewrite in C

[U-Boot] [PATCH v2 00/11] sunxi: PSCI implementation rewrite in C

[Chen-Yu Tsai]

Hi everyone,

This series rewrites the Allwinner/sunxi PSCI implementation in C, to make
it easier to maintain and extend for the currently unsupported multi-cluster
SoCs. The SMP code in the BSP kernels are in C. Having the PSCI code in C
as well will make it easier to work on.

To be able to convert the platform bits to C, some common PSCI functions
have to be fixed up according to the ARM calling conventions. Function
declarations are also needed.

This series is based on sunxi/next. Parts of it will likely conflict with
the effort to support PSCI 1.0 on the Freescale LS102xA.

Changes since v1:

  - Add and use helpers for accessing co-processors.

  - Split out power gating/clamping into helpers based on sun7i and the rest.

  - Drop secure section attribute on PSCI common function declarations.

  - Add packed attribute to PRCM and CPUCFG register struct definitions.

  - Only allocate PSCI stack space when PSCI is put in main memory.

  - Make it clear that PSCI stack overwriting normal memory only happens
    when PSCI is put in main memory.

  - Drop "cc" from clobber list.

  - Add comments explaining the need to preserve registers across
    psci_arch_init, and preserve r0 instead of setting it to 0.

Patch 1 fixes up psci_get_cpu_stack_top.

Patch 2 fixes up the PSCI version of v7_flush_dcache_all.

Patch 3 adds function declarations for some of the common PSCI functions.

Patch 4 fixes issues with reserving memory for the secure section.

Patch 5 unifies the CPUCFG_BASE macro names for various sunxi platforms.

Patch 6 adds packed attribute to struct sunxi_prcm_reg.

Patch 7 adds a missing header to cpucfg.h

Patch 8 groups cpu core related controls together into one struct per core.
This makes it straightforward to access the controls by the cpu index.

Patch 9 adds some missing fields to cpucfg, which were used in the assembly
code.

Patch 10 adds the base address for the GIC.

Patch 11 is the new PSCI implementation in C. Almost all of the code is
converted, with the exception of initial setup of the stack.


Regards
ChenYu


Chen-Yu Tsai (11):
  ARM: PSCI: use only r0 and r3 in psci_get_cpu_stack_top()
  ARM: PSCI: save and restore clobbered registers in v7_flush_dcache_all
  ARM: PSCI: export common PSCI function declarations for C code
  ARM: allocate extra space for PSCI stack in secure section during link
    phase
  sunxi: Make CPUCFG_BASE macro names the same across families
  sunxi: Add packed attribute to struct sunxi_prcm_reg
  sunxi: Add missing linux/types.h header for cpucfg_sun6i.h
  sunxi: Group cpu core related controls together
  sunxi: Add CPUCFG debug lock and sun7i cpu power controls
  sunxi: Add base address for GIC
  sunxi: Add PSCI implementation in C

 arch/arm/cpu/armv7/psci.S                          |  20 +-
 arch/arm/cpu/armv7/sunxi/Makefile                  |   7 +-
 arch/arm/cpu/armv7/sunxi/psci.c                    | 269 +++++++++++++++++++++
 arch/arm/cpu/armv7/sunxi/psci_head.S               |  66 +++++
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S              | 262 --------------------
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S              | 237 ------------------
 arch/arm/cpu/u-boot.lds                            |   7 +
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h        |  17 +-
 .../asm/arch-sunxi/{cpucfg_sun6i.h => cpucfg.h}    |  41 ++--
 arch/arm/include/asm/arch-sunxi/prcm.h             |  10 +-
 arch/arm/include/asm/psci.h                        |   8 +
 11 files changed, 404 insertions(+), 540 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/sunxi/psci.c
 create mode 100644 arch/arm/cpu/armv7/sunxi/psci_head.S
 delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun6i.S
 delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun7i.S
 rename arch/arm/include/asm/arch-sunxi/{cpucfg_sun6i.h => cpucfg.h} (67%)

-- 
2.8.1

[U-Boot] [PATCH v2 01/11] ARM: PSCI: use only r0 and r3 in psci_get_cpu_stack_top()

[Chen-Yu Tsai]

For psci_get_cpu_stack_top() to be usable in C code, it must adhere to
the ARM calling conventions. Since it could be called when the stack
is still unavailable, and the entry code to linux also expects r1 and
r2 to remain unchanged, stick to r0 and r3.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/cpu/armv7/psci.S | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index 87c0c0b6f5eb..cdd001fe3fb0 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -196,15 +196,15 @@ ENDPROC(psci_cpu_off_common)
 
 @ expects CPU ID in r0 and returns stack top in r0
 ENTRY(psci_get_cpu_stack_top)
-	mov	r5, #0x400			@ 1kB of stack per CPU
-	mul	r0, r0, r5
-
-	ldr	r5, =psci_text_end		@ end of monitor text
-	add	r5, r5, #0x2000			@ Skip two pages
-	lsr	r5, r5, #12			@ Align to start of page
-	lsl	r5, r5, #12
-	sub	r5, r5, #4			@ reserve 1 word for target PC
-	sub	r0, r5, r0			@ here's our stack!
+	mov	r3, #0x400			@ 1kB of stack per CPU
+	mul	r0, r0, r3
+
+	ldr	r3, =psci_text_end		@ end of monitor text
+	add	r3, r3, #0x2000			@ Skip two pages
+	lsr	r3, r3, #12			@ Align to start of page
+	lsl	r3, r3, #12
+	sub	r3, r3, #4			@ reserve 1 word for target PC
+	sub	r0, r3, r0			@ here's our stack!
 
 	bx	lr
 ENDPROC(psci_get_cpu_stack_top)
-- 
2.8.1

[U-Boot] [PATCH v2 02/11] ARM: PSCI: save and restore clobbered registers in v7_flush_dcache_all

[Chen-Yu Tsai]

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/cpu/armv7/psci.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S
index cdd001fe3fb0..ab408378fcae 100644
--- a/arch/arm/cpu/armv7/psci.S
+++ b/arch/arm/cpu/armv7/psci.S
@@ -110,6 +110,7 @@ ENDPROC(psci_get_cpu_id)
 
 /* Imported from Linux kernel */
 LENTRY(v7_flush_dcache_all)
+	stmfd	sp!, {r4-r5, r7, r9-r11, lr}
 	dmb					@ ensure ordering with previous memory accesses
 	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
 	ands	r3, r0, #0x7000000		@ extract loc from clidr
@@ -153,6 +154,7 @@ finished:
 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
 	dsb	st
 	isb
+	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}
 	bx	lr
 ENDPROC(v7_flush_dcache_all)
 
-- 
2.8.1

[U-Boot] [PATCH v2 03/11] ARM: PSCI: export common PSCI function declarations for C code

[Chen-Yu Tsai]

Some common PSCI functions are written in assembly, but it should be
possible to use them from C code.

Add function declarations for C code to consume.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/include/asm/psci.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 128a606444fe..8b245139cbdb 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -33,6 +33,14 @@
 #define ARM_PSCI_RET_DENIED		(-3)
 
 #ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <linux/compiler.h>
+
+void psci_cpu_entry(void);
+u32 psci_get_cpu_id(void);
+u32 psci_get_cpu_stack_top(int cpu);
+void psci_cpu_off_common(void);
+
 int psci_update_dt(void *fdt);
 void psci_board_init(void);
 #endif /* ! __ASSEMBLY__ */
-- 
2.8.1

[U-Boot] [PATCH v2 03/11] ARM: PSCI: export common PSCI function declarations for C code

[Marc Zyngier]

On 26/05/16 15:01, Chen-Yu Tsai wrote:
> Some common PSCI functions are written in assembly, but it should be
> possible to use them from C code.
> 
> Add function declarations for C code to consume.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  arch/arm/include/asm/psci.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
> index 128a606444fe..8b245139cbdb 100644
> --- a/arch/arm/include/asm/psci.h
> +++ b/arch/arm/include/asm/psci.h
> @@ -33,6 +33,14 @@
>  #define ARM_PSCI_RET_DENIED		(-3)
>  
>  #ifndef __ASSEMBLY__
> +#include <asm/types.h>
> +#include <linux/compiler.h>

nit: you don't need any of these #include.

> +
> +void psci_cpu_entry(void);
> +u32 psci_get_cpu_id(void);
> +u32 psci_get_cpu_stack_top(int cpu);
> +void psci_cpu_off_common(void);
> +
>  int psci_update_dt(void *fdt);
>  void psci_board_init(void);
>  #endif /* ! __ASSEMBLY__ */
> 

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

[U-Boot] [PATCH v2 03/11] ARM: PSCI: export common PSCI function declarations for C code

[Chen-Yu Tsai]

On Fri, May 27, 2016 at 12:49 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> On 26/05/16 15:01, Chen-Yu Tsai wrote:
>> Some common PSCI functions are written in assembly, but it should be
>> possible to use them from C code.
>>
>> Add function declarations for C code to consume.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>  arch/arm/include/asm/psci.h | 8 ++++++++
>>  1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
>> index 128a606444fe..8b245139cbdb 100644
>> --- a/arch/arm/include/asm/psci.h
>> +++ b/arch/arm/include/asm/psci.h
>> @@ -33,6 +33,14 @@
>>  #define ARM_PSCI_RET_DENIED          (-3)
>>
>>  #ifndef __ASSEMBLY__
>> +#include <asm/types.h>
>> +#include <linux/compiler.h>
>
> nit: you don't need any of these #include.

I think <asm/types.h> is still needed for u32?
Unless there's some compiler magic I don't know about.

I'll drop the other one.

ChenYu

>
>> +
>> +void psci_cpu_entry(void);
>> +u32 psci_get_cpu_id(void);
>> +u32 psci_get_cpu_stack_top(int cpu);
>> +void psci_cpu_off_common(void);
>> +
>>  int psci_update_dt(void *fdt);
>>  void psci_board_init(void);
>>  #endif /* ! __ASSEMBLY__ */
>>
>
> Thanks,
>
>         M.
> --
> Jazz is not dead. It just smells funny...

[U-Boot] [PATCH v2 04/11] ARM: allocate extra space for PSCI stack in secure section during link phase

[Chen-Yu Tsai]

The PSCI implementation expects at most 2 pages worth of space reserved
at the end of the secure section for its stacks. If PSCI is relocated to
secure SRAM, then everything is fine. If no secure SRAM is available,
and PSCI remains in main memory, the reserved memory space doesn't cover
the space used by the stack.

If one accesses PSCI after Linux has fully booted, the memory that should
have been reserved for the PSCI stacks may have been used by the kernel
or userspace, and would be corrupted. Observed after effects include the
system hanging or telinit core dumping when trying to reboot. It seems
the init process gets hit the most on my test bed.

This fix allocates the space used by the PSCI stacks in the secure
section by skipping pages in the linker script, but only when there is
no secure SRAM, to avoid bloating the binary.

This fix is only a stop gap. It would be better to rework the stack
allocation mechanism, maybe with proper usage of CONFIG_ macros and an
explicit symbol.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>

squash! ARM: allocate extra space for PSCI stack in secure section during link phase
---
 arch/arm/cpu/u-boot.lds | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index cfab8b041234..0770f8c878d1 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -50,6 +50,7 @@ SECTIONS
 
 #ifndef CONFIG_ARMV7_SECURE_BASE
 #define CONFIG_ARMV7_SECURE_BASE
+#define __ARMV7_ALLOCATE_SECURE_STACK
 #endif
 
 	.__secure_start : {
@@ -67,6 +68,12 @@ SECTIONS
 		SIZEOF(.__secure_start) +
 		SIZEOF(.secure_text);
 
+#ifdef __ARMV7_ALLOCATE_SECURE_STACK
+	/* Align to page boundary and skip 2 pages */
+	. = (. & ~ 0xfff) + 0x2000;
+#undef __ARMV7_ALLOCATE_SECURE_STACK
+#endif
+
 	__secure_end_lma = .;
 	.__secure_end : AT(__secure_end_lma) {
 		*(.__secure_end)
-- 
2.8.1

[U-Boot] [PATCH v2 04/11] ARM: allocate extra space for PSCI stack in secure section during link phase

[Marc Zyngier]

On 26/05/16 15:01, Chen-Yu Tsai wrote:
> The PSCI implementation expects at most 2 pages worth of space reserved
> at the end of the secure section for its stacks. If PSCI is relocated to
> secure SRAM, then everything is fine. If no secure SRAM is available,
> and PSCI remains in main memory, the reserved memory space doesn't cover
> the space used by the stack.
> 
> If one accesses PSCI after Linux has fully booted, the memory that should
> have been reserved for the PSCI stacks may have been used by the kernel
> or userspace, and would be corrupted. Observed after effects include the
> system hanging or telinit core dumping when trying to reboot. It seems
> the init process gets hit the most on my test bed.
> 
> This fix allocates the space used by the PSCI stacks in the secure
> section by skipping pages in the linker script, but only when there is
> no secure SRAM, to avoid bloating the binary.
> 
> This fix is only a stop gap. It would be better to rework the stack
> allocation mechanism, maybe with proper usage of CONFIG_ macros and an
> explicit symbol.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> 
> squash! ARM: allocate extra space for PSCI stack in secure section during link phase
> ---
>  arch/arm/cpu/u-boot.lds | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
> index cfab8b041234..0770f8c878d1 100644
> --- a/arch/arm/cpu/u-boot.lds
> +++ b/arch/arm/cpu/u-boot.lds
> @@ -50,6 +50,7 @@ SECTIONS
>  
>  #ifndef CONFIG_ARMV7_SECURE_BASE
>  #define CONFIG_ARMV7_SECURE_BASE
> +#define __ARMV7_ALLOCATE_SECURE_STACK

ALLOCATE_SECURE_STACK is a bit of a misnomer, because nothing is secure
at all there (it is in RAM).

Something like PSCI_RAM_STACK would be more accurate.

>  #endif
>  
>  	.__secure_start : {
> @@ -67,6 +68,12 @@ SECTIONS
>  		SIZEOF(.__secure_start) +
>  		SIZEOF(.secure_text);
>  
> +#ifdef __ARMV7_ALLOCATE_SECURE_STACK
> +	/* Align to page boundary and skip 2 pages */
> +	. = (. & ~ 0xfff) + 0x2000;
> +#undef __ARMV7_ALLOCATE_SECURE_STACK
> +#endif
> +
>  	__secure_end_lma = .;
>  	.__secure_end : AT(__secure_end_lma) {
>  		*(.__secure_end)
> 

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

[U-Boot] [PATCH v2 05/11] sunxi: Make CPUCFG_BASE macro names the same across families

[Chen-Yu Tsai]

Use SUNXI_CPUCFG_BASE across all families. This makes writing common
PSCI code easier.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S       | 16 ++++++++--------
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S       |  8 ++++----
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 15 +++++++++++++--
 3 files changed, 25 insertions(+), 14 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 90b5bfd35947..9752550dea35 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -73,8 +73,8 @@ psci_fiq_enter:
 	lsr	r9, r9, #10
 	and	r9, r9, #0xf
 
-	movw	r8, #(SUN6I_CPUCFG_BASE & 0xffff)
-	movt	r8, #(SUN6I_CPUCFG_BASE >> 16)
+	movw	r8, #(SUNXI_CPUCFG_BASE & 0xffff)
+	movt	r8, #(SUNXI_CPUCFG_BASE >> 16)
 
 	@ Wait for the core to enter WFI
 	lsl	r11, r9, #6		@ x64
@@ -114,8 +114,8 @@ psci_fiq_enter:
 	str	r10, [r12, #0x140]
 #endif
 
-	movw	r8, #(SUN6I_CPUCFG_BASE & 0xffff)
-	movt	r8, #(SUN6I_CPUCFG_BASE >> 16)
+	movw	r8, #(SUNXI_CPUCFG_BASE & 0xffff)
+	movt	r8, #(SUNXI_CPUCFG_BASE >> 16)
 
 	@ Unlock CPU
 	ldr	r10, [r8, #0x1e4]
@@ -139,8 +139,8 @@ psci_cpu_on:
 	str	r2, [r0]		@ store target PC at stack top
 	dsb
 
-	movw	r0, #(SUN6I_CPUCFG_BASE & 0xffff)
-	movt	r0, #(SUN6I_CPUCFG_BASE >> 16)
+	movw	r0, #(SUNXI_CPUCFG_BASE & 0xffff)
+	movt	r0, #(SUNXI_CPUCFG_BASE >> 16)
 
 	@ CPU mask
 	and	r1, r1, #3	@ only care about first cluster
@@ -189,8 +189,8 @@ psci_cpu_on:
 	str	r6, [r0, #0x100]
 
 	@ re-calculate CPU control register address
-	movw	r0, #(SUN6I_CPUCFG_BASE & 0xffff)
-	movt	r0, #(SUN6I_CPUCFG_BASE >> 16)
+	movw	r0, #(SUNXI_CPUCFG_BASE & 0xffff)
+	movt	r0, #(SUNXI_CPUCFG_BASE >> 16)
 
 	@ Deassert reset on target CPU
 	mov	r6, #3
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index e15d587f2901..ac8ebf888a4a 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -73,8 +73,8 @@ psci_fiq_enter:
 	lsr	r9, r9, #10
 	and	r9, r9, #0xf
 
-	movw	r8, #(SUN7I_CPUCFG_BASE & 0xffff)
-	movt	r8, #(SUN7I_CPUCFG_BASE >> 16)
+	movw	r8, #(SUNXI_CPUCFG_BASE & 0xffff)
+	movt	r8, #(SUNXI_CPUCFG_BASE >> 16)
 
 	@ Wait for the core to enter WFI
 	lsl	r11, r9, #6		@ x64
@@ -128,8 +128,8 @@ psci_cpu_on:
 	str	r2, [r0]		@ store target PC at stack top
 	dsb
 
-	movw	r0, #(SUN7I_CPUCFG_BASE & 0xffff)
-	movt	r0, #(SUN7I_CPUCFG_BASE >> 16)
+	movw	r0, #(SUNXI_CPUCFG_BASE & 0xffff)
+	movt	r0, #(SUNXI_CPUCFG_BASE >> 16)
 
 	@ CPU mask
 	and	r1, r1, #3	@ only care about first cluster
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 65c0441fe8a2..47e327e71f84 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -18,6 +18,10 @@
 #define SUNXI_SRAM_D_BASE		0x00010000	/* 4 kiB */
 #define SUNXI_SRAM_B_BASE		0x00020000	/* 64 kiB (secure) */
 
+#ifdef CONFIG_MACH_SUN8I_A83T
+#define SUNXI_CPUCFG_BASE		0x01700000
+#endif
+
 #define SUNXI_SRAMC_BASE		0x01c00000
 #define SUNXI_DRAMC_BASE		0x01c01000
 #define SUNXI_DMA_BASE			0x01c02000
@@ -94,7 +98,10 @@
 
 #define SUNXI_TP_BASE			0x01c25000
 #define SUNXI_PMU_BASE			0x01c25400
-#define SUN7I_CPUCFG_BASE              0x01c25c00
+
+#ifdef CONFIG_MACH_SUN7I
+#define SUNXI_CPUCFG_BASE		0x01c25c00
+#endif
 
 #define SUNXI_UART0_BASE		0x01c28000
 #define SUNXI_UART1_BASE		0x01c28400
@@ -148,7 +155,11 @@
 
 #define SUNXI_RTC_BASE			0x01f00000
 #define SUNXI_PRCM_BASE			0x01f01400
-#define SUN6I_CPUCFG_BASE		0x01f01c00
+
+#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN8I_A83T
+#define SUNXI_CPUCFG_BASE		0x01f01c00
+#endif
+
 #define SUNXI_R_TWI_BASE		0x01f02400
 #define SUNXI_R_UART_BASE		0x01f02800
 #define SUNXI_R_PIO_BASE		0x01f02c00
-- 
2.8.1

[U-Boot] [PATCH v2 06/11] sunxi: Add packed attribute to struct sunxi_prcm_reg

[Chen-Yu Tsai]

struct sunxi_prcm_reg is a representation of the PRCM registers. Add
the packed attribute to prevent the compiler from doing funny things.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/include/asm/arch-sunxi/prcm.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
index 556c1af60058..34e01e825df2 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -197,7 +197,9 @@
 #define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff)
 
 #ifndef __ASSEMBLY__
-struct sunxi_prcm_reg {
+#include <linux/compiler.h>
+
+struct __packed sunxi_prcm_reg {
 	u32 cpus_cfg;		/* 0x000 */
 	u8 res0[0x8];		/* 0x004 */
 	u32 apb0_ratio;		/* 0x00c */
-- 
2.8.1

[U-Boot] [PATCH v2 07/11] sunxi: Add missing linux/types.h header for cpucfg_sun6i.h

[Chen-Yu Tsai]

cpucfg_sun6i.h includes a register definition for the CPUCFG register
block. The types used are u32 and u8, which are defined in linux/types.h.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h b/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
index e2a29cb1818e..6885a972ce0b 100644
--- a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
@@ -9,6 +9,8 @@
 #ifndef _SUNXI_CPUCFG_H
 #define _SUNXI_CPUCFG_H
 
+#include <linux/types.h>
+
 #ifndef __ASSEMBLY__
 
 struct sunxi_cpucfg_reg {
-- 
2.8.1

[U-Boot] [PATCH v2 08/11] sunxi: Group cpu core related controls together

[Chen-Yu Tsai]

Instead of listing individual registers for controls to each processor
core, list them as an array of registers. This makes accessing controls
by core index easier.

Also rename "cpucfg_sun6i.h" (which was unused anyway) to the more generic
"cpucfg.h", and add packed attribute to struct sunxi_cpucfg.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 .../asm/arch-sunxi/{cpucfg_sun6i.h => cpucfg.h}    | 34 +++++++++-------------
 arch/arm/include/asm/arch-sunxi/prcm.h             |  6 ++--
 2 files changed, 16 insertions(+), 24 deletions(-)
 rename arch/arm/include/asm/arch-sunxi/{cpucfg_sun6i.h => cpucfg.h} (68%)

diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h b/arch/arm/include/asm/arch-sunxi/cpucfg.h
similarity index 68%
rename from arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
rename to arch/arm/include/asm/arch-sunxi/cpucfg.h
index 6885a972ce0b..f6d2f21d9d24 100644
--- a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg.h
@@ -9,37 +9,31 @@
 #ifndef _SUNXI_CPUCFG_H
 #define _SUNXI_CPUCFG_H
 
+#include <linux/compiler.h>
 #include <linux/types.h>
 
 #ifndef __ASSEMBLY__
 
-struct sunxi_cpucfg_reg {
+struct __packed sunxi_cpucfg_cpu {
+	u32 rst;		/* base + 0x0 */
+	u32 ctrl;		/* base + 0x4 */
+	u32 status;		/* base + 0x8 */
+	u8 res[0x34];		/* base + 0xc */
+};
+
+struct __packed sunxi_cpucfg_reg {
 	u8 res0[0x40];		/* 0x000 */
-	u32 cpu0_rst;		/* 0x040 */
-	u32 cpu0_ctrl;		/* 0x044 */
-	u32 cpu0_status;	/* 0x048 */
-	u8 res1[0x34];		/* 0x04c */
-	u32 cpu1_rst;		/* 0x080 */
-	u32 cpu1_ctrl;		/* 0x084 */
-	u32 cpu1_status;	/* 0x088 */
-	u8 res2[0x34];		/* 0x08c */
-	u32 cpu2_rst;		/* 0x0c0 */
-	u32 cpu2_ctrl;		/* 0x0c4 */
-	u32 cpu2_status;	/* 0x0c8 */
-	u8 res3[0x34];		/* 0x0cc */
-	u32 cpu3_rst;		/* 0x100 */
-	u32 cpu3_ctrl;		/* 0x104 */
-	u32 cpu3_status;	/* 0x108 */
-	u8 res4[0x78];		/* 0x10c */
+	struct sunxi_cpucfg_cpu cpu[4];		/* 0x040 */
+	u8 res1[0x44];		/* 0x140 */
 	u32 gen_ctrl;		/* 0x184 */
 	u32 l2_status;		/* 0x188 */
-	u8 res5[0x4];		/* 0x18c */
+	u8 res2[0x4];		/* 0x18c */
 	u32 event_in;		/* 0x190 */
-	u8 res6[0xc];		/* 0x194 */
+	u8 res3[0xc];		/* 0x194 */
 	u32 super_standy_flag;	/* 0x1a0 */
 	u32 priv0;		/* 0x1a4 */
 	u32 priv1;		/* 0x1a8 */
-	u8 res7[0x54];		/* 0x1ac */
+	u8 res4[0x54];		/* 0x1ac */
 	u32 idle_cnt0_low;	/* 0x200 */
 	u32 idle_cnt0_high;	/* 0x204 */
 	u32 idle_cnt0_ctrl;	/* 0x208 */
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
index 34e01e825df2..ae3880b13bdf 100644
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -227,10 +227,8 @@ struct __packed sunxi_prcm_reg {
 	u32 gpu_pwroff;		/* 0x118 */
 	u8 res9[0x4];		/* 0x11c */
 	u32 vdd_pwr_reset;	/* 0x120 */
-	u8 res10[0x20];		/* 0x124 */
-	u32 cpu1_pwr_clamp;	/* 0x144 */
-	u32 cpu2_pwr_clamp;	/* 0x148 */
-	u32 cpu3_pwr_clamp;	/* 0x14c */
+	u8 res10[0x1c];		/* 0x124 */
+	u32 cpu_pwr_clamp[4];	/* 0x140 but first one is actually unused */
 	u8 res11[0x30];		/* 0x150 */
 	u32 dram_pwr;		/* 0x180 */
 	u8 res12[0xc];		/* 0x184 */
-- 
2.8.1

[U-Boot] [PATCH v2 09/11] sunxi: Add CPUCFG debug lock and sun7i cpu power controls

[Chen-Yu Tsai]

CPUCFG has an unlisted debug control register, which is used to disable
external debug access.

Also, sun7i secondary core power controls are in CPUCFG, as there's no
separate PRCM block.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/include/asm/arch-sunxi/cpucfg.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg.h b/arch/arm/include/asm/arch-sunxi/cpucfg.h
index f6d2f21d9d24..297cdd28c060 100644
--- a/arch/arm/include/asm/arch-sunxi/cpucfg.h
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg.h
@@ -33,7 +33,12 @@ struct __packed sunxi_cpucfg_reg {
 	u32 super_standy_flag;	/* 0x1a0 */
 	u32 priv0;		/* 0x1a4 */
 	u32 priv1;		/* 0x1a8 */
-	u8 res4[0x54];		/* 0x1ac */
+	u8 res4[0x4];		/* 0x1ac */
+	u32 cpu1_pwr_clamp;	/* 0x1b0 sun7i only */
+	u32 cpu1_pwroff;	/* 0x1b4 sun7i only */
+	u8 res5[0x2c];		/* 0x1b8 */
+	u32 dbg_ctrl1;		/* 0x1e4 */
+	u8 res6[0x18];		/* 0x1e8 */
 	u32 idle_cnt0_low;	/* 0x200 */
 	u32 idle_cnt0_high;	/* 0x204 */
 	u32 idle_cnt0_ctrl;	/* 0x208 */
-- 
2.8.1

[U-Boot] [PATCH v2 10/11] sunxi: Add base address for GIC

[Chen-Yu Tsai]

Instead of hardcoding the GIC addresses in the PSCI implementation,
provide a base address in the cpu header.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S       | 4 ++--
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S       | 4 ++--
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 2 ++
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 9752550dea35..95fdb0e58874 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -42,8 +42,8 @@
 
 #define	ONE_MS			(CONFIG_TIMER_CLK_FREQ / 1000)
 #define	TEN_MS			(10 * ONE_MS)
-#define	GICD_BASE		0x1c81000
-#define	GICC_BASE		0x1c82000
+#define	GICD_BASE		(SUNXI_GIC400_BASE +  0x1000)
+#define	GICC_BASE		(SUNXI_GIC400_BASE +  0x2000)
 
 .globl	psci_fiq_enter
 psci_fiq_enter:
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
index ac8ebf888a4a..87bbd725f0b3 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
@@ -42,8 +42,8 @@
 
 #define	ONE_MS			(CONFIG_TIMER_CLK_FREQ / 1000)
 #define	TEN_MS			(10 * ONE_MS)
-#define	GICD_BASE		0x1c81000
-#define	GICC_BASE		0x1c82000
+#define	GICD_BASE		(SUNXI_GIC400_BASE +  0x1000)
+#define	GICC_BASE		(SUNXI_GIC400_BASE +  0x2000)
 
 .globl	psci_fiq_enter
 psci_fiq_enter:
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 47e327e71f84..c5e9d88bab5c 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -143,6 +143,8 @@
 #define SUNXI_DRAM_PHY0_BASE		0x01c65000
 #define SUNXI_DRAM_PHY1_BASE		0x01c66000
 
+#define SUNXI_GIC400_BASE		0x01c80000
+
 /* module sram */
 #define SUNXI_SRAM_C_BASE		0x01d00000
 
-- 
2.8.1

[U-Boot] [PATCH v2 11/11] sunxi: Add PSCI implementation in C

[Chen-Yu Tsai]

To make the PSCI backend more maintainable and easier to port to newer
SoCs, rewrite the current PSCI implementation in C.

Some inline assembly bits are required to access coprocessor registers.
PSCI stack setup is the only part left completely in assembly. In theory
this part could be split out of psci_arch_init into a separate common
function, and psci_arch_init could be completely in C.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/cpu/armv7/sunxi/Makefile     |   7 +-
 arch/arm/cpu/armv7/sunxi/psci.c       | 269 ++++++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/sunxi/psci_head.S  |  66 +++++++++
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 262 ---------------------------------
 arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 237 ------------------------------
 5 files changed, 337 insertions(+), 504 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/sunxi/psci.c
 create mode 100644 arch/arm/cpu/armv7/sunxi/psci_head.S
 delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun6i.S
 delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun7i.S

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 4d2274a38ed1..c2085101685b 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -13,11 +13,8 @@ obj-$(CONFIG_MACH_SUN6I)	+= tzpc.o
 obj-$(CONFIG_MACH_SUN8I_H3)	+= tzpc.o
 
 ifndef CONFIG_SPL_BUILD
-ifdef CONFIG_ARMV7_PSCI
-obj-$(CONFIG_MACH_SUN6I)	+= psci_sun6i.o
-obj-$(CONFIG_MACH_SUN7I)	+= psci_sun7i.o
-obj-$(CONFIG_MACH_SUN8I)	+= psci_sun6i.o
-endif
+obj-$(CONFIG_ARMV7_PSCI)	+= psci.o
+obj-$(CONFIG_ARMV7_PSCI)	+= psci_head.o
 endif
 
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
new file mode 100644
index 000000000000..f0c151a349c8
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (C) 2016
+ * Author: Chen-Yu Tsai <wens@csie.org>
+ *
+ * Based on assembly code by Marc Zyngier <marc.zyngier@arm.com>,
+ * which was based on code by Carl van Schaik <carl@ok-labs.com>.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+#include <config.h>
+#include <common.h>
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/cpucfg.h>
+#include <asm/arch/prcm.h>
+#include <asm/armv7.h>
+#include <asm/gic.h>
+#include <asm/io.h>
+#include <asm/psci.h>
+#include <asm/system.h>
+
+#include <linux/bitops.h>
+
+#define __secure	__attribute__ ((section ("._secure.text")))
+#define __irq		__attribute__ ((interrupt ("IRQ")))
+
+#define	GICD_BASE	(SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
+#define	GICC_BASE	(SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
+
+static void cp15_write_cntp_tval(u32 tval)
+{
+	asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
+}
+
+static void cp15_write_cntp_ctl(u32 val)
+{
+	asm volatile ("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
+}
+
+static u32 cp15_read_cntp_ctl(void)
+{
+	u32 val;
+
+	asm volatile ("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+
+	return val;
+}
+
+static void __secure __mdelay(u32 ms)
+{
+	u32 reg = DIV_ROUND_UP(CONFIG_TIMER_CLK_FREQ, ms);
+
+	cp15_write_cntp_tval(reg);
+	ISB;
+	cp15_write_cntp_ctl(3);
+
+	do {
+		ISB;
+		reg = cp15_read_cntp_ctl();
+	} while (!(reg & BIT(2)));
+
+	cp15_write_cntp_ctl(0);
+}
+
+#ifdef CONFIG_MACH_SUN7I
+/* sun7i (A20) is different from other single cluster SoCs */
+static void sunxi_cpu_set_power(int __always_unused cpu, bool on)
+{
+	struct sunxi_cpucfg_reg *cpucfg =
+		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+
+	if (on) {
+		/* Release power clamp */
+		u32 tmp = 0x1ff;
+		do {
+			tmp >>= 1;
+			writel(tmp, &cpucfg->cpu1_pwr_clamp);
+		} while (tmp);
+
+		__mdelay(10);
+
+		/* Clear power gating */
+		clrbits_le32(&cpucfg->cpu1_pwroff, BIT(0));
+	} else {
+		/* Set power gating */
+		setbits_le32(&cpucfg->cpu1_pwroff, BIT(0));
+
+		/* Activate power clamp */
+		writel(0xff, &cpucfg->cpu1_pwr_clamp);
+	}
+}
+#else /* ! CONFIG_MACH_SUN7I */
+static void sunxi_cpu_set_power(int cpu, bool on)
+{
+	struct sunxi_prcm_reg *prcm =
+		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+	if (on) {
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
+		/* Release power clamp (A31 & H3 only) */
+		u32 tmp = 0x1ff;
+		do {
+			tmp >>= 1;
+			writel(tmp, &prcm->cpu_pwr_clamp[cpu]);
+		} while (tmp);
+#endif
+
+		__mdelay(10);
+
+		/* Clear power gating */
+		clrbits_le32(&prcm->cpu_pwroff, BIT(cpu));
+	} else {
+		/* Set power gating */
+		setbits_le32(&prcm->cpu_pwroff, BIT(cpu));
+
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
+		/* Activate power clamp (A31 & H3 only) */
+		writel(0xff, &prcm->cpu_pwr_clamp[cpu]);
+#endif
+	}
+}
+#endif /* CONFIG_MACH_SUN7I */
+
+void __secure sunxi_cpu_power_off(u32 cpuid)
+{
+	struct sunxi_cpucfg_reg *cpucfg =
+		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+	u32 cpu = cpuid & 0x3;
+
+	/* Wait for the core to enter WFI */
+	while (1) {
+		if (readl(&cpucfg->cpu[cpu].status) & BIT(2))
+			break;
+		__mdelay(1);
+	}
+
+	/* Assert reset on target CPU */
+	writel(0, &cpucfg->cpu[cpu].rst);
+
+	/* Lock CPU (Disable external debug access) */
+	clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+
+	/* Power down CPU */
+	sunxi_cpu_set_power(cpuid, false);
+
+	/* Unlock CPU (Disable external debug access) */
+	setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+}
+
+static u32 cp15_read_scr(void)
+{
+	u32 scr;
+
+	asm volatile ("mrc p15, 0, %0, c1, c1, 0" : "=r" (scr));
+
+	return scr;
+}
+
+static void cp15_write_scr(u32 scr)
+{
+	asm volatile ("mcr p15, 0, %0, c1, c1, 0" : : "r" (scr));
+}
+
+/*
+ * Although this is an FIQ handler, the FIQ is processed in monitor mode,
+ * which means there's no FIQ banked registers. This is the same as IRQ
+ * mode, so use the IRQ attribute to ask the compiler to handler entry
+ * and return.
+ */
+void __secure __irq psci_fiq_enter(void)
+{
+	u32 scr, reg, cpu;
+
+	/* Switch to secure mode */
+	scr = cp15_read_scr();
+	cp15_write_scr(scr & ~BIT(0));
+	ISB;
+
+	/* Validate reason based on IAR and acknowledge */
+	reg = readl(GICC_BASE + GICC_IAR);
+
+	/* Skip spurious interrupts 1022 and 1023 */
+	if (reg == 1023 || reg == 1022)
+		goto out;
+
+	/* Acknowledge interrupt */
+	writel(reg, GICC_BASE + GICC_EOIR);
+	DSB;
+
+	/* Get CPU number */
+	cpu = (reg >> 10) & 0x7;
+
+	/* Power off the CPU */
+	sunxi_cpu_power_off(cpu);
+
+out:
+	/* Restore security level */
+	cp15_write_scr(scr);
+}
+
+int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc)
+{
+	struct sunxi_cpucfg_reg *cpucfg =
+		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+	u32 cpu = (mpidr & 0x3);
+
+	/* store target PC at target CPU stack top */
+	writel(pc, psci_get_cpu_stack_top(cpu));
+	DSB;
+
+	/* Set secondary core power on PC */
+	writel((u32)&psci_cpu_entry, &cpucfg->priv0);
+
+	/* Assert reset on target CPU */
+	writel(0, &cpucfg->cpu[cpu].rst);
+
+	/* Invalidate L1 cache */
+	clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu));
+
+	/* Lock CPU (Disable external debug access) */
+	clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+
+	/* Power up target CPU */
+	sunxi_cpu_set_power(cpu, true);
+
+	/* De-assert reset on target CPU */
+	writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
+
+	/* Unlock CPU (Disable external debug access) */
+	setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
+
+	return ARM_PSCI_RET_SUCCESS;
+}
+
+void __secure psci_cpu_off(void)
+{
+	psci_cpu_off_common();
+
+	/* Ask CPU0 via SGI15 to pull the rug... */
+	writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
+	DSB;
+
+	/* Wait to be turned off */
+	while (1)
+		wfi();
+}
+
+void __secure sunxi_gic_init(void)
+{
+	u32 reg;
+
+	/* SGI15 as Group-0 */
+	clrbits_le32(GICD_BASE + GICD_IGROUPRn, BIT(15));
+
+	/* Set SGI15 priority to 0 */
+	writeb(0, GICD_BASE + GICD_IPRIORITYRn + 15);
+
+	/* Be cool with non-secure */
+	writel(0xff, GICC_BASE + GICC_PMR);
+
+	/* Switch FIQEn on */
+	setbits_le32(GICC_BASE + GICC_CTLR, BIT(3));
+
+	reg = cp15_read_scr();
+	reg |= BIT(2);  /* Enable FIQ in monitor mode */
+	reg &= ~BIT(0); /* Secure mode */
+	cp15_write_scr(reg);
+	ISB;
+}
diff --git a/arch/arm/cpu/armv7/sunxi/psci_head.S b/arch/arm/cpu/armv7/sunxi/psci_head.S
new file mode 100644
index 000000000000..8fa823d1df3a
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/psci_head.S
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Based on code by Carl van Schaik <carl@ok-labs.com>.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#include <asm/arch-armv7/generictimer.h>
+#include <asm/gic.h>
+#include <asm/macro.h>
+#include <asm/psci.h>
+#include <asm/arch/cpu.h>
+
+/*
+ * Memory layout:
+ *
+ * SECURE_RAM to text_end :
+ *	._secure_text section
+ * text_end to ALIGN_PAGE(text_end):
+ *	nothing
+ * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
+ *	1kB of stack per CPU (4 CPUs max).
+ */
+
+	.pushsection ._secure.text, "ax"
+
+	.arch_extension sec
+
+#define	GICD_BASE		(SUNXI_GIC400_BASE +  0x1000)
+#define	GICC_BASE		(SUNXI_GIC400_BASE +  0x2000)
+
+@ {r0, r1, r2, ip} from _do_nonsec_entry(kernel_entry, 0, machid, r2) in
+@ arch/arm/lib/bootm.c:boot_jump_linux() must remain unchanged across
+@ this function.
+ENTRY(psci_arch_init)
+	mov	r6, lr
+	mov	r7, r0
+	bl	psci_get_cpu_id		@ CPU ID => r0
+	bl	psci_get_cpu_stack_top	@ stack top => r0
+	sub	r0, r0, #4		@ Save space for target PC
+	mov	sp, r0
+	mov	r0, r7
+	mov	lr, r6
+
+	push	{r0, r1, r2, ip, lr}
+	bl	sunxi_gic_init
+	pop	{r0, r1, r2, ip, pc}
+ENDPROC(psci_arch_init)
+
+ENTRY(psci_text_end)
+	.popsection
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
deleted file mode 100644
index 95fdb0e58874..000000000000
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ /dev/null
@@ -1,262 +0,0 @@
-/*
- * Copyright (C) 2015 - Chen-Yu Tsai
- * Author: Chen-Yu Tsai <wens@csie.org>
- *
- * Based on psci_sun7i.S by Marc Zyngier <marc.zyngier@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <config.h>
-
-#include <asm/arch-armv7/generictimer.h>
-#include <asm/gic.h>
-#include <asm/macro.h>
-#include <asm/psci.h>
-#include <asm/arch/cpu.h>
-
-/*
- * Memory layout:
- *
- * SECURE_RAM to text_end :
- *	._secure_text section
- * text_end to ALIGN_PAGE(text_end):
- *	nothing
- * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
- *	1kB of stack per CPU (4 CPUs max).
- */
-
-	.pushsection ._secure.text, "ax"
-
-	.arch_extension sec
-
-#define	ONE_MS			(CONFIG_TIMER_CLK_FREQ / 1000)
-#define	TEN_MS			(10 * ONE_MS)
-#define	GICD_BASE		(SUNXI_GIC400_BASE +  0x1000)
-#define	GICC_BASE		(SUNXI_GIC400_BASE +  0x2000)
-
-.globl	psci_fiq_enter
-psci_fiq_enter:
-	push	{r0-r12}
-
-	@ Switch to secure
-	mrc	p15, 0, r7, c1, c1, 0
-	bic	r8, r7, #1
-	mcr	p15, 0, r8, c1, c1, 0
-	isb
-
-	@ Validate reason based on IAR and acknowledge
-	movw	r8, #(GICC_BASE & 0xffff)
-	movt	r8, #(GICC_BASE >> 16)
-	ldr	r9, [r8, #GICC_IAR]
-	movw	r10, #0x3ff
-	movt	r10, #0
-	cmp	r9, r10			@ skip spurious interrupt 1023
-	beq	out
-	movw	r10, #0x3fe		@ ...and 1022
-	cmp	r9, r10
-	beq	out
-	str	r9, [r8, #GICC_EOIR]	@ acknowledge the interrupt
-	dsb
-
-	@ Compute CPU number
-	lsr	r9, r9, #10
-	and	r9, r9, #0xf
-
-	movw	r8, #(SUNXI_CPUCFG_BASE & 0xffff)
-	movt	r8, #(SUNXI_CPUCFG_BASE >> 16)
-
-	@ Wait for the core to enter WFI
-	lsl	r11, r9, #6		@ x64
-	add	r11, r11, r8
-
-1:	ldr	r10, [r11, #0x48]
-	tst	r10, #(1 << 2)
-	bne	2f
-	timer_wait r10, ONE_MS
-	b	1b
-
-	@ Reset CPU
-2:	mov	r10, #0
-	str	r10, [r11, #0x40]
-
-	@ Lock CPU
-	mov	r10, #1
-	lsl	r11, r10, r9		@ r11 is now CPU mask
-	ldr	r10, [r8, #0x1e4]
-	bic	r10, r10, r11
-	str	r10, [r8, #0x1e4]
-
-	movw	r8, #(SUNXI_PRCM_BASE & 0xffff)
-	movt	r8, #(SUNXI_PRCM_BASE >> 16)
-
-	@ Set power gating
-	ldr	r10, [r8, #0x100]
-	orr	r10, r10, r11
-	str	r10, [r8, #0x100]
-	timer_wait r10, ONE_MS
-
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
-	@ Activate power clamp
-	lsl	r12, r9, #2		@ x4
-	add	r12, r12, r8
-	mov	r10, #0xff
-	str	r10, [r12, #0x140]
-#endif
-
-	movw	r8, #(SUNXI_CPUCFG_BASE & 0xffff)
-	movt	r8, #(SUNXI_CPUCFG_BASE >> 16)
-
-	@ Unlock CPU
-	ldr	r10, [r8, #0x1e4]
-	orr	r10, r10, r11
-	str	r10, [r8, #0x1e4]
-
-	@ Restore security level
-out:	mcr	p15, 0, r7, c1, c1, 0
-
-	pop	{r0-r12}
-	subs    pc, lr, #4
-
-	@ r1 = target CPU
-	@ r2 = target PC
-.globl	psci_cpu_on
-psci_cpu_on:
-	push	{lr}
-
-	mov	r0, r1
-	bl	psci_get_cpu_stack_top	@ get stack top of target CPU
-	str	r2, [r0]		@ store target PC at stack top
-	dsb
-
-	movw	r0, #(SUNXI_CPUCFG_BASE & 0xffff)
-	movt	r0, #(SUNXI_CPUCFG_BASE >> 16)
-
-	@ CPU mask
-	and	r1, r1, #3	@ only care about first cluster
-	mov	r4, #1
-	lsl	r4, r4, r1
-
-	ldr	r6, =psci_cpu_entry
-	str	r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
-
-	@ Assert reset on target CPU
-	mov	r6, #0
-	lsl	r5, r1, #6	@ 64 bytes per CPU
-	add	r5, r5, #0x40	@ Offset from base
-	add	r5, r5, r0	@ CPU control block
-	str	r6, [r5]	@ Reset CPU
-
-	@ l1 invalidate
-	ldr	r6, [r0, #0x184] @ CPUCFG_GEN_CTRL_REG
-	bic	r6, r6, r4
-	str	r6, [r0, #0x184]
-
-	@ Lock CPU (Disable external debug access)
-	ldr	r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
-	bic	r6, r6, r4
-	str	r6, [r0, #0x1e4]
-
-	movw	r0, #(SUNXI_PRCM_BASE & 0xffff)
-	movt	r0, #(SUNXI_PRCM_BASE >> 16)
-
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
-	@ Release power clamp
-	lsl	r5, r1, #2	@ 1 register per CPU
-	add	r5, r5, r0	@ PRCM
-	movw	r6, #0x1ff
-	movt	r6, #0
-1:	lsrs	r6, r6, #1
-	str	r6, [r5, #0x140] @ CPUx_PWR_CLAMP
-	bne	1b
-#endif
-
-	timer_wait r6, TEN_MS
-
-	@ Clear power gating
-	ldr	r6, [r0, #0x100] @ CPU_PWROFF_GATING
-	bic	r6, r6, r4
-	str	r6, [r0, #0x100]
-
-	@ re-calculate CPU control register address
-	movw	r0, #(SUNXI_CPUCFG_BASE & 0xffff)
-	movt	r0, #(SUNXI_CPUCFG_BASE >> 16)
-
-	@ Deassert reset on target CPU
-	mov	r6, #3
-	lsl	r5, r1, #6	@ 64 bytes per CPU
-	add	r5, r5, #0x40	@ Offset from base
-	add	r5, r5, r0	@ CPU control block
-	str	r6, [r5]
-
-	@ Unlock CPU (Enable external debug access)
-	ldr	r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
-	orr	r6, r6, r4
-	str	r6, [r0, #0x1e4]
-
-	mov	r0, #ARM_PSCI_RET_SUCCESS	@ Return PSCI_RET_SUCCESS
-	pop	{pc}
-
-.globl	psci_cpu_off
-psci_cpu_off:
-	bl	psci_cpu_off_common
-
-	@ Ask CPU0 to pull the rug...
-	movw	r0, #(GICD_BASE & 0xffff)
-	movt	r0, #(GICD_BASE >> 16)
-	movw	r1, #15				@ SGI15
-	movt	r1, #1				@ Target is CPU0
-	str	r1, [r0, #GICD_SGIR]
-	dsb
-
-1:	wfi
-	b	1b
-
-.globl	psci_arch_init
-psci_arch_init:
-	mov	r6, lr
-
-	movw	r4, #(GICD_BASE & 0xffff)
-	movt	r4, #(GICD_BASE >> 16)
-
-	ldr	r5, [r4, #GICD_IGROUPRn]
-	bic	r5, r5, #(1 << 15) 	@ SGI15 as Group-0
-	str	r5, [r4, #GICD_IGROUPRn]
-
-	mov	r5, #0			@ Set SGI15 priority to 0
-	strb	r5, [r4, #(GICD_IPRIORITYRn + 15)]
-
-	add	r4, r4, #0x1000		@ GICC address
-
-	mov	r5, #0xff
-	str	r5, [r4, #GICC_PMR]	@ Be cool with non-secure
-
-	ldr	r5, [r4, #GICC_CTLR]
-	orr	r5, r5, #(1 << 3)	@ Switch FIQEn on
-	str	r5, [r4, #GICC_CTLR]
-
-	mrc	p15, 0, r5, c1, c1, 0	@ Read SCR
-	orr	r5, r5, #4		@ Enable FIQ in monitor mode
-	bic	r5, r5, #1		@ Secure mode
-	mcr	p15, 0, r5, c1, c1, 0	@ Write SCR
-	isb
-
-	bl	psci_get_cpu_id		@ CPU ID => r0
-	bl	psci_get_cpu_stack_top	@ stack top => r0
-	mov	sp, r0
-
-	bx	r6
-
-	.globl psci_text_end
-psci_text_end:
-	.popsection
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
deleted file mode 100644
index 87bbd725f0b3..000000000000
--- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * Copyright (C) 2013 - ARM Ltd
- * Author: Marc Zyngier <marc.zyngier@arm.com>
- *
- * Based on code by Carl van Schaik <carl@ok-labs.com>.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <config.h>
-
-#include <asm/arch-armv7/generictimer.h>
-#include <asm/gic.h>
-#include <asm/macro.h>
-#include <asm/psci.h>
-#include <asm/arch/cpu.h>
-
-/*
- * Memory layout:
- *
- * SECURE_RAM to text_end :
- *	._secure_text section
- * text_end to ALIGN_PAGE(text_end):
- *	nothing
- * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
- *	1kB of stack per CPU (4 CPUs max).
- */
-
-	.pushsection ._secure.text, "ax"
-
-	.arch_extension sec
-
-#define	ONE_MS			(CONFIG_TIMER_CLK_FREQ / 1000)
-#define	TEN_MS			(10 * ONE_MS)
-#define	GICD_BASE		(SUNXI_GIC400_BASE +  0x1000)
-#define	GICC_BASE		(SUNXI_GIC400_BASE +  0x2000)
-
-.globl	psci_fiq_enter
-psci_fiq_enter:
-	push	{r0-r12}
-
-	@ Switch to secure
-	mrc	p15, 0, r7, c1, c1, 0
-	bic	r8, r7, #1
-	mcr	p15, 0, r8, c1, c1, 0
-	isb
-
-	@ Validate reason based on IAR and acknowledge
-	movw	r8, #(GICC_BASE & 0xffff)
-	movt	r8, #(GICC_BASE >> 16)
-	ldr	r9, [r8, #GICC_IAR]
-	movw	r10, #0x3ff
-	movt	r10, #0
-	cmp	r9, r10			@ skip spurious interrupt 1023
-	beq	out
-	movw	r10, #0x3fe		@ ...and 1022
-	cmp	r9, r10
-	beq	out
-	str	r9, [r8, #GICC_EOIR]	@ acknowledge the interrupt
-	dsb
-
-	@ Compute CPU number
-	lsr	r9, r9, #10
-	and	r9, r9, #0xf
-
-	movw	r8, #(SUNXI_CPUCFG_BASE & 0xffff)
-	movt	r8, #(SUNXI_CPUCFG_BASE >> 16)
-
-	@ Wait for the core to enter WFI
-	lsl	r11, r9, #6		@ x64
-	add	r11, r11, r8
-
-1:	ldr	r10, [r11, #0x48]
-	tst	r10, #(1 << 2)
-	bne	2f
-	timer_wait r10, ONE_MS
-	b	1b
-
-	@ Reset CPU
-2:	mov	r10, #0
-	str	r10, [r11, #0x40]
-
-	@ Lock CPU
-	mov	r10, #1
-	lsl	r9, r10, r9		@ r9 is now CPU mask
-	ldr	r10, [r8, #0x1e4]
-	bic	r10, r10, r9
-	str	r10, [r8, #0x1e4]
-
-	@ Set power gating
-	ldr	r10, [r8, #0x1b4]
-	orr	r10, r10, #1
-	str	r10, [r8, #0x1b4]
-	timer_wait r10, ONE_MS
-
-	@ Activate power clamp
-	mov	r10, #1
-1:	str	r10, [r8, #0x1b0]
-	lsl	r10, r10, #1
-	orr	r10, r10, #1
-	tst	r10, #0x100
-	beq	1b
-
-	@ Restore security level
-out:	mcr	p15, 0, r7, c1, c1, 0
-
-	pop	{r0-r12}
-	subs    pc, lr, #4
-
-	@ r1 = target CPU
-	@ r2 = target PC
-.globl	psci_cpu_on
-psci_cpu_on:
-	push	{lr}
-
-	mov	r0, r1
-	bl	psci_get_cpu_stack_top	@ get stack top of target CPU
-	str	r2, [r0]		@ store target PC@stack top
-	dsb
-
-	movw	r0, #(SUNXI_CPUCFG_BASE & 0xffff)
-	movt	r0, #(SUNXI_CPUCFG_BASE >> 16)
-
-	@ CPU mask
-	and	r1, r1, #3	@ only care about first cluster
-	mov	r4, #1
-	lsl	r4, r4, r1
-
-	ldr	r6, =psci_cpu_entry
-	str	r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
-
-	@ Assert reset on target CPU
-	mov	r6, #0
-	lsl	r5, r1, #6	@ 64 bytes per CPU
-	add	r5, r5, #0x40	@ Offset from base
-	add	r5, r5, r0	@ CPU control block
-	str	r6, [r5]	@ Reset CPU
-
-	@ l1 invalidate
-	ldr	r6, [r0, #0x184] @ CPUCFG_GEN_CTRL_REG
-	bic	r6, r6, r4
-	str	r6, [r0, #0x184]
-
-	@ Lock CPU (Disable external debug access)
-	ldr	r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
-	bic	r6, r6, r4
-	str	r6, [r0, #0x1e4]
-
-	@ Release power clamp
-	movw	r6, #0x1ff
-	movt	r6, #0
-1:	lsrs	r6, r6, #1
-	str	r6, [r0, #0x1b0] @ CPU1_PWR_CLAMP
-	bne	1b
-
-	timer_wait r1, TEN_MS
-
-	@ Clear power gating
-	ldr	r6, [r0, #0x1b4] @ CPU1_PWROFF_REG
-	bic	r6, r6, #1
-	str	r6, [r0, #0x1b4]
-
-	@ Deassert reset on target CPU
-	mov	r6, #3
-	str	r6, [r5]
-
-	@ Unlock CPU (Enable external debug access)
-	ldr	r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
-	orr	r6, r6, r4
-	str	r6, [r0, #0x1e4]
-
-	mov	r0, #ARM_PSCI_RET_SUCCESS	@ Return PSCI_RET_SUCCESS
-	pop	{pc}
-
-.globl	psci_cpu_off
-psci_cpu_off:
-	bl	psci_cpu_off_common
-
-	@ Ask CPU0 to pull the rug...
-	movw	r0, #(GICD_BASE & 0xffff)
-	movt	r0, #(GICD_BASE >> 16)
-	movw	r1, #15				@ SGI15
-	movt	r1, #1				@ Target is CPU0
-	str	r1, [r0, #GICD_SGIR]
-	dsb
-
-1:	wfi
-	b	1b
-
-.globl	psci_arch_init
-psci_arch_init:
-	mov	r6, lr
-
-	movw	r4, #(GICD_BASE & 0xffff)
-	movt	r4, #(GICD_BASE >> 16)
-
-	ldr	r5, [r4, #GICD_IGROUPRn]
-	bic	r5, r5, #(1 << 15) 	@ SGI15 as Group-0
-	str	r5, [r4, #GICD_IGROUPRn]
-
-	mov	r5, #0			@ Set SGI15 priority to 0
-	strb	r5, [r4, #(GICD_IPRIORITYRn + 15)]
-
-	add	r4, r4, #0x1000		@ GICC address
-
-	mov	r5, #0xff
-	str	r5, [r4, #GICC_PMR]	@ Be cool with non-secure
-
-	ldr	r5, [r4, #GICC_CTLR]
-	orr	r5, r5, #(1 << 3)	@ Switch FIQEn on
-	str	r5, [r4, #GICC_CTLR]
-
-	mrc	p15, 0, r5, c1, c1, 0	@ Read SCR
-	orr	r5, r5, #4		@ Enable FIQ in monitor mode
-	bic	r5, r5, #1		@ Secure mode
-	mcr	p15, 0, r5, c1, c1, 0	@ Write SCR
-	isb
-
-	bl	psci_get_cpu_id		@ CPU ID => r0
-	bl	psci_get_cpu_stack_top	@ stack top => r0
-	mov	sp, r0
-
-	bx	r6
-
-	.globl psci_text_end
-psci_text_end:
-	.popsection
-- 
2.8.1

[U-Boot] [PATCH v2 11/11] sunxi: Add PSCI implementation in C

[Marc Zyngier]

On 26/05/16 15:01, Chen-Yu Tsai wrote:
> To make the PSCI backend more maintainable and easier to port to newer
> SoCs, rewrite the current PSCI implementation in C.
> 
> Some inline assembly bits are required to access coprocessor registers.
> PSCI stack setup is the only part left completely in assembly. In theory
> this part could be split out of psci_arch_init into a separate common
> function, and psci_arch_init could be completely in C.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  arch/arm/cpu/armv7/sunxi/Makefile     |   7 +-
>  arch/arm/cpu/armv7/sunxi/psci.c       | 269 ++++++++++++++++++++++++++++++++++
>  arch/arm/cpu/armv7/sunxi/psci_head.S  |  66 +++++++++
>  arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 262 ---------------------------------
>  arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 237 ------------------------------
>  5 files changed, 337 insertions(+), 504 deletions(-)
>  create mode 100644 arch/arm/cpu/armv7/sunxi/psci.c
>  create mode 100644 arch/arm/cpu/armv7/sunxi/psci_head.S
>  delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun6i.S
>  delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun7i.S
> 
> diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
> index 4d2274a38ed1..c2085101685b 100644
> --- a/arch/arm/cpu/armv7/sunxi/Makefile
> +++ b/arch/arm/cpu/armv7/sunxi/Makefile
> @@ -13,11 +13,8 @@ obj-$(CONFIG_MACH_SUN6I)	+= tzpc.o
>  obj-$(CONFIG_MACH_SUN8I_H3)	+= tzpc.o
>  
>  ifndef CONFIG_SPL_BUILD
> -ifdef CONFIG_ARMV7_PSCI
> -obj-$(CONFIG_MACH_SUN6I)	+= psci_sun6i.o
> -obj-$(CONFIG_MACH_SUN7I)	+= psci_sun7i.o
> -obj-$(CONFIG_MACH_SUN8I)	+= psci_sun6i.o
> -endif
> +obj-$(CONFIG_ARMV7_PSCI)	+= psci.o
> +obj-$(CONFIG_ARMV7_PSCI)	+= psci_head.o
>  endif
>  
>  ifdef CONFIG_SPL_BUILD
> diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
> new file mode 100644
> index 000000000000..f0c151a349c8
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/sunxi/psci.c
> @@ -0,0 +1,269 @@
> +/*
> + * Copyright (C) 2016
> + * Author: Chen-Yu Tsai <wens@csie.org>
> + *
> + * Based on assembly code by Marc Zyngier <marc.zyngier@arm.com>,
> + * which was based on code by Carl van Schaik <carl@ok-labs.com>.
> + *
> + * SPDX-License-Identifier:	GPL-2.0
> + */
> +#include <config.h>
> +#include <common.h>
> +
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/cpucfg.h>
> +#include <asm/arch/prcm.h>
> +#include <asm/armv7.h>
> +#include <asm/gic.h>
> +#include <asm/io.h>
> +#include <asm/psci.h>
> +#include <asm/system.h>
> +
> +#include <linux/bitops.h>
> +
> +#define __secure	__attribute__ ((section ("._secure.text")))
> +#define __irq		__attribute__ ((interrupt ("IRQ")))
> +
> +#define	GICD_BASE	(SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
> +#define	GICC_BASE	(SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
> +
> +static void cp15_write_cntp_tval(u32 tval)
> +{
> +	asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
> +}
> +
> +static void cp15_write_cntp_ctl(u32 val)
> +{
> +	asm volatile ("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
> +}
> +
> +static u32 cp15_read_cntp_ctl(void)
> +{
> +	u32 val;
> +
> +	asm volatile ("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
> +
> +	return val;
> +}
> +
> +static void __secure __mdelay(u32 ms)
> +{
> +	u32 reg = DIV_ROUND_UP(CONFIG_TIMER_CLK_FREQ, ms);
> +
> +	cp15_write_cntp_tval(reg);
> +	ISB;
> +	cp15_write_cntp_ctl(3);
> +
> +	do {
> +		ISB;
> +		reg = cp15_read_cntp_ctl();
> +	} while (!(reg & BIT(2)));
> +
> +	cp15_write_cntp_ctl(0);
> +}
> +
> +#ifdef CONFIG_MACH_SUN7I
> +/* sun7i (A20) is different from other single cluster SoCs */
> +static void sunxi_cpu_set_power(int __always_unused cpu, bool on)

Missing __secure annotation?

> +{
> +	struct sunxi_cpucfg_reg *cpucfg =
> +		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
> +
> +	if (on) {
> +		/* Release power clamp */
> +		u32 tmp = 0x1ff;
> +		do {
> +			tmp >>= 1;
> +			writel(tmp, &cpucfg->cpu1_pwr_clamp);
> +		} while (tmp);
> +
> +		__mdelay(10);
> +
> +		/* Clear power gating */
> +		clrbits_le32(&cpucfg->cpu1_pwroff, BIT(0));
> +	} else {
> +		/* Set power gating */
> +		setbits_le32(&cpucfg->cpu1_pwroff, BIT(0));
> +
> +		/* Activate power clamp */
> +		writel(0xff, &cpucfg->cpu1_pwr_clamp);
> +	}
> +}
> +#else /* ! CONFIG_MACH_SUN7I */
> +static void sunxi_cpu_set_power(int cpu, bool on)

Same here?

> +{
> +	struct sunxi_prcm_reg *prcm =
> +		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
> +
> +	if (on) {
> +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
> +		/* Release power clamp (A31 & H3 only) */
> +		u32 tmp = 0x1ff;
> +		do {
> +			tmp >>= 1;
> +			writel(tmp, &prcm->cpu_pwr_clamp[cpu]);
> +		} while (tmp);
> +#endif

Do you still need these #ifdefs now that you've split the code from the
sun7i case? If you do, you may want to have a set of "power clamp"
operations (which, by the way, would work on sun7i as well).

> +
> +		__mdelay(10);
> +
> +		/* Clear power gating */
> +		clrbits_le32(&prcm->cpu_pwroff, BIT(cpu));
> +	} else {
> +		/* Set power gating */
> +		setbits_le32(&prcm->cpu_pwroff, BIT(cpu));
> +
> +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
> +		/* Activate power clamp (A31 & H3 only) */
> +		writel(0xff, &prcm->cpu_pwr_clamp[cpu]);
> +#endif
> +	}
> +}
> +#endif /* CONFIG_MACH_SUN7I */
> +
> +void __secure sunxi_cpu_power_off(u32 cpuid)
> +{
> +	struct sunxi_cpucfg_reg *cpucfg =
> +		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
> +	u32 cpu = cpuid & 0x3;
> +
> +	/* Wait for the core to enter WFI */
> +	while (1) {
> +		if (readl(&cpucfg->cpu[cpu].status) & BIT(2))
> +			break;
> +		__mdelay(1);
> +	}
> +
> +	/* Assert reset on target CPU */
> +	writel(0, &cpucfg->cpu[cpu].rst);
> +
> +	/* Lock CPU (Disable external debug access) */
> +	clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
> +
> +	/* Power down CPU */
> +	sunxi_cpu_set_power(cpuid, false);
> +
> +	/* Unlock CPU (Disable external debug access) */
> +	setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
> +}
> +
> +static u32 cp15_read_scr(void)
> +{
> +	u32 scr;
> +
> +	asm volatile ("mrc p15, 0, %0, c1, c1, 0" : "=r" (scr));
> +
> +	return scr;
> +}
> +
> +static void cp15_write_scr(u32 scr)
> +{
> +	asm volatile ("mcr p15, 0, %0, c1, c1, 0" : : "r" (scr));
> +}
> +
> +/*
> + * Although this is an FIQ handler, the FIQ is processed in monitor mode,
> + * which means there's no FIQ banked registers. This is the same as IRQ
> + * mode, so use the IRQ attribute to ask the compiler to handler entry
> + * and return.
> + */
> +void __secure __irq psci_fiq_enter(void)
> +{
> +	u32 scr, reg, cpu;
> +
> +	/* Switch to secure mode */
> +	scr = cp15_read_scr();
> +	cp15_write_scr(scr & ~BIT(0));
> +	ISB;
> +
> +	/* Validate reason based on IAR and acknowledge */
> +	reg = readl(GICC_BASE + GICC_IAR);
> +
> +	/* Skip spurious interrupts 1022 and 1023 */
> +	if (reg == 1023 || reg == 1022)
> +		goto out;
> +
> +	/* Acknowledge interrupt */
> +	writel(reg, GICC_BASE + GICC_EOIR);
> +	DSB;
> +
> +	/* Get CPU number */
> +	cpu = (reg >> 10) & 0x7;
> +
> +	/* Power off the CPU */
> +	sunxi_cpu_power_off(cpu);
> +
> +out:
> +	/* Restore security level */
> +	cp15_write_scr(scr);

I'd feel more confident if we had an isb here, or added one to the helper.

Also, I can't see where is the exception return done. Can you shed any
light on it? Have you tried to do a CPU unplug from Linux?

> +}
> +
> +int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc)
> +{
> +	struct sunxi_cpucfg_reg *cpucfg =
> +		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
> +	u32 cpu = (mpidr & 0x3);
> +
> +	/* store target PC at target CPU stack top */
> +	writel(pc, psci_get_cpu_stack_top(cpu));
> +	DSB;
> +
> +	/* Set secondary core power on PC */
> +	writel((u32)&psci_cpu_entry, &cpucfg->priv0);
> +
> +	/* Assert reset on target CPU */
> +	writel(0, &cpucfg->cpu[cpu].rst);
> +
> +	/* Invalidate L1 cache */
> +	clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu));
> +
> +	/* Lock CPU (Disable external debug access) */
> +	clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
> +
> +	/* Power up target CPU */
> +	sunxi_cpu_set_power(cpu, true);
> +
> +	/* De-assert reset on target CPU */
> +	writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
> +
> +	/* Unlock CPU (Disable external debug access) */
> +	setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
> +
> +	return ARM_PSCI_RET_SUCCESS;
> +}
> +
> +void __secure psci_cpu_off(void)
> +{
> +	psci_cpu_off_common();
> +
> +	/* Ask CPU0 via SGI15 to pull the rug... */
> +	writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
> +	DSB;
> +
> +	/* Wait to be turned off */
> +	while (1)
> +		wfi();
> +}
> +
> +void __secure sunxi_gic_init(void)
> +{
> +	u32 reg;
> +
> +	/* SGI15 as Group-0 */
> +	clrbits_le32(GICD_BASE + GICD_IGROUPRn, BIT(15));
> +
> +	/* Set SGI15 priority to 0 */
> +	writeb(0, GICD_BASE + GICD_IPRIORITYRn + 15);
> +
> +	/* Be cool with non-secure */
> +	writel(0xff, GICC_BASE + GICC_PMR);
> +
> +	/* Switch FIQEn on */
> +	setbits_le32(GICC_BASE + GICC_CTLR, BIT(3));
> +
> +	reg = cp15_read_scr();
> +	reg |= BIT(2);  /* Enable FIQ in monitor mode */
> +	reg &= ~BIT(0); /* Secure mode */
> +	cp15_write_scr(reg);
> +	ISB;

Definitely worth moving that isb inside the helper.

> +}

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

[U-Boot] [PATCH v2 11/11] sunxi: Add PSCI implementation in C

[Chen-Yu Tsai]

On Fri, May 27, 2016 at 1:19 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> On 26/05/16 15:01, Chen-Yu Tsai wrote:
>> To make the PSCI backend more maintainable and easier to port to newer
>> SoCs, rewrite the current PSCI implementation in C.
>>
>> Some inline assembly bits are required to access coprocessor registers.
>> PSCI stack setup is the only part left completely in assembly. In theory
>> this part could be split out of psci_arch_init into a separate common
>> function, and psci_arch_init could be completely in C.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>  arch/arm/cpu/armv7/sunxi/Makefile     |   7 +-
>>  arch/arm/cpu/armv7/sunxi/psci.c       | 269 ++++++++++++++++++++++++++++++++++
>>  arch/arm/cpu/armv7/sunxi/psci_head.S  |  66 +++++++++
>>  arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 262 ---------------------------------
>>  arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 237 ------------------------------
>>  5 files changed, 337 insertions(+), 504 deletions(-)
>>  create mode 100644 arch/arm/cpu/armv7/sunxi/psci.c
>>  create mode 100644 arch/arm/cpu/armv7/sunxi/psci_head.S
>>  delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun6i.S
>>  delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun7i.S
>>
>> diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
>> index 4d2274a38ed1..c2085101685b 100644
>> --- a/arch/arm/cpu/armv7/sunxi/Makefile
>> +++ b/arch/arm/cpu/armv7/sunxi/Makefile
>> @@ -13,11 +13,8 @@ obj-$(CONFIG_MACH_SUN6I)   += tzpc.o
>>  obj-$(CONFIG_MACH_SUN8I_H3)  += tzpc.o
>>
>>  ifndef CONFIG_SPL_BUILD
>> -ifdef CONFIG_ARMV7_PSCI
>> -obj-$(CONFIG_MACH_SUN6I)     += psci_sun6i.o
>> -obj-$(CONFIG_MACH_SUN7I)     += psci_sun7i.o
>> -obj-$(CONFIG_MACH_SUN8I)     += psci_sun6i.o
>> -endif
>> +obj-$(CONFIG_ARMV7_PSCI)     += psci.o
>> +obj-$(CONFIG_ARMV7_PSCI)     += psci_head.o
>>  endif
>>
>>  ifdef CONFIG_SPL_BUILD
>> diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
>> new file mode 100644
>> index 000000000000..f0c151a349c8
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv7/sunxi/psci.c
>> @@ -0,0 +1,269 @@
>> +/*
>> + * Copyright (C) 2016
>> + * Author: Chen-Yu Tsai <wens@csie.org>
>> + *
>> + * Based on assembly code by Marc Zyngier <marc.zyngier@arm.com>,
>> + * which was based on code by Carl van Schaik <carl@ok-labs.com>.
>> + *
>> + * SPDX-License-Identifier:  GPL-2.0
>> + */
>> +#include <config.h>
>> +#include <common.h>
>> +
>> +#include <asm/arch/cpu.h>
>> +#include <asm/arch/cpucfg.h>
>> +#include <asm/arch/prcm.h>
>> +#include <asm/armv7.h>
>> +#include <asm/gic.h>
>> +#include <asm/io.h>
>> +#include <asm/psci.h>
>> +#include <asm/system.h>
>> +
>> +#include <linux/bitops.h>
>> +
>> +#define __secure     __attribute__ ((section ("._secure.text")))
>> +#define __irq                __attribute__ ((interrupt ("IRQ")))
>> +
>> +#define      GICD_BASE       (SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
>> +#define      GICC_BASE       (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
>> +
>> +static void cp15_write_cntp_tval(u32 tval)
>> +{
>> +     asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
>> +}
>> +
>> +static void cp15_write_cntp_ctl(u32 val)
>> +{
>> +     asm volatile ("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
>> +}
>> +
>> +static u32 cp15_read_cntp_ctl(void)
>> +{
>> +     u32 val;
>> +
>> +     asm volatile ("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
>> +
>> +     return val;
>> +}
>> +
>> +static void __secure __mdelay(u32 ms)
>> +{
>> +     u32 reg = DIV_ROUND_UP(CONFIG_TIMER_CLK_FREQ, ms);
>> +
>> +     cp15_write_cntp_tval(reg);
>> +     ISB;
>> +     cp15_write_cntp_ctl(3);
>> +
>> +     do {
>> +             ISB;
>> +             reg = cp15_read_cntp_ctl();
>> +     } while (!(reg & BIT(2)));
>> +
>> +     cp15_write_cntp_ctl(0);
>> +}
>> +
>> +#ifdef CONFIG_MACH_SUN7I
>> +/* sun7i (A20) is different from other single cluster SoCs */
>> +static void sunxi_cpu_set_power(int __always_unused cpu, bool on)
>
> Missing __secure annotation?

Right. This worked because the compiler inlined the whole thing.
I'll add it.

>
>> +{
>> +     struct sunxi_cpucfg_reg *cpucfg =
>> +             (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
>> +
>> +     if (on) {
>> +             /* Release power clamp */
>> +             u32 tmp = 0x1ff;
>> +             do {
>> +                     tmp >>= 1;
>> +                     writel(tmp, &cpucfg->cpu1_pwr_clamp);
>> +             } while (tmp);
>> +
>> +             __mdelay(10);
>> +
>> +             /* Clear power gating */
>> +             clrbits_le32(&cpucfg->cpu1_pwroff, BIT(0));
>> +     } else {
>> +             /* Set power gating */
>> +             setbits_le32(&cpucfg->cpu1_pwroff, BIT(0));
>> +
>> +             /* Activate power clamp */
>> +             writel(0xff, &cpucfg->cpu1_pwr_clamp);
>> +     }
>> +}
>> +#else /* ! CONFIG_MACH_SUN7I */
>> +static void sunxi_cpu_set_power(int cpu, bool on)
>
> Same here?
>
>> +{
>> +     struct sunxi_prcm_reg *prcm =
>> +             (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
>> +
>> +     if (on) {
>> +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
>> +             /* Release power clamp (A31 & H3 only) */
>> +             u32 tmp = 0x1ff;
>> +             do {
>> +                     tmp >>= 1;
>> +                     writel(tmp, &prcm->cpu_pwr_clamp[cpu]);
>> +             } while (tmp);
>> +#endif
>
> Do you still need these #ifdefs now that you've split the code from the
> sun7i case? If you do, you may want to have a set of "power clamp"
> operations (which, by the way, would work on sun7i as well).

Only the A31, A31s (sun6i) and H3 have power clamps. The A23 and A33
do not. While writing to the registers seemed ok, the values stuck
and I'm not so sure we should do so.

So splitting this out is just pushing the #ifdefs to another function
which is unused for A23/A33. I'm not sure that really helps.

>
>> +
>> +             __mdelay(10);
>> +
>> +             /* Clear power gating */
>> +             clrbits_le32(&prcm->cpu_pwroff, BIT(cpu));
>> +     } else {
>> +             /* Set power gating */
>> +             setbits_le32(&prcm->cpu_pwroff, BIT(cpu));
>> +
>> +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
>> +             /* Activate power clamp (A31 & H3 only) */
>> +             writel(0xff, &prcm->cpu_pwr_clamp[cpu]);
>> +#endif
>> +     }
>> +}
>> +#endif /* CONFIG_MACH_SUN7I */
>> +
>> +void __secure sunxi_cpu_power_off(u32 cpuid)
>> +{
>> +     struct sunxi_cpucfg_reg *cpucfg =
>> +             (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
>> +     u32 cpu = cpuid & 0x3;
>> +
>> +     /* Wait for the core to enter WFI */
>> +     while (1) {
>> +             if (readl(&cpucfg->cpu[cpu].status) & BIT(2))
>> +                     break;
>> +             __mdelay(1);
>> +     }
>> +
>> +     /* Assert reset on target CPU */
>> +     writel(0, &cpucfg->cpu[cpu].rst);
>> +
>> +     /* Lock CPU (Disable external debug access) */
>> +     clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
>> +
>> +     /* Power down CPU */
>> +     sunxi_cpu_set_power(cpuid, false);
>> +
>> +     /* Unlock CPU (Disable external debug access) */
>> +     setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
>> +}
>> +
>> +static u32 cp15_read_scr(void)
>> +{
>> +     u32 scr;
>> +
>> +     asm volatile ("mrc p15, 0, %0, c1, c1, 0" : "=r" (scr));
>> +
>> +     return scr;
>> +}
>> +
>> +static void cp15_write_scr(u32 scr)
>> +{
>> +     asm volatile ("mcr p15, 0, %0, c1, c1, 0" : : "r" (scr));
>> +}
>> +
>> +/*
>> + * Although this is an FIQ handler, the FIQ is processed in monitor mode,
>> + * which means there's no FIQ banked registers. This is the same as IRQ
>> + * mode, so use the IRQ attribute to ask the compiler to handler entry
>> + * and return.
>> + */
>> +void __secure __irq psci_fiq_enter(void)
>> +{
>> +     u32 scr, reg, cpu;
>> +
>> +     /* Switch to secure mode */
>> +     scr = cp15_read_scr();
>> +     cp15_write_scr(scr & ~BIT(0));
>> +     ISB;
>> +
>> +     /* Validate reason based on IAR and acknowledge */
>> +     reg = readl(GICC_BASE + GICC_IAR);
>> +
>> +     /* Skip spurious interrupts 1022 and 1023 */
>> +     if (reg == 1023 || reg == 1022)
>> +             goto out;
>> +
>> +     /* Acknowledge interrupt */
>> +     writel(reg, GICC_BASE + GICC_EOIR);
>> +     DSB;
>> +
>> +     /* Get CPU number */
>> +     cpu = (reg >> 10) & 0x7;
>> +
>> +     /* Power off the CPU */
>> +     sunxi_cpu_power_off(cpu);
>> +
>> +out:
>> +     /* Restore security level */
>> +     cp15_write_scr(scr);
>
> I'd feel more confident if we had an isb here, or added one to the helper.
>
> Also, I can't see where is the exception return done. Can you shed any
> light on it? Have you tried to do a CPU unplug from Linux?

I have. The exception return is generated by the compiler, because of
__irq (which expands to """__attribute__ ((interrupt ("IRQ")))""").

See: https://gcc.gnu.org/onlinedocs/gcc/ARM-Function-Attributes.html#ARM-Function-Attributes

AFAIK, FIQ in monitor mode only sp and lr are banked, which would be
the same as IRQ handling. Hence the comment on top. I can't seem to
find where I looked this up now, but it was some official ARM document.

The Linaro toolchain GCC 4.9 2014.11 generates the prologue:

4a03c3f0 <psci_fiq_enter>:
4a03c3f0:       e24ee004        sub     lr, lr, #4
4a03c3f4:       e92d521f        push    {r0, r1, r2, r3, r4, r9, ip, lr}

and the epilogue:

4a03c434:       e8fd921f        ldm     sp!, {r0, r1, r2, r3, r4, r9, ip, pc}^

which would be equivalent to

    pop {r0, r1, r2, r3, r4, r9, ip, lr}
    movs pc, lr

gcc version 5.3.1 20160519 (Debian 5.3.1-20) generates the same sequence.

The entry and return parts are almost the same as the original assembly
code, though the original has "subs pc, lr, #4" and store r0 - r12.

>> +}
>> +
>> +int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc)
>> +{
>> +     struct sunxi_cpucfg_reg *cpucfg =
>> +             (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
>> +     u32 cpu = (mpidr & 0x3);
>> +
>> +     /* store target PC at target CPU stack top */
>> +     writel(pc, psci_get_cpu_stack_top(cpu));
>> +     DSB;
>> +
>> +     /* Set secondary core power on PC */
>> +     writel((u32)&psci_cpu_entry, &cpucfg->priv0);
>> +
>> +     /* Assert reset on target CPU */
>> +     writel(0, &cpucfg->cpu[cpu].rst);
>> +
>> +     /* Invalidate L1 cache */
>> +     clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu));
>> +
>> +     /* Lock CPU (Disable external debug access) */
>> +     clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
>> +
>> +     /* Power up target CPU */
>> +     sunxi_cpu_set_power(cpu, true);
>> +
>> +     /* De-assert reset on target CPU */
>> +     writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
>> +
>> +     /* Unlock CPU (Disable external debug access) */
>> +     setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
>> +
>> +     return ARM_PSCI_RET_SUCCESS;
>> +}
>> +
>> +void __secure psci_cpu_off(void)
>> +{
>> +     psci_cpu_off_common();
>> +
>> +     /* Ask CPU0 via SGI15 to pull the rug... */
>> +     writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
>> +     DSB;
>> +
>> +     /* Wait to be turned off */
>> +     while (1)
>> +             wfi();
>> +}
>> +
>> +void __secure sunxi_gic_init(void)
>> +{
>> +     u32 reg;
>> +
>> +     /* SGI15 as Group-0 */
>> +     clrbits_le32(GICD_BASE + GICD_IGROUPRn, BIT(15));
>> +
>> +     /* Set SGI15 priority to 0 */
>> +     writeb(0, GICD_BASE + GICD_IPRIORITYRn + 15);
>> +
>> +     /* Be cool with non-secure */
>> +     writel(0xff, GICC_BASE + GICC_PMR);
>> +
>> +     /* Switch FIQEn on */
>> +     setbits_le32(GICC_BASE + GICC_CTLR, BIT(3));
>> +
>> +     reg = cp15_read_scr();
>> +     reg |= BIT(2);  /* Enable FIQ in monitor mode */
>> +     reg &= ~BIT(0); /* Secure mode */
>> +     cp15_write_scr(reg);
>> +     ISB;
>
> Definitely worth moving that isb inside the helper.

Will do.


Regards
ChenYu

>> +}
>
> Thanks,
>
>         M.
> --
> Jazz is not dead. It just smells funny...

[U-Boot] [PATCH v2 11/11] sunxi: Add PSCI implementation in C

[Marc Zyngier]

On 27/05/16 05:22, Chen-Yu Tsai wrote:
> On Fri, May 27, 2016 at 1:19 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> On 26/05/16 15:01, Chen-Yu Tsai wrote:
>>> To make the PSCI backend more maintainable and easier to port to newer
>>> SoCs, rewrite the current PSCI implementation in C.
>>>
>>> Some inline assembly bits are required to access coprocessor registers.
>>> PSCI stack setup is the only part left completely in assembly. In theory
>>> this part could be split out of psci_arch_init into a separate common
>>> function, and psci_arch_init could be completely in C.
>>>
>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>>> ---
>>>  arch/arm/cpu/armv7/sunxi/Makefile     |   7 +-
>>>  arch/arm/cpu/armv7/sunxi/psci.c       | 269 ++++++++++++++++++++++++++++++++++
>>>  arch/arm/cpu/armv7/sunxi/psci_head.S  |  66 +++++++++
>>>  arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 262 ---------------------------------
>>>  arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 237 ------------------------------
>>>  5 files changed, 337 insertions(+), 504 deletions(-)
>>>  create mode 100644 arch/arm/cpu/armv7/sunxi/psci.c
>>>  create mode 100644 arch/arm/cpu/armv7/sunxi/psci_head.S
>>>  delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun6i.S
>>>  delete mode 100644 arch/arm/cpu/armv7/sunxi/psci_sun7i.S
>>>
>>> diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
>>> index 4d2274a38ed1..c2085101685b 100644
>>> --- a/arch/arm/cpu/armv7/sunxi/Makefile
>>> +++ b/arch/arm/cpu/armv7/sunxi/Makefile
>>> @@ -13,11 +13,8 @@ obj-$(CONFIG_MACH_SUN6I)   += tzpc.o
>>>  obj-$(CONFIG_MACH_SUN8I_H3)  += tzpc.o
>>>
>>>  ifndef CONFIG_SPL_BUILD
>>> -ifdef CONFIG_ARMV7_PSCI
>>> -obj-$(CONFIG_MACH_SUN6I)     += psci_sun6i.o
>>> -obj-$(CONFIG_MACH_SUN7I)     += psci_sun7i.o
>>> -obj-$(CONFIG_MACH_SUN8I)     += psci_sun6i.o
>>> -endif
>>> +obj-$(CONFIG_ARMV7_PSCI)     += psci.o
>>> +obj-$(CONFIG_ARMV7_PSCI)     += psci_head.o
>>>  endif
>>>
>>>  ifdef CONFIG_SPL_BUILD
>>> diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
>>> new file mode 100644
>>> index 000000000000..f0c151a349c8
>>> --- /dev/null
>>> +++ b/arch/arm/cpu/armv7/sunxi/psci.c
>>> @@ -0,0 +1,269 @@
>>> +/*
>>> + * Copyright (C) 2016
>>> + * Author: Chen-Yu Tsai <wens@csie.org>
>>> + *
>>> + * Based on assembly code by Marc Zyngier <marc.zyngier@arm.com>,
>>> + * which was based on code by Carl van Schaik <carl@ok-labs.com>.
>>> + *
>>> + * SPDX-License-Identifier:  GPL-2.0
>>> + */
>>> +#include <config.h>
>>> +#include <common.h>
>>> +
>>> +#include <asm/arch/cpu.h>
>>> +#include <asm/arch/cpucfg.h>
>>> +#include <asm/arch/prcm.h>
>>> +#include <asm/armv7.h>
>>> +#include <asm/gic.h>
>>> +#include <asm/io.h>
>>> +#include <asm/psci.h>
>>> +#include <asm/system.h>
>>> +
>>> +#include <linux/bitops.h>
>>> +
>>> +#define __secure     __attribute__ ((section ("._secure.text")))
>>> +#define __irq                __attribute__ ((interrupt ("IRQ")))
>>> +
>>> +#define      GICD_BASE       (SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
>>> +#define      GICC_BASE       (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
>>> +
>>> +static void cp15_write_cntp_tval(u32 tval)
>>> +{
>>> +     asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
>>> +}
>>> +
>>> +static void cp15_write_cntp_ctl(u32 val)
>>> +{
>>> +     asm volatile ("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
>>> +}
>>> +
>>> +static u32 cp15_read_cntp_ctl(void)
>>> +{
>>> +     u32 val;
>>> +
>>> +     asm volatile ("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
>>> +
>>> +     return val;
>>> +}
>>> +
>>> +static void __secure __mdelay(u32 ms)
>>> +{
>>> +     u32 reg = DIV_ROUND_UP(CONFIG_TIMER_CLK_FREQ, ms);
>>> +
>>> +     cp15_write_cntp_tval(reg);
>>> +     ISB;
>>> +     cp15_write_cntp_ctl(3);
>>> +
>>> +     do {
>>> +             ISB;
>>> +             reg = cp15_read_cntp_ctl();
>>> +     } while (!(reg & BIT(2)));
>>> +
>>> +     cp15_write_cntp_ctl(0);
>>> +}
>>> +
>>> +#ifdef CONFIG_MACH_SUN7I
>>> +/* sun7i (A20) is different from other single cluster SoCs */
>>> +static void sunxi_cpu_set_power(int __always_unused cpu, bool on)
>>
>> Missing __secure annotation?
> 
> Right. This worked because the compiler inlined the whole thing.
> I'll add it.
> 
>>
>>> +{
>>> +     struct sunxi_cpucfg_reg *cpucfg =
>>> +             (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
>>> +
>>> +     if (on) {
>>> +             /* Release power clamp */
>>> +             u32 tmp = 0x1ff;
>>> +             do {
>>> +                     tmp >>= 1;
>>> +                     writel(tmp, &cpucfg->cpu1_pwr_clamp);
>>> +             } while (tmp);
>>> +
>>> +             __mdelay(10);
>>> +
>>> +             /* Clear power gating */
>>> +             clrbits_le32(&cpucfg->cpu1_pwroff, BIT(0));
>>> +     } else {
>>> +             /* Set power gating */
>>> +             setbits_le32(&cpucfg->cpu1_pwroff, BIT(0));
>>> +
>>> +             /* Activate power clamp */
>>> +             writel(0xff, &cpucfg->cpu1_pwr_clamp);
>>> +     }
>>> +}
>>> +#else /* ! CONFIG_MACH_SUN7I */
>>> +static void sunxi_cpu_set_power(int cpu, bool on)
>>
>> Same here?
>>
>>> +{
>>> +     struct sunxi_prcm_reg *prcm =
>>> +             (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
>>> +
>>> +     if (on) {
>>> +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
>>> +             /* Release power clamp (A31 & H3 only) */
>>> +             u32 tmp = 0x1ff;
>>> +             do {
>>> +                     tmp >>= 1;
>>> +                     writel(tmp, &prcm->cpu_pwr_clamp[cpu]);
>>> +             } while (tmp);
>>> +#endif
>>
>> Do you still need these #ifdefs now that you've split the code from the
>> sun7i case? If you do, you may want to have a set of "power clamp"
>> operations (which, by the way, would work on sun7i as well).
> 
> Only the A31, A31s (sun6i) and H3 have power clamps. The A23 and A33
> do not. While writing to the registers seemed ok, the values stuck
> and I'm not so sure we should do so.
> 
> So splitting this out is just pushing the #ifdefs to another function
> which is unused for A23/A33. I'm not sure that really helps.

Here's what I had in mind:

static void clamp_release(u32 *clamp)
{
#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3) ||
defined (CONFIG_MACH_SUN7I)
	u32 tmp = 0x1ff;
	do {
		tmp >>= 1;
		writel(tmp, clamp);
	} while (tmp);

	__mdelay(10);
#endif
}

static void clamp_set(u32 *clamp)
{
#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3) ||
defined (CONFIG_MACH_SUN7I)
	write(0xff, clamp);
#endif
}

static void sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on, int cpu)
{
	if (on) {
		/* Release power clamp */
		clamp_release(clamp);

		/* Clear power gating */
		clrbits_le32(pwroff, BIT(cpu));
	} else {
		/* Set power gating */
		setbits_le32(pwroff, BIT(cpu));

		/* Activate power clamp */
		clamp_set(clamp);
	}
}

#ifdef CONFIG_MACH_SUN7I
/* sun7i (A20) is different from other single cluster SoCs */
static void sunxi_cpu_set_power(int __always_unused cpu, bool on)
{
	struct sunxi_cpucfg_reg *cpucfg =
		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;

	sunxi_power_switch(&cpucfg->cpu1_pwr_clamp,
			   &cpucfg->cpu1_pwroff,
			   on, 0);
}
#else /* ! CONFIG_MACH_SUN7I */
static void sunxi_cpu_set_power(int cpu, bool on)
{
	struct sunxi_prcm_reg *prcm =
		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;

	sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu],
			   &prcm->cpu_pwroff,
			   on, cpu);
}
#endif /* CONFIG_MACH_SUN7I */

Feel free to use it or not.

>>
>>> +
>>> +             __mdelay(10);
>>> +
>>> +             /* Clear power gating */
>>> +             clrbits_le32(&prcm->cpu_pwroff, BIT(cpu));
>>> +     } else {
>>> +             /* Set power gating */
>>> +             setbits_le32(&prcm->cpu_pwroff, BIT(cpu));
>>> +
>>> +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
>>> +             /* Activate power clamp (A31 & H3 only) */
>>> +             writel(0xff, &prcm->cpu_pwr_clamp[cpu]);
>>> +#endif
>>> +     }
>>> +}
>>> +#endif /* CONFIG_MACH_SUN7I */
>>> +
>>> +void __secure sunxi_cpu_power_off(u32 cpuid)
>>> +{
>>> +     struct sunxi_cpucfg_reg *cpucfg =
>>> +             (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
>>> +     u32 cpu = cpuid & 0x3;
>>> +
>>> +     /* Wait for the core to enter WFI */
>>> +     while (1) {
>>> +             if (readl(&cpucfg->cpu[cpu].status) & BIT(2))
>>> +                     break;
>>> +             __mdelay(1);
>>> +     }
>>> +
>>> +     /* Assert reset on target CPU */
>>> +     writel(0, &cpucfg->cpu[cpu].rst);
>>> +
>>> +     /* Lock CPU (Disable external debug access) */
>>> +     clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
>>> +
>>> +     /* Power down CPU */
>>> +     sunxi_cpu_set_power(cpuid, false);
>>> +
>>> +     /* Unlock CPU (Disable external debug access) */
>>> +     setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
>>> +}
>>> +
>>> +static u32 cp15_read_scr(void)
>>> +{
>>> +     u32 scr;
>>> +
>>> +     asm volatile ("mrc p15, 0, %0, c1, c1, 0" : "=r" (scr));
>>> +
>>> +     return scr;
>>> +}
>>> +
>>> +static void cp15_write_scr(u32 scr)
>>> +{
>>> +     asm volatile ("mcr p15, 0, %0, c1, c1, 0" : : "r" (scr));
>>> +}
>>> +
>>> +/*
>>> + * Although this is an FIQ handler, the FIQ is processed in monitor mode,
>>> + * which means there's no FIQ banked registers. This is the same as IRQ
>>> + * mode, so use the IRQ attribute to ask the compiler to handler entry
>>> + * and return.
>>> + */
>>> +void __secure __irq psci_fiq_enter(void)
>>> +{
>>> +     u32 scr, reg, cpu;
>>> +
>>> +     /* Switch to secure mode */
>>> +     scr = cp15_read_scr();
>>> +     cp15_write_scr(scr & ~BIT(0));
>>> +     ISB;
>>> +
>>> +     /* Validate reason based on IAR and acknowledge */
>>> +     reg = readl(GICC_BASE + GICC_IAR);
>>> +
>>> +     /* Skip spurious interrupts 1022 and 1023 */
>>> +     if (reg == 1023 || reg == 1022)
>>> +             goto out;
>>> +
>>> +     /* Acknowledge interrupt */
>>> +     writel(reg, GICC_BASE + GICC_EOIR);
>>> +     DSB;
>>> +
>>> +     /* Get CPU number */
>>> +     cpu = (reg >> 10) & 0x7;
>>> +
>>> +     /* Power off the CPU */
>>> +     sunxi_cpu_power_off(cpu);
>>> +
>>> +out:
>>> +     /* Restore security level */
>>> +     cp15_write_scr(scr);
>>
>> I'd feel more confident if we had an isb here, or added one to the helper.
>>
>> Also, I can't see where is the exception return done. Can you shed any
>> light on it? Have you tried to do a CPU unplug from Linux?
> 
> I have. The exception return is generated by the compiler, because of
> __irq (which expands to """__attribute__ ((interrupt ("IRQ")))""").
> 
> See: https://gcc.gnu.org/onlinedocs/gcc/ARM-Function-Attributes.html#ARM-Function-Attributes

Ah, that's an interesting one (I'm obviously used to deal with this by
hand, hence my surprise at this).

> AFAIK, FIQ in monitor mode only sp and lr are banked, which would be
> the same as IRQ handling. Hence the comment on top. I can't seem to
> find where I looked this up now, but it was some official ARM document.
> 
> The Linaro toolchain GCC 4.9 2014.11 generates the prologue:
> 
> 4a03c3f0 <psci_fiq_enter>:
> 4a03c3f0:       e24ee004        sub     lr, lr, #4
> 4a03c3f4:       e92d521f        push    {r0, r1, r2, r3, r4, r9, ip, lr}
> 
> and the epilogue:
> 
> 4a03c434:       e8fd921f        ldm     sp!, {r0, r1, r2, r3, r4, r9, ip, pc}^

Yup, that looks sane.

> which would be equivalent to
> 
>     pop {r0, r1, r2, r3, r4, r9, ip, lr}
>     movs pc, lr
> 
> gcc version 5.3.1 20160519 (Debian 5.3.1-20) generates the same sequence.
> 
> The entry and return parts are almost the same as the original assembly
> code, though the original has "subs pc, lr, #4" and store r0 - r12.
> 
>>> +}
>>> +
>>> +int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc)
>>> +{
>>> +     struct sunxi_cpucfg_reg *cpucfg =
>>> +             (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
>>> +     u32 cpu = (mpidr & 0x3);
>>> +
>>> +     /* store target PC at target CPU stack top */
>>> +     writel(pc, psci_get_cpu_stack_top(cpu));
>>> +     DSB;
>>> +
>>> +     /* Set secondary core power on PC */
>>> +     writel((u32)&psci_cpu_entry, &cpucfg->priv0);
>>> +
>>> +     /* Assert reset on target CPU */
>>> +     writel(0, &cpucfg->cpu[cpu].rst);
>>> +
>>> +     /* Invalidate L1 cache */
>>> +     clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu));
>>> +
>>> +     /* Lock CPU (Disable external debug access) */
>>> +     clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
>>> +
>>> +     /* Power up target CPU */
>>> +     sunxi_cpu_set_power(cpu, true);
>>> +
>>> +     /* De-assert reset on target CPU */
>>> +     writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
>>> +
>>> +     /* Unlock CPU (Disable external debug access) */
>>> +     setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
>>> +
>>> +     return ARM_PSCI_RET_SUCCESS;
>>> +}
>>> +
>>> +void __secure psci_cpu_off(void)
>>> +{
>>> +     psci_cpu_off_common();
>>> +
>>> +     /* Ask CPU0 via SGI15 to pull the rug... */
>>> +     writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
>>> +     DSB;
>>> +
>>> +     /* Wait to be turned off */
>>> +     while (1)
>>> +             wfi();
>>> +}
>>> +
>>> +void __secure sunxi_gic_init(void)
>>> +{
>>> +     u32 reg;
>>> +
>>> +     /* SGI15 as Group-0 */
>>> +     clrbits_le32(GICD_BASE + GICD_IGROUPRn, BIT(15));
>>> +
>>> +     /* Set SGI15 priority to 0 */
>>> +     writeb(0, GICD_BASE + GICD_IPRIORITYRn + 15);
>>> +
>>> +     /* Be cool with non-secure */
>>> +     writel(0xff, GICC_BASE + GICC_PMR);
>>> +
>>> +     /* Switch FIQEn on */
>>> +     setbits_le32(GICC_BASE + GICC_CTLR, BIT(3));
>>> +
>>> +     reg = cp15_read_scr();
>>> +     reg |= BIT(2);  /* Enable FIQ in monitor mode */
>>> +     reg &= ~BIT(0); /* Secure mode */
>>> +     cp15_write_scr(reg);
>>> +     ISB;
>>
>> Definitely worth moving that isb inside the helper.
> 
> Will do.

I think this is starting to look good overall. Feel free to send a v3,
and we should be good to go.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...