From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Fri, 3 Jun 2016 22:03:01 -0700 Subject: [U-Boot] [PATCH 2/2] board/freescale: Update ddr clk_adjust In-Reply-To: <1462328422-37229-2-git-send-email-Shengzhou.Liu@nxp.com> References: <1462328422-37229-1-git-send-email-Shengzhou.Liu@nxp.com> <1462328422-37229-2-git-send-email-Shengzhou.Liu@nxp.com> Message-ID: <57526105.6070209@nxp.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 05/03/2016 07:30 PM, Shengzhou Liu wrote: > This patch updates clk_adjust to actual value for boards with > T-series and LS-series SoCs to match the setting of clk_adjust > in latest ddr driver. > > Signed-off-by: Shengzhou Liu > --- > board/freescale/ls1021aqds/ddr.h | 28 ++++++++++++++-------------- > board/freescale/ls1043aqds/ddr.h | 28 ++++++++++++++-------------- > board/freescale/ls1043ardb/ddr.h | 6 +++--- > board/freescale/ls2080aqds/ddr.h | 32 ++++++++++++++++---------------- > board/freescale/ls2080ardb/ddr.h | 32 ++++++++++++++++---------------- > board/freescale/t102xqds/ddr.c | 22 +++++++++++----------- > board/freescale/t102xrdb/ddr.c | 12 ++++++------ > board/freescale/t1040qds/ddr.h | 22 +++++++++++----------- > board/freescale/t104xrdb/ddr.h | 26 +++++++++++++------------- > board/freescale/t208xqds/ddr.h | 40 ++++++++++++++++++++-------------------- > board/freescale/t208xrdb/ddr.h | 20 ++++++++++---------- > board/freescale/t4qds/ddr.h | 38 +++++++++++++++++++------------------- > board/freescale/t4rdb/ddr.h | 38 +++++++++++++++++++------------------- > 13 files changed, 172 insertions(+), 172 deletions(-) > Applied to fsl-qoriq master branch. Awaiting upstream. Thanks. York