From: York Sun <york.sun@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] drivers/ddr/fsl: Fix timing_cfg_2 register
Date: Fri, 3 Jun 2016 22:05:04 -0700 [thread overview]
Message-ID: <57526180.4030508@nxp.com> (raw)
In-Reply-To: <1463631079-22490-1-git-send-email-york.sun@nxp.com>
On 05/18/2016 09:11 PM, York Sun wrote:
> Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but
> with wrong bit position. It is bit 13 in big-endian, or left shift
> 18 from LSB. This error hasn't had any impact because we don't have
> fast enough DDR4 using the extra bit so far.
>
> Signed-off-by: York Sun <york.sun@nxp.com>
>
> ---
>
> drivers/ddr/fsl/ctrl_regs.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied to fsl-qoriq master branch. Awaiting upstream.
York
prev parent reply other threads:[~2016-06-04 5:05 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-19 4:11 [U-Boot] [PATCH] drivers/ddr/fsl: Fix timing_cfg_2 register York Sun
2016-06-04 5:05 ` York Sun [this message]
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