* [U-Boot] [PATCH] drivers/ddr/fsl: Fix timing_cfg_2 register
@ 2016-05-19 4:11 York Sun
2016-06-04 5:05 ` York Sun
0 siblings, 1 reply; 2+ messages in thread
From: York Sun @ 2016-05-19 4:11 UTC (permalink / raw)
To: u-boot
Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but
with wrong bit position. It is bit 13 in big-endian, or left shift
18 from LSB. This error hasn't had any impact because we don't have
fast enough DDR4 using the extra bit so far.
Signed-off-by: York Sun <york.sun@nxp.com>
---
drivers/ddr/fsl/ctrl_regs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 9073917..60fed84 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -709,7 +709,7 @@ static void set_timing_cfg_2(const unsigned int ctrl_num,
| ((add_lat_mclk & 0xf) << 28)
| ((cpo & 0x1f) << 23)
| ((wr_lat & 0xf) << 19)
- | ((wr_lat & 0x10) << 14)
+ | ((wr_lat & 0x10) << 18)
| ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
| ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
| ((cke_pls & 0x7) << 6)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [U-Boot] [PATCH] drivers/ddr/fsl: Fix timing_cfg_2 register
2016-05-19 4:11 [U-Boot] [PATCH] drivers/ddr/fsl: Fix timing_cfg_2 register York Sun
@ 2016-06-04 5:05 ` York Sun
0 siblings, 0 replies; 2+ messages in thread
From: York Sun @ 2016-06-04 5:05 UTC (permalink / raw)
To: u-boot
On 05/18/2016 09:11 PM, York Sun wrote:
> Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but
> with wrong bit position. It is bit 13 in big-endian, or left shift
> 18 from LSB. This error hasn't had any impact because we don't have
> fast enough DDR4 using the extra bit so far.
>
> Signed-off-by: York Sun <york.sun@nxp.com>
>
> ---
>
> drivers/ddr/fsl/ctrl_regs.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied to fsl-qoriq master branch. Awaiting upstream.
York
^ permalink raw reply [flat|nested] 2+ messages in thread
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