From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/2] MIPS: Make CONFIG_SYS_DCACHE_LINE_SIZE int, not hex
Date: Fri, 10 Jun 2016 12:46:09 +0200 [thread overview]
Message-ID: <575A9A71.7010706@gmail.com> (raw)
In-Reply-To: <20160609120952.4799-2-paul.burton@imgtec.com>
Am 09.06.2016 um 14:09 schrieb Paul Burton:
> For consistency with the other cache-related Kconfig entries & the
> values actually set by boards, make CONFIG_SYS_DCACHE_LINE_SIZE an int
> entry instead of a hex entry.
>
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> Fixes: 372286217f05 ("MIPS: Split I & D cache line size config")
> ---
>
> arch/mips/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
applied to u-boot-mips, thanks.
BTW: there is a similar patch from Purna [1] but I applied this one
because it contains a "Fixes:" line.
[1] http://patchwork.ozlabs.org/patch/630747/
--
- Daniel
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next prev parent reply other threads:[~2016-06-10 10:46 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-09 12:09 [U-Boot] [PATCH 1/2] MIPS: Fix invalidate_dcache_range to operate on L1 Dcache Paul Burton
2016-06-09 12:09 ` [U-Boot] [PATCH 2/2] MIPS: Make CONFIG_SYS_DCACHE_LINE_SIZE int, not hex Paul Burton
2016-06-10 10:46 ` Daniel Schwierzeck [this message]
2016-06-10 10:42 ` [U-Boot] [PATCH 1/2] MIPS: Fix invalidate_dcache_range to operate on L1 Dcache Daniel Schwierzeck
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