From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Mon, 20 Jun 2016 04:58:42 +0200
Subject: [U-Boot] [PATCH 1/5] arm: Move check_cache_range() into a
	common place
In-Reply-To: <1466386991-10469-2-git-send-email-sjg@chromium.org>
References: <1466386991-10469-1-git-send-email-sjg@chromium.org>
 <1466386991-10469-2-git-send-email-sjg@chromium.org>
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To: u-boot@lists.denx.de

On 06/20/2016 03:43 AM, Simon Glass wrote:
> This code is common, so move it into a common file.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Marek Vasut <marex@denx.de>

> ---
> 
>  arch/arm/cpu/arm11/cpu.c       | 17 -----------------
>  arch/arm/cpu/arm926ejs/cache.c | 17 -----------------
>  arch/arm/cpu/armv7/cache_v7.c  | 17 -----------------
>  arch/arm/include/asm/cache.h   |  2 ++
>  arch/arm/lib/cache.c           | 22 ++++++++++++++++++++++
>  5 files changed, 24 insertions(+), 51 deletions(-)
> 
> diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c
> index 1e4c214..7244c2e 100644
> --- a/arch/arm/cpu/arm11/cpu.c
> +++ b/arch/arm/cpu/arm11/cpu.c
> @@ -69,23 +69,6 @@ void flush_dcache_all(void)
>  	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
>  }
>  
> -static int check_cache_range(unsigned long start, unsigned long stop)
> -{
> -	int ok = 1;
> -
> -	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
> -		ok = 0;
> -
> -	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
> -		ok = 0;
> -
> -	if (!ok)
> -		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
> -			start, stop);
> -
> -	return ok;
> -}
> -
>  void invalidate_dcache_range(unsigned long start, unsigned long stop)
>  {
>  	if (!check_cache_range(start, stop))
> diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
> index 2839c86..2119382 100644
> --- a/arch/arm/cpu/arm926ejs/cache.c
> +++ b/arch/arm/cpu/arm926ejs/cache.c
> @@ -29,23 +29,6 @@ void flush_dcache_all(void)
>  	);
>  }
>  
> -static int check_cache_range(unsigned long start, unsigned long stop)
> -{
> -	int ok = 1;
> -
> -	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
> -		ok = 0;
> -
> -	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
> -		ok = 0;
> -
> -	if (!ok)
> -		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
> -			start, stop);
> -
> -	return ok;
> -}
> -
>  void invalidate_dcache_range(unsigned long start, unsigned long stop)
>  {
>  	if (!check_cache_range(start, stop))
> diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
> index dc309da..823a156 100644
> --- a/arch/arm/cpu/armv7/cache_v7.c
> +++ b/arch/arm/cpu/armv7/cache_v7.c
> @@ -19,23 +19,6 @@
>  void v7_flush_dcache_all(void);
>  void v7_invalidate_dcache_all(void);
>  
> -static int check_cache_range(unsigned long start, unsigned long stop)
> -{
> -	int ok = 1;
> -
> -	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
> -		ok = 0;
> -
> -	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
> -		ok = 0;
> -
> -	if (!ok)
> -		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
> -			start, stop);
> -
> -	return ok;
> -}
> -
>  static u32 get_ccsidr(void)
>  {
>  	u32 ccsidr;
> diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
> index 1f63127..16e65c3 100644
> --- a/arch/arm/include/asm/cache.h
> +++ b/arch/arm/include/asm/cache.h
> @@ -29,6 +29,8 @@ static inline void invalidate_l2_cache(void)
>  }
>  #endif
>  
> +int check_cache_range(unsigned long start, unsigned long stop);
> +
>  void l2_cache_enable(void);
>  void l2_cache_disable(void);
>  void set_section_dcache(int section, enum dcache_option option);
> diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
> index 3bd8710..642a952 100644
> --- a/arch/arm/lib/cache.c
> +++ b/arch/arm/lib/cache.c
> @@ -10,6 +10,10 @@
>  #include <common.h>
>  #include <malloc.h>
>  
> +#ifndef CONFIG_SYS_CACHELINE_SIZE
> +#define CONFIG_SYS_CACHELINE_SIZE 32
> +#endif
> +
>  /*
>   * Flush range from all levels of d-cache/unified-cache.
>   * Affects the range [start, start + size - 1].
> @@ -46,6 +50,24 @@ __weak void flush_dcache_range(unsigned long start, unsigned long stop)
>  	/* An empty stub, real implementation should be in platform code */
>  }
>  
> +int check_cache_range(unsigned long start, unsigned long stop)
> +{
> +	int ok = 1;
> +
> +	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
> +		ok = 0;
> +
> +	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
> +		ok = 0;
> +
> +	if (!ok) {
> +		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
> +		      start, stop);
> +	}
> +
> +	return ok;
> +}
> +
>  #ifdef CONFIG_SYS_NONCACHED_MEMORY
>  /*
>   * Reserve one MMU section worth of address space below the malloc() area that
> 


-- 
Best regards,
Marek Vasut