From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= Date: Fri, 19 Apr 2013 13:32:41 +0200 (CEST) Subject: [U-Boot] [PATCH 5/6] arm: mx5: Add NAND clock handling In-Reply-To: <201304191318.06457.marex@denx.de> References: <1366344655-8535-1-git-send-email-marex@denx.de> <453481559.1870065.1366362123680.JavaMail.root@advansee.com> <1000802118.1870337.1366362490297.JavaMail.root@advansee.com> <201304191318.06457.marex@denx.de> Message-ID: <576873698.1874036.1366371161666.JavaMail.root@advansee.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Dear Marek Vasut, On Friday, April 19, 2013 1:18:06 PM, Marek Vasut wrote: > Dear Beno?t Th?baudeau, > > > On Friday, April 19, 2013 11:02:03 AM, Beno?t Th?baudeau wrote: > > > Dear Marek Vasut, > > > > > > On Friday, April 19, 2013 6:10:54 AM, Marek Vasut wrote: > > > > Augment the MX5 clock code with function to enable and configure > > > > NFC clock. This is necessary to get NFC working on MX5. > > > > > > > > Signed-off-by: Marek Vasut > > > > Cc: Albert ARIBAUD > > > > Cc: Beno?t Th?baudeau > > > > Cc: Fabio Estevam > > > > Cc: Scott Wood > > > > Cc: Stefano Babic > > > > Cc: Tom Rini > > > > --- > > > > > > > > arch/arm/cpu/armv7/mx5/clock.c | 14 ++++++++++++-- > > > > arch/arm/include/asm/arch-mx5/clock.h | 1 + > > > > 2 files changed, 13 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/arch/arm/cpu/armv7/mx5/clock.c > > > > b/arch/arm/cpu/armv7/mx5/clock.c > > > > index 76c2c52..431756e 100644 > > > > --- a/arch/arm/cpu/armv7/mx5/clock.c > > > > +++ b/arch/arm/cpu/armv7/mx5/clock.c > > > > @@ -739,10 +739,11 @@ static int config_core_clk(u32 ref, u32 freq) > > > > > > > > static int config_nfc_clk(u32 nfc_clk) > > > > { > > > > > > > > u32 parent_rate = get_emi_slow_clk(); > > > > > > > > - u32 div = parent_rate / nfc_clk; > > > > + u32 div; > > > > > > > > - if (nfc_clk <= 0) > > > > + if (nfc_clk == 0) > > > > > > > > return -EINVAL; > > > > > > > > + div = parent_rate / nfc_clk; > > > > > > > > if (div == 0) > > > > > > > > div++; > > > > > > > > if (parent_rate / div > NFC_CLK_MAX) > > > > > > > > @@ -755,6 +756,15 @@ static int config_nfc_clk(u32 nfc_clk) > > > > > > > > return 0; > > > > > > > > } > > > > > > > > +void enable_nfc_clk(unsigned char enable) > > > > +{ > > > > + unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; > > > > + > > > > + clrsetbits_le32(&mxc_ccm->CCGR5, > > > > + MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK), > > > > + MXC_CCM_CCGR5_EMI_ENFC(cg)); > > > > +} > > > > + > > > > > > > > /* Config main_bus_clock for periphs */ > > > > static int config_periph_clk(u32 ref, u32 freq) > > > > { > > > > > > > > diff --git a/arch/arm/include/asm/arch-mx5/clock.h > > > > b/arch/arm/include/asm/arch-mx5/clock.h > > > > index 9cdfb48..6910192 100644 > > > > --- a/arch/arm/include/asm/arch-mx5/clock.h > > > > +++ b/arch/arm/include/asm/arch-mx5/clock.h > > > > @@ -68,5 +68,6 @@ void set_usboh3_clk(void); > > > > > > > > void enable_usboh3_clk(unsigned char enable); > > > > void mxc_set_sata_internal_clock(void); > > > > int enable_i2c_clk(unsigned char enable, unsigned i2c_num); > > > > > > > > +void enable_nfc_clk(unsigned char enable); > > > > > > > > #endif /* __ASM_ARCH_CLOCK_H */ > > > > > > > > -- > > > > 1.7.11.7 > > > > > > Reviewed-by: Beno?t Th?baudeau > > > > Actually, this code is correct, but why is it needed? Indeed, this clock is > > already ungated by arch/arm/cpu/armv7/mx5/lowlevel_init.S. > > This is not good, the code should be moved away from the assembly. > > > Also, your board > > seems to be hardware-bootable only from NAND > > This is incorrect, it is bootable from SD card as well. > > > so in this case the boot ROM > > also ungates this clock itself. > > We can not rely on that. OK, then this patch is fine. Best regards, Beno?t