[U-Boot] [PATCH 2/3] FIX: mmc: sdhci: Board specific definitions for SDHCI CMD and READ TIMEOUTS

[Jaehoon Chung <jh80.chung@samsung.com>]

Hi Lukasz,

On 07/11/2016 09:49 PM, Lukasz Majewski wrote:
> For some boards - e.g. odroid u3, it is necessary to adjust manually those
> two timeouts.
> 
> Exynos4 based boards, which use SDHCI controller to read data from SD cards,
> have SDHCI_QUIRK_BROKEN_R1B flag set. This quirk requires short timeout
> values, since in fact it relies on timeout exit, because the controller is
> not able to read status bit properly for this kind of response.
> 
> Change: 29905a451b7ecf86785a4404e926fb14a8daced3, introduced longer timeouts
> for boards with SDHCI_QUIRK_BROKEN_R1B, which resulted in write speed
> regression (to ext4 fs via DFU):
> 
> Before (31 MiB test file):
> 32505856 bytes written in 4342 ms (7.1 MiB/s)
> 
> After this change:
> 32505856 bytes written in 20466 ms (1.5 MiB/s)
> 
> Such performance regression caused timeouts during DFU write (observed at
> HWT test setup).
> 
> This commit, however introduces possibility to define different timeout
> values for SDHCI mmc IP blocks embedded in different SoCs (and boards).
> 
> This problem was observed only in SDHCI controller, when target board was
> running solely from SD card.
> 
> Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
> ---
>  drivers/mmc/sdhci.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
> index aa4cd4f..9f38ecb 100644
> --- a/drivers/mmc/sdhci.c
> +++ b/drivers/mmc/sdhci.c
> @@ -126,8 +126,12 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
>  #ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT
>  #define CONFIG_SDHCI_CMD_MAX_TIMEOUT		3200
>  #endif
> +#ifndef CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT
>  #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT	100
> +#endif
> +#ifndef CONFIG_SDHCI_READ_STATUS_TIMEOUT
>  #define CONFIG_SDHCI_READ_STATUS_TIMEOUT	1000
> +#endif
>  
>  static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
>  		       struct mmc_data *data)
> 

I have checked this..it's right. how about the below code?
I just applied the below patch..then i saw the similar performance.

--- a/drivers/mmc/s5p_sdhci.c
+++ b/drivers/mmc/s5p_sdhci.c
@@ -68,7 +68,7 @@ static int s5p_sdhci_core_init(struct sdhci_host *host)
        host->name = S5P_NAME;

        host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
-               SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
+               SDHCI_QUIRK_32BIT_DMA_ADDR |
                SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8;
        host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
        host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 604f18d..0a38a56 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -175,7 +175,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
                flags = SDHCI_CMD_RESP_LONG;
        else if (cmd->resp_type & MMC_RSP_BUSY) {
                flags = SDHCI_CMD_RESP_SHORT_BUSY;
-               mask |= SDHCI_INT_DATA_END;
+               if (data)
+                       mask |= SDHCI_INT_DATA_END;
        } else
                flags = SDHCI_CMD_RESP_SHORT;

I think it doesn't needs to set SDHCI_INT_DATA_END.(I think that it can be just removed.)

I have tested with this on Exynos4 boards. It's working fine for eMMC/SD.
Could you check this patch?

Best Regards,
Jaehoon Chung