From: Michal Simek <monstr@monstr.eu>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 8/8] xtensa: add support for the 'xtfpga' evaluation board
Date: Wed, 13 Jul 2016 08:35:37 +0200 [thread overview]
Message-ID: <5785E139.50903@monstr.eu> (raw)
In-Reply-To: <1467992526-13417-9-git-send-email-jcmvbkbc@gmail.com>
On 8.7.2016 17:42, Max Filippov wrote:
> From: Chris Zankel <chris@zankel.net>
>
> The 'xtfpga' board is actually a set of FPGA evaluation boards that
> can be configured to run an Xtensa processor.
>
> - Avnet Xilinx LX60
> - Avnet Xilinx LX110
> - Avnet Xilinx LX200
> - Xilinx ML605
> - Xilinx KC705
>
> These boards share the same components (open-ethernet, ns16550 serial,
> lcd display, flash, etc.).
>
> Signed-off-by: Chris Zankel <chris@zankel.net>
> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
> ---
> arch/xtensa/Kconfig | 3 +
> arch/xtensa/dts/Makefile | 2 +
> arch/xtensa/dts/kc705.dts | 15 ++
> arch/xtensa/dts/kc705_nommu.dts | 17 ++
> arch/xtensa/dts/ml605.dts | 15 ++
> arch/xtensa/dts/ml605_nommu.dts | 18 +++
> arch/xtensa/dts/xtfpga-flash-128m.dtsi | 28 ++++
> arch/xtensa/dts/xtfpga-flash-16m.dtsi | 28 ++++
> arch/xtensa/dts/xtfpga.dtsi | 137 ++++++++++++++++
> board/cadence/xtfpga/Kconfig | 43 +++++
> board/cadence/xtfpga/MAINTAINERS | 6 +
> board/cadence/xtfpga/Makefile | 8 +
> board/cadence/xtfpga/README | 125 ++++++++++++++
> board/cadence/xtfpga/lcd.c | 88 ++++++++++
> board/cadence/xtfpga/lcd.h | 12 ++
> board/cadence/xtfpga/xtfpga.c | 173 ++++++++++++++++++++
> configs/xtfpga_defconfig | 13 ++
> include/configs/xtfpga.h | 286 +++++++++++++++++++++++++++++++++
> 18 files changed, 1017 insertions(+)
> create mode 100644 arch/xtensa/dts/kc705.dts
> create mode 100644 arch/xtensa/dts/kc705_nommu.dts
> create mode 100644 arch/xtensa/dts/ml605.dts
> create mode 100644 arch/xtensa/dts/ml605_nommu.dts
> create mode 100644 arch/xtensa/dts/xtfpga-flash-128m.dtsi
> create mode 100644 arch/xtensa/dts/xtfpga-flash-16m.dtsi
> create mode 100644 arch/xtensa/dts/xtfpga.dtsi
> create mode 100644 board/cadence/xtfpga/Kconfig
> create mode 100644 board/cadence/xtfpga/MAINTAINERS
> create mode 100644 board/cadence/xtfpga/Makefile
> create mode 100644 board/cadence/xtfpga/README
> create mode 100644 board/cadence/xtfpga/lcd.c
> create mode 100644 board/cadence/xtfpga/lcd.h
> create mode 100644 board/cadence/xtfpga/xtfpga.c
> create mode 100644 configs/xtfpga_defconfig
> create mode 100644 include/configs/xtfpga.h
>
> diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
> index e4e3625..d41949f 100644
> --- a/arch/xtensa/Kconfig
> +++ b/arch/xtensa/Kconfig
> @@ -11,9 +11,12 @@ config SYS_CPU
> choice
> prompt "Target select"
>
> +config TARGET_XTFPGA
> + bool "Support XTFPGA"
>
> endchoice
>
> +source "board/cadence/xtfpga/Kconfig"
>
> config HAVE_SYS_ASCDISP
> bool
> diff --git a/arch/xtensa/dts/Makefile b/arch/xtensa/dts/Makefile
> index eacf6f3..e14cdac 100644
> --- a/arch/xtensa/dts/Makefile
> +++ b/arch/xtensa/dts/Makefile
> @@ -2,6 +2,8 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
>
> +dtb-$(CONFIG_XTFPGA) += ml605.dtb ml605_nommu.dtb kc705.dtb kc705_nommu.dtb
> +
> targets += $(dtb-y)
>
> DTC_FLAGS +=
> diff --git a/arch/xtensa/dts/kc705.dts b/arch/xtensa/dts/kc705.dts
> new file mode 100644
> index 0000000..3b89e83
> --- /dev/null
> +++ b/arch/xtensa/dts/kc705.dts
> @@ -0,0 +1,15 @@
> +/dts-v1/;
> +/include/ "xtfpga.dtsi"
> +/include/ "xtfpga-flash-128m.dtsi"
> +
> +/ {
> + compatible = "cdns,xtensa-kc705";
> + chosen {
> + bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
> + stdout-path = &serial0;
> + };
> + memory at 0 {
> + device_type = "memory";
> + reg = <0x00000000 0x38000000>;
> + };
> +};
> diff --git a/arch/xtensa/dts/kc705_nommu.dts b/arch/xtensa/dts/kc705_nommu.dts
> new file mode 100644
> index 0000000..57f0dab
> --- /dev/null
> +++ b/arch/xtensa/dts/kc705_nommu.dts
> @@ -0,0 +1,17 @@
> +/dts-v1/;
> +/include/ "xtfpga.dtsi"
> +/include/ "xtfpga-flash-128m.dtsi"
> +
> +/ {
> + compatible = "cdns,xtensa-kc705";
> + chosen {
> + bootargs = "earlycon=uart8250,mmio32native,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
> + };
> + memory at 0 {
> + device_type = "memory";
> + reg = <0x60000000 0x10000000>;
> + };
> + soc {
> + ranges = <0x00000000 0x90000000 0x10000000>;
> + };
> +};
> diff --git a/arch/xtensa/dts/ml605.dts b/arch/xtensa/dts/ml605.dts
> new file mode 100644
> index 0000000..f323f96
> --- /dev/null
> +++ b/arch/xtensa/dts/ml605.dts
> @@ -0,0 +1,15 @@
> +/dts-v1/;
> +/include/ "xtfpga.dtsi"
> +/include/ "xtfpga-flash-16m.dtsi"
> +
> +/ {
> + compatible = "cdns,xtensa-ml605";
> + chosen {
> + bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
> + stdout-path = &serial0;
> + };
> + memory at 0 {
> + device_type = "memory";
> + reg = <0x00000000 0x18000000>;
> + };
> +};
> diff --git a/arch/xtensa/dts/ml605_nommu.dts b/arch/xtensa/dts/ml605_nommu.dts
> new file mode 100644
> index 0000000..6bdf400
> --- /dev/null
> +++ b/arch/xtensa/dts/ml605_nommu.dts
> @@ -0,0 +1,18 @@
> +/dts-v1/;
> +/include/ "xtfpga.dtsi"
> +/include/ "xtfpga-flash-16m.dtsi"
> +
> +/ {
> + compatible = "cdns,xtensa-ml605";
> + chosen {
> + bootargs = "earlycon=uart8250,mmio32native,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
> + stdout-path = &serial0;
> + };
> + memory at 0 {
> + device_type = "memory";
> + reg = <0x00000000 0x10000000>;
> + };
> + soc {
> + ranges = <0x00000000 0x90000000 0x10000000>;
> + };
> +};
> diff --git a/arch/xtensa/dts/xtfpga-flash-128m.dtsi b/arch/xtensa/dts/xtfpga-flash-128m.dtsi
> new file mode 100644
> index 0000000..d3a88e0
> --- /dev/null
> +++ b/arch/xtensa/dts/xtfpga-flash-128m.dtsi
> @@ -0,0 +1,28 @@
> +/ {
> + soc {
> + flash: flash at 00000000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "cfi-flash";
> + reg = <0x00000000 0x08000000>;
> + bank-width = <2>;
> + device-width = <2>;
> + partition at 0x0 {
> + label = "data";
> + reg = <0x00000000 0x06000000>;
> + };
> + partition at 0x6000000 {
> + label = "boot loader area";
> + reg = <0x06000000 0x00800000>;
> + };
> + partition at 0x6800000 {
> + label = "kernel image";
> + reg = <0x06800000 0x017e0000>;
> + };
> + partition at 0x7fe0000 {
> + label = "boot environment";
> + reg = <0x07fe0000 0x00020000>;
> + };
> + };
> + };
> +};
> diff --git a/arch/xtensa/dts/xtfpga-flash-16m.dtsi b/arch/xtensa/dts/xtfpga-flash-16m.dtsi
> new file mode 100644
> index 0000000..1d97203
> --- /dev/null
> +++ b/arch/xtensa/dts/xtfpga-flash-16m.dtsi
> @@ -0,0 +1,28 @@
> +/ {
> + soc {
> + flash: flash at 08000000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "cfi-flash";
> + reg = <0x08000000 0x01000000>;
> + bank-width = <2>;
> + device-width = <2>;
> + partition at 0x0 {
> + label = "boot loader area";
> + reg = <0x00000000 0x00400000>;
> + };
> + partition at 0x400000 {
> + label = "kernel image";
> + reg = <0x00400000 0x00600000>;
> + };
> + partition at 0xa00000 {
> + label = "data";
> + reg = <0x00a00000 0x005e0000>;
> + };
> + partition at 0xfe0000 {
> + label = "boot environment";
> + reg = <0x00fe0000 0x00020000>;
> + };
> + };
> + };
> +};
> diff --git a/arch/xtensa/dts/xtfpga.dtsi b/arch/xtensa/dts/xtfpga.dtsi
> new file mode 100644
> index 0000000..cd45f9c
> --- /dev/null
> +++ b/arch/xtensa/dts/xtfpga.dtsi
> @@ -0,0 +1,137 @@
> +/ {
> + compatible = "cdns,xtensa-xtfpga";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <&pic>;
> +
> + chosen {
> + bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
> + };
> +
> + memory at 0 {
> + device_type = "memory";
> + reg = <0x00000000 0x06000000>;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu at 0 {
> + compatible = "cdns,xtensa-cpu";
> + reg = <0>;
> + /* Filled in by platform_setup from FPGA register
> + * clock-frequency = <100000000>;
> + */
> + };
> + };
> +
> + pic: pic {
> + compatible = "cdns,xtensa-pic";
> + /* one cell: internal irq number,
> + * two cells: second cell == 0: internal irq number
> + * second cell == 1: external irq number
> + */
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + };
> +
> + clocks {
> + osc: main-oscillator {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + };
> +
> + clk54: clk54 {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <54000000>;
> + };
> + };
> +
> + soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "simple-bus";
> + ranges = <0x00000000 0xf0000000 0x10000000>;
> +
> + serial0: serial at 0d050020 {
> + device_type = "serial";
> + compatible = "ns16550a";
> + no-loopback-test;
> + reg = <0x0d050020 0x20>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + native-endian;
> + interrupts = <0 1>; /* external irq 0 */
> + clocks = <&osc>;
> + };
> +
> + enet0: ethoc at 0d030000 {
> + compatible = "opencores,ethoc";
> + reg = <0x0d030000 0x4000 0x0d800000 0x4000>;
> + native-endian;
> + interrupts = <1 1>; /* external irq 1 */
> + local-mac-address = [00 50 c2 13 6f 00];
> + clocks = <&osc>;
> + };
> +
> + i2s0: xtfpga-i2s at 0d080000 {
> + #sound-dai-cells = <0>;
> + compatible = "cdns,xtfpga-i2s";
> + reg = <0x0d080000 0x40>;
> + interrupts = <2 1>; /* external irq 2 */
> + clocks = <&cdce706 4>;
> + };
> +
> + i2c0: i2c-master at 0d090000 {
> + compatible = "opencores,i2c-ocores";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0d090000 0x20>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + native-endian;
> + interrupts = <4 1>;
> + clocks = <&osc>;
> +
> + cdce706: clock-synth at 69 {
> + compatible = "ti,cdce706";
> + #clock-cells = <1>;
> + reg = <0x69>;
> + clocks = <&clk54>;
> + clock-names = "clk_in0";
> + };
> + };
> +
> + spi0: spi-master at 0d0a0000 {
> + compatible = "cdns,xtfpga-spi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0d0a0000 0xc>;
> +
> + tlv320aic23: sound-codec at 0 {
> + #sound-dai-cells = <0>;
> + compatible = "tlv320aic23";
> + reg = <0>;
> + spi-max-frequency = <12500000>;
> + };
> + };
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,mclk-fs = <256>;
> +
> + simple-audio-card,cpu {
> + sound-dai = <&i2s0>;
> + };
> +
> + simple-audio-card,codec {
> + sound-dai = <&tlv320aic23>;
> + simple-audio-card,bitclock-master = <0>;
> + simple-audio-card,frame-master = <0>;
> + clocks = <&cdce706 4>;
> + };
> + };
> +};
> diff --git a/board/cadence/xtfpga/Kconfig b/board/cadence/xtfpga/Kconfig
> new file mode 100644
> index 0000000..a7b65ef
> --- /dev/null
> +++ b/board/cadence/xtfpga/Kconfig
> @@ -0,0 +1,43 @@
> +if TARGET_XTFPGA
> +
> +choice
> + prompt "XTFPGA board type select"
> +
> +config XTFPGA_LX60
> + bool "Support Avnet LX60"
> + select HAVE_SYS_ASCDISP
> +config XTFPGA_LX110
> + bool "Support Avnet LX110"
> + select HAVE_SYS_ASCDISP
> +config XTFPGA_LX200
> + bool "Support Avnet LX200"
> +config XTFPGA_ML605
> + bool "Support Xilinx ML605"
> + select HAVE_SYS_ASCDISP
> +config XTFPGA_KC705
> + bool "Support Xilinx KC705"
> + select HAVE_SYS_ASCDISP
> +
> +endchoice
> +
> +config SYS_BOARD
> + string
> + default "xtfpga"
> +
> +config SYS_VENDOR
> + string
> + default "cadence"
> +
> +config SYS_CONFIG_NAME
> + string
> + default "xtfpga"
> +
> +config BOARD_SDRAM_SIZE
> + hex
> + default 0x04000000 if XTFPGA_LX60
> + default 0x03000000 if XTFPGA_LX110
> + default 0x06000000 if XTFPGA_LX200
> + default 0x18000000 if XTFPGA_ML605
> + default 0x38000000 if XTFPGA_KC705
You should read this directly from DTS files.
The same you have below in config.
Thanks,
Michal
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next prev parent reply other threads:[~2016-07-13 6:35 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-08 15:41 [U-Boot] [PATCH v2 0/8] U-Boot port to Xtensa architecture Max Filippov
2016-07-08 15:41 ` [U-Boot] [PATCH 1/8] xtensa: add support for the xtensa processor architecture [1/2] Max Filippov
2016-07-12 21:56 ` Simon Glass
2016-07-14 21:55 ` Max Filippov
2016-07-08 15:42 ` [U-Boot] [PATCH 2/8] xtensa: add support for the xtensa processor architecture [2/2] Max Filippov
2016-07-12 21:56 ` Simon Glass
2016-07-14 22:58 ` Max Filippov
2016-07-15 0:20 ` Simon Glass
2016-07-08 15:42 ` [U-Boot] [PATCH 3/8] xtensa: add core information for the dc232b processor Max Filippov
2016-07-12 21:56 ` Simon Glass
2016-07-14 23:15 ` Max Filippov
2016-07-15 0:20 ` Simon Glass
2016-07-08 15:42 ` [U-Boot] [PATCH 4/8] xtensa: add core information for the dc233c processor Max Filippov
2016-07-12 21:56 ` Simon Glass
2016-07-14 23:19 ` Max Filippov
2016-07-08 15:42 ` [U-Boot] [PATCH 5/8] xtensa: add core information for the de212 processor Max Filippov
2016-07-12 21:56 ` Simon Glass
2016-07-14 23:20 ` Max Filippov
2016-07-08 15:42 ` [U-Boot] [PATCH 6/8] net/ethoc: support private memory configurations Max Filippov
2016-07-12 21:56 ` Simon Glass
2016-07-14 23:34 ` Max Filippov
2016-07-15 0:20 ` Simon Glass
2016-07-08 15:42 ` [U-Boot] [PATCH 7/8] net/ethoc: don't advertise gigabit on the connected PHY Max Filippov
2016-07-12 21:56 ` Simon Glass
2016-07-14 23:41 ` Max Filippov
2016-07-13 6:28 ` Michal Simek
2016-07-14 23:51 ` Max Filippov
2016-07-08 15:42 ` [U-Boot] [PATCH 8/8] xtensa: add support for the 'xtfpga' evaluation board Max Filippov
2016-07-12 21:57 ` Simon Glass
2016-07-15 0:13 ` Max Filippov
2016-07-13 6:35 ` Michal Simek [this message]
2016-07-15 0:04 ` Max Filippov
-- strict thread matches above, loose matches on Subject: below --
2014-08-20 17:42 [U-Boot] [PATCH 0/8] U-Boot port to Xtensa architecture Max Filippov
2014-08-20 17:42 ` [U-Boot] [PATCH 8/8] xtensa: add support for the 'xtfpga' evaluation board Max Filippov
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