From mboxrd@z Thu Jan  1 00:00:00 1970
From: Keerthy <a0393675@ti.com>
Date: Tue, 2 Aug 2016 17:29:20 +0530
Subject: [U-Boot] Question on Enabling hypervisor mode in u-boot
In-Reply-To: <579FFD45.4030805@ti.com>
References: <579F1F7B.2090504@ti.com>
 <21F98B1B-D7ED-4F0A-A4FC-9F45DADF0986@suse.de> <579FFD45.4030805@ti.com>
Message-ID: <57A08B18.30200@ti.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

Hi Alex,


On Tuesday 02 August 2016 07:24 AM, Keerthy wrote:
>
>
> On Tuesday 02 August 2016 03:16 AM, Alexander Graf wrote:
>>
>>> On 01 Aug 2016, at 11:07, Keerthy <a0393675@ti.com> wrote:
>>>
>>> Hi Alexander,
>>>
>>> I am trying to enable hypervisor in u-boot for DRA7(A15 based) family
>>> of SoCs which does not have LPAE support yet.
>>>
>>> Is it mandatory for LPAE to be enabled before enabling hypervisor for
>>> A15?
>>
>> HYP mode shares the same page table layout as the LPAE one. I?m
>> actually surprised you managed to configure an A15 without LPAE. Are
>> you sure it doesn?t support it?
>
> I meant CONFIG_LPAE not enabled yet in our defconfig. I was trying to
> get hyp mode enabled and saw that enabling LPAE config seemed mandatory
> as per your commit.

I am referring 
http://liris.cnrs.fr/~mmrissa/lib/exe/fetch.php?media=armv7-a-r-manual.pdf.

Attrm[3:0] bits for DCACHE_WRITEALLOC, DCACHE_WRITEBACK, 
DCACHE_WRITETHROUGH definitions.

DCACHE_WRITEBACK should have 0x3 << 2 to get 11RW for MAIRn.Attrm[3:0] 
encoding.

Correct me if i am wrong of referring a wrong document.


Regards,
Keerthy

>
>>
>>
>> Alex
>>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot