[U-Boot] Question on Enabling hypervisor mode in u-boot

[Keerthy <a0393675@ti.com>]

On Thursday 04 August 2016 10:51 AM, Alexander Graf wrote:
>
>> On 02 Aug 2016, at 12:59, Keerthy <a0393675@ti.com> wrote:
>>
>> Hi Alex,
>>
>>
>> On Tuesday 02 August 2016 07:24 AM, Keerthy wrote:
>>>
>>>
>>> On Tuesday 02 August 2016 03:16 AM, Alexander Graf wrote:
>>>>
>>>>> On 01 Aug 2016, at 11:07, Keerthy <a0393675@ti.com> wrote:
>>>>>
>>>>> Hi Alexander,
>>>>>
>>>>> I am trying to enable hypervisor in u-boot for DRA7(A15 based) family
>>>>> of SoCs which does not have LPAE support yet.
>>>>>
>>>>> Is it mandatory for LPAE to be enabled before enabling hypervisor for
>>>>> A15?
>>>>
>>>> HYP mode shares the same page table layout as the LPAE one. I?m
>>>> actually surprised you managed to configure an A15 without LPAE. Are
>>>> you sure it doesn?t support it?
>>>
>>> I meant CONFIG_LPAE not enabled yet in our defconfig. I was trying to
>>> get hyp mode enabled and saw that enabling LPAE config seemed mandatory
>>> as per your commit.
>>
>> I am referring http://liris.cnrs.fr/~mmrissa/lib/exe/fetch.php?media=armv7-a-r-manual.pdf.
>>
>> Attrm[3:0] bits for DCACHE_WRITEALLOC, DCACHE_WRITEBACK, DCACHE_WRITETHROUGH definitions.
>>
>> DCACHE_WRITEBACK should have 0x3 << 2 to get 11RW for MAIRn.Attrm[3:0] encoding.
>>
>> Correct me if i am wrong of referring a wrong document.
>
> I?m not quite sure I understand your issue correctly. If you want to run in HYP mode, the only page table format available is the ?long-descriptor? page table format, which is the same as the LPAE page table format. That?s the one that also puts the caching modes into MAIR registers instead of the PTEs.
>
> So if you want to enable page tables (which you need to enable in order to enable caching), you have to write page tables in the LPAE format if you?re running in HYP mode. That?s why the config option is mandatory.
>
> See sections B3.1.3 and B3.3 in the document you linked to:
>
>    "the translation tables for the Non-secure PL2 stage 1 translations, and for the Non-secure PL1&0 stage 2 translations, must use the Long-descriptor translation table format."

Thanks for the confirmations and pointers. I will go through that part 
of ARM documentation.

Best Regards,
Keerthy


>
>
> Alex
>