[U-Boot] [PATCH v4] arm: cache: always flush cache line size for page table

[Heiko Schocher <hs@denx.de>]

Hello Stefan,

Am 07.08.2016 um 19:43 schrieb Stefan Agner:
> From: Stefan Agner <stefan.agner@toradex.com>
>
> The page table is maintained by the CPU, hence it is safe to always
> align cache flush to a whole cache line size. This allows to use
> mmu_page_table_flush for a single page table, e.g. when configure
> only small regions through mmu_set_region_dcache_behaviour.
>
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v4:
> - Fixed spelling misstake for real
>
> Changes in v3:
> - Fixed spelling misstake
>
> Changes in v2:
> - Move cache line alignment from mmu_page_table_flush to
>    mmu_set_region_dcache_behaviour
>
>   arch/arm/lib/cache-cp15.c | 13 ++++++++++++-
>   1 file changed, 12 insertions(+), 1 deletion(-)

Reviewed-by: Heiko Schocher <hs@denx.de>

bye,
Heiko
>
> diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
> index 1121dc3..488094e 100644
> --- a/arch/arm/lib/cache-cp15.c
> +++ b/arch/arm/lib/cache-cp15.c
> @@ -62,6 +62,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
>   				     enum dcache_option option)
>   {
>   	u32 *page_table = (u32 *)gd->arch.tlb_addr;
> +	phys_addr_t startpt, stoppt;
>   	unsigned long upto, end;
>
>   	end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
> @@ -70,7 +71,17 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
>   	      option);
>   	for (upto = start; upto < end; upto++)
>   		set_section_dcache(upto, option);
> -	mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
> +
> +	/*
> +	 * Make sure range is cache line aligned
> +	 * Only CPU maintains page tables, hence it is safe to always
> +	 * flush complete cache lines...
> +	 */
> +	startpt = (phys_addr_t)&page_table[start];
> +	startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
> +	stoppt = (phys_addr_t)&page_table[end];
> +	stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
> +	mmu_page_table_flush(startpt, stoppt);
>   }
>
>   __weak void dram_bank_mmu_setup(int bank)
>

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