[U-Boot] [PATCH 3/4] usb: dwc3: add support for 16 bit UTMI+ interface

[Kever Yang <kever.yang@rock-chips.com>]

Hi Marek,

On 08/17/2016 09:39 AM, Marek Vasut wrote:
> On 08/17/2016 03:31 AM, Kever Yang wrote:
>> Hi Marek,
> Hi,
>
>> On 08/16/2016 09:18 PM, Marek Vasut wrote:
>>> On 08/16/2016 12:03 PM, Kever Yang wrote:
>>>> The dwc3 controller is using 8 bit UTMI+ interface for USB2.0 PHY,
>>>> add one MACRO CONFIG_USB_DWC3_USB2PHY_16BIT to support 16 bit
>>>> UTMI+ interface on some SoCs like Rockchip rk3399.
>>>>
>>>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>>> This should be configured from either DT or Kconfig option.
>> This setting in kernel is from DT, but we do not use DT for gadget mode
>> in U-Boot.
>> How about we add a quirk for it like u2phy_utmi_width_quirk in both
>> dwc3_device
>> and dwc3 struct for device mode?
>>
>> For Host mode, we can get from DT and also need a quirk to store it.
> Surely, if you can get this info from DT for host mode, you can also get
> it from DT for gadget mode, yes ?

No, for gadget mode, the controller is init by board_usb_init() called 
from cmd like fastboot,
there is no uclass driver for a udc driver and no one parse the DT 
currently.

You can see my patch "[PATCH 2/4] board: evb-rk3399: add api to support 
dwc3 gadget"
for how it initialized.

Thanks,
- Kever

>
>> Thanks,
>> - Kever
>>>> ---
>>>>
>>>>    drivers/usb/dwc3/core.c | 10 ++++++++++
>>>>    drivers/usb/dwc3/core.h | 11 +++++++++++
>>>>    2 files changed, 21 insertions(+)
>>>>
>>>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>>>> index 85cc96a..7141d11 100644
>>>> --- a/drivers/usb/dwc3/core.c
>>>> +++ b/drivers/usb/dwc3/core.c
>>>> @@ -75,6 +75,11 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
>>>>        /* Clear USB2 PHY reset */
>>>>        reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
>>>>        reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
>>>> +#ifdef CONFIG_USB_DWC3_USB2PHY_16BIT
>>>> +    reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
>>>> +    reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
>>>> +    reg |= DWC3_GUSB2PHYCFG_PHYIF_16BIT;
>>>> +#endif
>>>>        dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
>>>>          mdelay(100);
>>>> @@ -388,6 +393,11 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
>>>>        if (dwc->dis_u2_susphy_quirk)
>>>>            reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
>>>>    +#ifdef CONFIG_USB_DWC3_USB2PHY_16BIT
>>>> +    reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
>>>> +    reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
>>>> +    reg |= DWC3_GUSB2PHYCFG_PHYIF_16BIT;
>>>> +#endif
>>>>        dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
>>>>          mdelay(100);
>>>> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
>>>> index 72d2fcd..b4f3963 100644
>>>> --- a/drivers/usb/dwc3/core.h
>>>> +++ b/drivers/usb/dwc3/core.h
>>>> @@ -74,6 +74,7 @@
>>>>    #define DWC3_GCTL        0xc110
>>>>    #define DWC3_GEVTEN        0xc114
>>>>    #define DWC3_GSTS        0xc118
>>>> +#define DWC3_GUCTL1        0xc11c
>>>>    #define DWC3_GSNPSID        0xc120
>>>>    #define DWC3_GGPIO        0xc124
>>>>    #define DWC3_GUID        0xc128
>>>> @@ -162,7 +163,17 @@
>>>>      /* Global USB2 PHY Configuration Register */
>>>>    #define DWC3_GUSB2PHYCFG_PHYSOFTRST    (1 << 31)
>>>> +#define DWC3_GUSB2PHYCFG_ENBLSLPM   (1 << 8)
>>>>    #define DWC3_GUSB2PHYCFG_SUSPHY        (1 << 6)
>>>> +#define DWC3_GUSB2PHYCFG_PHYIF_8BIT    (0 << 3)
>>>> +#define DWC3_GUSB2PHYCFG_PHYIF_16BIT    (1 << 3)
>>>> +#define DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT    (10)
>>>> +#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK    (0xf << \
>>>> +        DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT)
>>>> +#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \
>>>> +        DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT)
>>>> +#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \
>>>> +        DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT)
>>>>      /* Global USB3 PIPE Control Register */
>>>>    #define DWC3_GUSB3PIPECTL_PHYSOFTRST    (1 << 31)
>>>>
>>
>