From mboxrd@z Thu Jan  1 00:00:00 1970
From: Kever Yang <kever.yang@rock-chips.com>
Date: Wed, 24 Aug 2016 11:06:45 +0800
Subject: [U-Boot] [PATCH v2 1/7] usb: xhci-rockchip: add rockchip dwc3
 controller driver
In-Reply-To: <46132467-7a85-fb68-7b67-48699ae4d2d8@denx.de>
References: <1471591170-7633-1-git-send-email-kever.yang@rock-chips.com>
 <1471591170-7633-2-git-send-email-kever.yang@rock-chips.com>
 <46132467-7a85-fb68-7b67-48699ae4d2d8@denx.de>
Message-ID: <57BD0F45.1010906@rock-chips.com>
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To: u-boot@lists.denx.de

Hi Marek,

On 08/19/2016 06:52 PM, Marek Vasut wrote:
> On 08/19/2016 09:19 AM, Kever Yang wrote:
>> From: MengDongyang <daniel.meng@rock-chips.com>
>>
>> This patch add support for rockchip dwc3 controller, which corresponding
>> to the two type-C port on rk3399 evb.
>> Only support usb2.0 currently for we have not enable the usb3.0 phy
>> driver and PD(fusb302) driver.
>>
>> Signed-off-by: MengDongyang <daniel.meng@rock-chips.com>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Hi,
>
> [...]
>
>> +static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg,
>> +				    struct rockchip_xhci *rockchip)
>> +{
>> +	u32 reg;
>> +	const void *blob = gd->fdt_blob;
>> +	struct udevice *dev = rockchip->dev;
>> +	const struct fdt_property *prop;
>> +	const u32 *data;
>> +
>> +	reg = readl(&dwc3_reg->g_usb3pipectl[0]);
>> +
>> +	/* To do set dwc3 usb3 pipe control */
>> +
>> +	writel(reg, &dwc3_reg->g_usb3pipectl[0]);
> This read - do nothing - write looks suspicious. Is this needed ?

This is for usb3.0 phy, will remove in next version for we not enable 
usb3.0 phy  now.
>
> Also, drop the newline after the comment, it's useless, both above and
> below here.

Will fix in next version.

Thanks,
- Kever
>
>> +	/* Set dwc3 usb2 phy config */
>> +
>> +	reg = readl(&dwc3_reg->g_usb2phycfg[0]);
>> +
>> +	prop = fdt_get_property(blob, dev->of_offset,
>> +				"snps,dis-enblslpm-quirk", NULL);
>> +	if (prop)
>> +		reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
>> +
>> +	prop = fdt_get_property(blob, dev->of_offset,
>> +				"snps,phyif-utmi-bits", NULL);
>> +	data = (u32 *)prop->data;
>> +	if (fdt32_to_cpu(*data) == 16) {
>> +		reg |= DWC3_GUSB2PHYCFG_PHYIF;
>> +		reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
>> +		reg |= 5 << DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET;
>> +	} else if (fdt32_to_cpu(*data) == 8) {
>> +		reg &= ~DWC3_GUSB2PHYCFG_PHYIF;
>> +		reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
>> +		reg |= 9 << DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET;
>> +	}
>> +
>> +	prop = fdt_get_property(blob, dev->of_offset,
>> +				"snps,dis-u2-freeclk-exists-quirk", NULL);
>> +	if (prop)
>> +		reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
>> +
>> +	prop = fdt_get_property(blob, dev->of_offset,
>> +				"snps,dis-u2-susphy-quirk", NULL);
>> +	if (prop)
>> +		reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
>> +
>> +	writel(reg, &dwc3_reg->g_usb2phycfg[0]);
>> +}
> [...]
>