From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kever Yang Date: Tue, 06 Sep 2016 17:52:17 +0800 Subject: [U-Boot] [PATCH 1/7] rockchip: rk3399: update PPLL and pmu_pclk frequency In-Reply-To: References: <1472526134-26965-1-git-send-email-kever.yang@rock-chips.com> <1472526134-26965-2-git-send-email-kever.yang@rock-chips.com> Message-ID: <57CE91D1.3080401@rock-chips.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Simon, On 09/06/2016 09:03 AM, Simon Glass wrote: > Hi Kever, > > On 29 August 2016 at 21:02, Kever Yang wrote: >> This patch update PPLL to 676MHz and PMU_PCLK to 48MHz. > Why? > 1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz can not, 2. We think 48MHz is fast enough for pmu pclk and it is lower power cost than 99MHz, 3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using internally for kernel, it suppose not to change the bus clock like pmu_pclk in kernel, so we want to change it in uboot. Thanks, - Kever >> Signed-off-by: Kever Yang >> --- >> >> arch/arm/include/asm/arch-rockchip/cru_rk3399.h | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h >> index c919f47..6776e48 100644 >> --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h >> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h >> @@ -64,9 +64,9 @@ check_member(rk3399_cru, sdio1_con[1], 0x594); >> #define APLL_HZ (600*MHz) >> #define GPLL_HZ (594*MHz) >> #define CPLL_HZ (384*MHz) >> -#define PPLL_HZ (594*MHz) >> +#define PPLL_HZ (676*MHz) >> >> -#define PMU_PCLK_HZ (99*MHz) >> +#define PMU_PCLK_HZ (48*MHz) >> >> #define ACLKM_CORE_HZ (300*MHz) >> #define ATCLK_CORE_HZ (300*MHz) >> -- >> 1.9.1 >> > Regards, > Simon > > >