* [U-Boot] [PATCH] net, cmd: fix misaligned cache operation warning
@ 2016-08-29 5:46 Heiko Schocher
2016-10-02 12:03 ` [U-Boot] " Tom Rini
0 siblings, 1 reply; 6+ messages in thread
From: Heiko Schocher @ 2016-08-29 5:46 UTC (permalink / raw)
To: u-boot
when using tftp on the smartweb board, it prints, when
using the tftp command:
Using ethernet at fffc4000 device
TFTP from server 192.168.1.1; our IP address is 192.168.20.80
Filename '/tftpboot/smartweb_hw/tbot/u-boot.bin'.
Load address: 0x21000000
Loading: ###########################
73.2 KiB/s
done
Bytes transferred = 391560 (5f988 hex)
CACHE: Misaligned operation at range [21000000, 2105f988]
U-Boot#
Fixing this.
Signed-off-by: Heiko Schocher <hs@denx.de>
---
cmd/net.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cmd/net.c b/cmd/net.c
index b2f3c7b..540daeb 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -244,7 +244,7 @@ static int netboot_common(enum proto_t proto, cmd_tbl_t *cmdtp, int argc,
}
/* flush cache */
- flush_cache(load_addr, size);
+ flush_cache(load_addr, ALIGN(size, CONFIG_SYS_CACHELINE_SIZE));
bootstage_mark(BOOTSTAGE_ID_NET_LOADED);
--
2.5.5
^ permalink raw reply related [flat|nested] 6+ messages in thread* [U-Boot] net, cmd: fix misaligned cache operation warning
2016-08-29 5:46 [U-Boot] [PATCH] net, cmd: fix misaligned cache operation warning Heiko Schocher
@ 2016-10-02 12:03 ` Tom Rini
2016-10-02 12:06 ` Joe Hershberger
0 siblings, 1 reply; 6+ messages in thread
From: Tom Rini @ 2016-10-02 12:03 UTC (permalink / raw)
To: u-boot
On Mon, Aug 29, 2016 at 07:46:47AM +0200, Heiko Schocher wrote:
> when using tftp on the smartweb board, it prints, when
> using the tftp command:
>
> Using ethernet at fffc4000 device
> TFTP from server 192.168.1.1; our IP address is 192.168.20.80
> Filename '/tftpboot/smartweb_hw/tbot/u-boot.bin'.
> Load address: 0x21000000
> Loading: ###########################
> 73.2 KiB/s
> done
> Bytes transferred = 391560 (5f988 hex)
> CACHE: Misaligned operation at range [21000000, 2105f988]
> U-Boot#
>
> Fixing this.
>
> Signed-off-by: Heiko Schocher <hs@denx.de>
NAK, we need to sort out:
xtensa: + xtfpga avr32: + atngw100mkii grasshopper atstk1002 atngw100
sparc: + gr_cpci_ax2000 gr_xc3s_1500 gr_ep2s60
microblaze: + microblaze-generic
Lacking a define for CONFIG_SYS_CACHELINE_SIZE first.
--
Tom
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^ permalink raw reply [flat|nested] 6+ messages in thread* [U-Boot] net, cmd: fix misaligned cache operation warning
2016-10-02 12:03 ` [U-Boot] " Tom Rini
@ 2016-10-02 12:06 ` Joe Hershberger
2016-10-04 5:21 ` Heiko Schocher
2016-10-05 23:44 ` Peter.Chubb at data61.csiro.au
0 siblings, 2 replies; 6+ messages in thread
From: Joe Hershberger @ 2016-10-02 12:06 UTC (permalink / raw)
To: u-boot
Hi Tom,
On Sun, Oct 2, 2016 at 7:03 AM, Tom Rini <trini@konsulko.com> wrote:
> On Mon, Aug 29, 2016 at 07:46:47AM +0200, Heiko Schocher wrote:
>
>> when using tftp on the smartweb board, it prints, when
>> using the tftp command:
>>
>> Using ethernet at fffc4000 device
>> TFTP from server 192.168.1.1; our IP address is 192.168.20.80
>> Filename '/tftpboot/smartweb_hw/tbot/u-boot.bin'.
>> Load address: 0x21000000
>> Loading: ###########################
>> 73.2 KiB/s
>> done
>> Bytes transferred = 391560 (5f988 hex)
>> CACHE: Misaligned operation at range [21000000, 2105f988]
>> U-Boot#
>>
>> Fixing this.
>>
>> Signed-off-by: Heiko Schocher <hs@denx.de>
>
> NAK, we need to sort out:
> xtensa: + xtfpga avr32: + atngw100mkii grasshopper atstk1002 atngw100
> sparc: + gr_cpci_ax2000 gr_xc3s_1500 gr_ep2s60
> microblaze: + microblaze-generic
>
> Lacking a define for CONFIG_SYS_CACHELINE_SIZE first.
https://patchwork.ozlabs.org/patch/669691/
...is the approach I prefer to take instead of this patch.
Thanks,
-Joe
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] net, cmd: fix misaligned cache operation warning
2016-10-02 12:06 ` Joe Hershberger
@ 2016-10-04 5:21 ` Heiko Schocher
2016-10-04 12:22 ` Tom Rini
2016-10-05 23:44 ` Peter.Chubb at data61.csiro.au
1 sibling, 1 reply; 6+ messages in thread
From: Heiko Schocher @ 2016-10-04 5:21 UTC (permalink / raw)
To: u-boot
Hello Joe, Tom,
Am 02.10.2016 um 14:06 schrieb Joe Hershberger:
> Hi Tom,
>
> On Sun, Oct 2, 2016 at 7:03 AM, Tom Rini <trini@konsulko.com> wrote:
>> On Mon, Aug 29, 2016 at 07:46:47AM +0200, Heiko Schocher wrote:
>>
>>> when using tftp on the smartweb board, it prints, when
>>> using the tftp command:
>>>
>>> Using ethernet at fffc4000 device
>>> TFTP from server 192.168.1.1; our IP address is 192.168.20.80
>>> Filename '/tftpboot/smartweb_hw/tbot/u-boot.bin'.
>>> Load address: 0x21000000
>>> Loading: ###########################
>>> 73.2 KiB/s
>>> done
>>> Bytes transferred = 391560 (5f988 hex)
>>> CACHE: Misaligned operation at range [21000000, 2105f988]
>>> U-Boot#
>>>
>>> Fixing this.
>>>
>>> Signed-off-by: Heiko Schocher <hs@denx.de>
>>
>> NAK, we need to sort out:
>> xtensa: + xtfpga avr32: + atngw100mkii grasshopper atstk1002 atngw100
>> sparc: + gr_cpci_ax2000 gr_xc3s_1500 gr_ep2s60
>> microblaze: + microblaze-generic
>>
>> Lacking a define for CONFIG_SYS_CACHELINE_SIZE first.
>
> https://patchwork.ozlabs.org/patch/669691/
>
> ...is the approach I prefer to take instead of this patch.
Yep, I already acked this patch, thanks!
bye,
Heiko
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] net, cmd: fix misaligned cache operation warning
2016-10-04 5:21 ` Heiko Schocher
@ 2016-10-04 12:22 ` Tom Rini
0 siblings, 0 replies; 6+ messages in thread
From: Tom Rini @ 2016-10-04 12:22 UTC (permalink / raw)
To: u-boot
On Tue, Oct 04, 2016 at 07:21:08AM +0200, Heiko Schocher wrote:
> Hello Joe, Tom,
>
> Am 02.10.2016 um 14:06 schrieb Joe Hershberger:
> >Hi Tom,
> >
> >On Sun, Oct 2, 2016 at 7:03 AM, Tom Rini <trini@konsulko.com> wrote:
> >>On Mon, Aug 29, 2016 at 07:46:47AM +0200, Heiko Schocher wrote:
> >>
> >>>when using tftp on the smartweb board, it prints, when
> >>>using the tftp command:
> >>>
> >>>Using ethernet at fffc4000 device
> >>>TFTP from server 192.168.1.1; our IP address is 192.168.20.80
> >>>Filename '/tftpboot/smartweb_hw/tbot/u-boot.bin'.
> >>>Load address: 0x21000000
> >>>Loading: ###########################
> >>> 73.2 KiB/s
> >>>done
> >>>Bytes transferred = 391560 (5f988 hex)
> >>>CACHE: Misaligned operation at range [21000000, 2105f988]
> >>>U-Boot#
> >>>
> >>>Fixing this.
> >>>
> >>>Signed-off-by: Heiko Schocher <hs@denx.de>
> >>
> >>NAK, we need to sort out:
> >> xtensa: + xtfpga avr32: + atngw100mkii grasshopper atstk1002 atngw100
> >> sparc: + gr_cpci_ax2000 gr_xc3s_1500 gr_ep2s60
> >>microblaze: + microblaze-generic
> >>
> >>Lacking a define for CONFIG_SYS_CACHELINE_SIZE first.
> >
> >https://patchwork.ozlabs.org/patch/669691/
> >
> >...is the approach I prefer to take instead of this patch.
>
> Yep, I already acked this patch, thanks!
OK. Then please try and either NAK in email, or modify in patchwork so
I don't miss things. Thanks!
--
Tom
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] net, cmd: fix misaligned cache operation warning
2016-10-02 12:06 ` Joe Hershberger
2016-10-04 5:21 ` Heiko Schocher
@ 2016-10-05 23:44 ` Peter.Chubb at data61.csiro.au
1 sibling, 0 replies; 6+ messages in thread
From: Peter.Chubb at data61.csiro.au @ 2016-10-05 23:44 UTC (permalink / raw)
To: u-boot
>>>>> "Joe" == Joe Hershberger <joe.hershberger@gmail.com> writes:
>>
>> Lacking a define for CONFIG_SYS_CACHELINE_SIZE first.
Joe> https://patchwork.ozlabs.org/patch/669691/
Joe> ...is the approach I prefer to take instead of this patch.
Is there anything more I need to do to push this patch?
--
Dr Peter Chubb Tel: +61 2 9490 5852 http://ts.data61.csiro.au/
Trustworthy Systems Group Data61 (formerly NICTA)
^ permalink raw reply [flat|nested] 6+ messages in thread
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2016-08-29 5:46 [U-Boot] [PATCH] net, cmd: fix misaligned cache operation warning Heiko Schocher
2016-10-02 12:03 ` [U-Boot] " Tom Rini
2016-10-02 12:06 ` Joe Hershberger
2016-10-04 5:21 ` Heiko Schocher
2016-10-04 12:22 ` Tom Rini
2016-10-05 23:44 ` Peter.Chubb at data61.csiro.au
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