From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kever Yang Date: Fri, 04 Nov 2016 09:05:06 +0800 Subject: [U-Boot] [PATCH 18/20] rockchip: clk: Support setting ACLK In-Reply-To: <1477946376-29471-19-git-send-email-sjg@chromium.org> References: <1477946376-29471-1-git-send-email-sjg@chromium.org> <1477946376-29471-19-git-send-email-sjg@chromium.org> Message-ID: <581BDEC2.5020300@rock-chips.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Simon, On 11/01/2016 04:39 AM, Simon Glass wrote: > Add basic support for setting the ARM clock, since this allows us to run > at maximum speed in U-Boot. Currently only a single speed is supported > (1.8GHz). > > Signed-off-by: Simon Glass > --- > > drivers/clk/rockchip/clk_rk3288.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c > index ed97e87..d15504c 100644 > --- a/drivers/clk/rockchip/clk_rk3288.c > +++ b/drivers/clk/rockchip/clk_rk3288.c > @@ -691,6 +691,13 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) > > gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); > switch (clk->id) { > + case PLL_APLL: > + /* We only support a fixed rate here */ > + if (rate != 1800000000) > + return -EINVAL; > + rk3288_clk_configure_cpu(priv->cru, priv->grf); > + new_rate = rate; > + break; > case CLK_DDR: > new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate); > break; Reviewed-by: Kever Yang Thanks, - Kever