[U-Boot] [PATCH 0/5] Convert omap24xx-i2c driver to Driver Model

[U-Boot] [PATCH 0/5] Convert omap24xx-i2c driver to Driver Model

[Christophe Ricard]

Hi Simon,

This patchset tries to convert the TI omap24xx_i2c driver to Driver Model.
It has been tested on a TI BeagleBoard xM.

Best Regards
Christophe



Christophe Ricard (5):
  i2c: omap24xx: Convert to DM
  i2c: omap24xx: Fix waitdelay value for I2C HS
  i2c: omap24xx: Remove unused I2C_WAIT macro
  i2c: omap24xx: Fix high speed trimming calculation
  i2c: omap24xx: Convert fully to DM_I2C

 drivers/i2c/Kconfig        |   8 +
 drivers/i2c/omap24xx_i2c.c | 395 ++++++++++++++++++++++++++++++---------------
 drivers/i2c/omap24xx_i2c.h | 154 ------------------
 3 files changed, 276 insertions(+), 281 deletions(-)
 delete mode 100644 drivers/i2c/omap24xx_i2c.h

-- 
2.5.0

[U-Boot] [PATCH 1/5] i2c: omap24xx: Convert to DM

[Christophe Ricard]

Convert omap24xx_i2c driver to DM

Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
---

 drivers/i2c/Kconfig        |   8 ++
 drivers/i2c/omap24xx_i2c.c | 280 +++++++++++++++++++++++++++++++++++++++++++--
 2 files changed, 277 insertions(+), 11 deletions(-)

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 14adda2..3498af1 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -58,6 +58,14 @@ config DM_I2C_GPIO
 	  bindings are supported.
 	  Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
 
+config SYS_I2C_OMAP24XX
+	bool "Texas Instrument OMAP I2C driver"
+	depends on DM_I2C
+	help
+	  Enable support for the I2C interface on the Texas Instruments
+	  OMAP1/2 family of processors. Like OMAP1510/1610/1710/5912 and OMAP242x.
+	  For details see http://www.ti.com/omap.
+
 config SYS_I2C_ROCKCHIP
 	bool "Rockchip I2C driver"
 	depends on DM_I2C
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 79a5c94..f3a4d96 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -36,13 +36,18 @@
  * Copyright (c) 2014 Hannes Schmelzer <oe5hpm@oevsv.at>, B&R
  * - Added support for set_speed
  *
+ * Copyright (c) 2016 Christophe Ricard <christophe.ricard@gmail.com>
+ * - Added support for DM_I2C
+ *
  */
 
 #include <common.h>
 #include <i2c.h>
+#include <dm.h>
 
 #include <asm/arch/i2c.h>
 #include <asm/io.h>
+#include <asm/errno.h>
 
 #include "omap24xx_i2c.h"
 
@@ -53,10 +58,26 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Absolutely safe for status update at 100 kHz I2C: */
 #define I2C_WAIT	200
 
+#ifdef CONFIG_DM_I2C
+struct omap24_i2c_bus {
+	int bus_num;
+	int waitdelay;
+	unsigned clock_frequency;
+	struct i2c *i2c_base;
+};
+#endif
+
+#ifdef CONFIG_SYS_I2C
 static int wait_for_bb(struct i2c_adapter *adap);
 static struct i2c *omap24_get_base(struct i2c_adapter *adap);
 static u16 wait_for_event(struct i2c_adapter *adap);
 static void flush_fifo(struct i2c_adapter *adap);
+#else
+static int wait_for_bb(struct udevice *dev);
+static u16 wait_for_event(struct udevice *dev);
+static void flush_fifo(struct udevice *dev);
+#endif
+
 static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
 {
 	unsigned int sampleclk, prescaler;
@@ -90,13 +111,27 @@ static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
 	}
 	return -1;
 }
+
+#ifdef CONFIG_SYS_I2C
 static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
+#else
+static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
+#endif
 {
-	struct i2c *i2c_base = omap24_get_base(adap);
+	struct i2c *i2c_base;
 	int psc, fsscll = 0, fssclh = 0;
 	int hsscll = 0, hssclh = 0;
 	u32 scll = 0, sclh = 0;
 
+#ifdef CONFIG_SYS_I2C
+	i2c_base = omap24_get_base(adap);
+#else
+	struct omap24_i2c_bus *i2c_bus;
+
+	i2c_bus = dev_get_priv(adap);
+	i2c_base = i2c_bus->i2c_base;
+#endif
+
 	if (speed >= OMAP_I2C_HIGH_SPEED) {
 		/* High speed */
 		psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
@@ -142,8 +177,14 @@ static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
 		}
 	}
 
+#ifdef CONFIG_SYS_I2C
 	adap->speed	= speed;
 	adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
+#else
+	i2c_bus->clock_frequency = speed;
+	i2c_bus->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
+#endif
+
 	writew(0, &i2c_base->con);
 	writew(psc, &i2c_base->psc);
 	writew(scll, &i2c_base->scll);
@@ -154,13 +195,26 @@ static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
 	return 0;
 }
 
+#ifdef CONFIG_SYS_I2C
 static void omap24_i2c_deblock(struct i2c_adapter *adap)
+#else
+static int omap24_i2c_deblock(struct udevice *adap)
+#endif
 {
-	struct i2c *i2c_base = omap24_get_base(adap);
+	struct i2c *i2c_base;
 	int i;
 	u16 systest;
 	u16 orgsystest;
 
+#ifdef CONFIG_SYS_I2C
+	i2c_base = omap24_get_base(adap);
+#else
+	struct omap24_i2c_bus *i2c_bus;
+
+	i2c_bus = dev_get_priv(adap);
+	i2c_base = i2c_bus->i2c_base;
+#endif
+
 	/* set test mode ST_EN = 1 */
 	orgsystest = readw(&i2c_base->systest);
 	systest = orgsystest;
@@ -198,14 +252,31 @@ static void omap24_i2c_deblock(struct i2c_adapter *adap)
 
 	/* restore original mode */
 	writew(orgsystest, &i2c_base->systest);
+
+#ifdef CONFIG_DM_I2C
+	return 0;
+#endif
 }
 
+#ifdef CONFIG_SYS_I2C
 static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+#else
+static void omap24_i2c_init(struct udevice *adap, int speed, int slaveadd)
+#endif
 {
-	struct i2c *i2c_base = omap24_get_base(adap);
+	struct i2c *i2c_base;
 	int timeout = I2C_TIMEOUT;
 	int deblock = 1;
 
+#ifdef CONFIG_SYS_I2C
+	i2c_base = omap24_get_base(adap);
+#else
+	struct omap24_i2c_bus *i2c_bus;
+
+	i2c_bus = dev_get_priv(adap);
+	i2c_base = i2c_bus->i2c_base;
+#endif
+
 retry:
 	if (readw(&i2c_base->con) & I2C_CON_EN) {
 		writew(0, &i2c_base->con);
@@ -253,11 +324,24 @@ retry:
 		}
 }
 
+#ifdef CONFIG_SYS_I2C
 static void flush_fifo(struct i2c_adapter *adap)
+#else
+static void flush_fifo(struct udevice *adap)
+#endif
 {
-	struct i2c *i2c_base = omap24_get_base(adap);
+	struct i2c *i2c_base;
 	u16 stat;
 
+#ifdef CONFIG_SYS_I2C
+	i2c_base = omap24_get_base(adap);
+#else
+	struct omap24_i2c_bus *i2c_bus;
+
+	i2c_bus = dev_get_priv(adap);
+	i2c_base = i2c_bus->i2c_base;
+#endif
+
 	/*
 	 * note: if you try and read data when its not there or ready
 	 * you get a bus error
@@ -277,12 +361,25 @@ static void flush_fifo(struct i2c_adapter *adap)
  * i2c_probe: Use write access. Allows to identify addresses that are
  *            write-only (like the config register of dual-port EEPROMs)
  */
+#ifdef CONFIG_SYS_I2C
 static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
+#else
+static int omap24_i2c_probe(struct udevice *adap, uint chip, uint chip_flags)
+#endif
 {
-	struct i2c *i2c_base = omap24_get_base(adap);
+	struct i2c *i2c_base;
 	u16 status;
 	int res = 1; /* default = fail */
 
+#ifdef CONFIG_SYS_I2C
+	i2c_base = omap24_get_base(adap);
+#else
+	struct omap24_i2c_bus *i2c_bus;
+
+	i2c_bus = dev_get_priv(adap);
+	i2c_base = i2c_bus->i2c_base;
+#endif
+
 	if (chip == readw(&i2c_base->oa))
 		return res;
 
@@ -305,17 +402,26 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
 		 * silent exit is desired upon unconfigured bus, remove the
 		 * following 'if' section:
 		 */
-		if (status == I2C_STAT_XRDY)
+		if (status == I2C_STAT_XRDY) {
+#ifdef CONFIG_SYS_I2C
 			printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
 			       adap->hwadapnr, status);
-
+#else
+			printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
+			       i2c_bus->bus_num, status);
+#endif
+		}
 		goto pr_exit;
 	}
 
 	/* Check for ACK (!NAK) */
 	if (!(status & I2C_STAT_NACK)) {
 		res = 0;				/* Device found */
+#ifdef CONFIG_SYS_I2C
 		udelay(adap->waitdelay);/* Required by AM335X in SPL */
+#else
+		udelay(i2c_bus->waitdelay);
+#endif
 		/* Abort transfer (force idle state) */
 		writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
 		udelay(1000);
@@ -341,13 +447,27 @@ pr_exit:
  *           or that do not need a register address at all (such as some clock
  *           distributors).
  */
+#ifdef CONFIG_SYS_I2C
 static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 			   int alen, uchar *buffer, int len)
+#else
+static int omap24_i2c_read(struct udevice *adap, uchar chip, uint addr,
+			   int alen, uchar *buffer, int len)
+#endif
 {
-	struct i2c *i2c_base = omap24_get_base(adap);
+	struct i2c *i2c_base;
 	int i2c_error = 0;
 	u16 status;
 
+#ifdef CONFIG_SYS_I2C
+	i2c_base = omap24_get_base(adap);
+#else
+	struct omap24_i2c_bus *i2c_bus;
+
+	i2c_bus = dev_get_priv(adap);
+	i2c_base = i2c_bus->i2c_base;
+#endif
+
 	if (alen < 0) {
 		puts("I2C read: addr len < 0\n");
 		return 1;
@@ -397,8 +517,13 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 			/* Try to identify bus that is not padconf'd for I2C */
 			if (status == I2C_STAT_XRDY) {
 				i2c_error = 2;
+#ifdef CONFIG_SYS_I2C
 				printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
 				       adap->hwadapnr, status);
+#else
+				printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
+				       i2c_bus->bus_num, status);
+#endif
 				goto rd_exit;
 			}
 			if (status == 0 || (status & I2C_STAT_NACK)) {
@@ -441,8 +566,13 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 		 */
 		if (status == I2C_STAT_XRDY) {
 			i2c_error = 2;
+#ifdef CONFIG_SYS_I2C
 			printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
 			       adap->hwadapnr, status);
+#else
+			printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
+			       i2c_bus->bus_num, status);
+#endif
 			goto rd_exit;
 		}
 		if (status == 0 || (status & I2C_STAT_NACK)) {
@@ -466,15 +596,29 @@ rd_exit:
 }
 
 /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
+#ifdef CONFIG_SYS_I2C
 static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 			    int alen, uchar *buffer, int len)
+#else
+static int omap24_i2c_write(struct udevice *adap, uchar chip, uint addr,
+			    int alen, uchar *buffer, int len)
+#endif
 {
-	struct i2c *i2c_base = omap24_get_base(adap);
+	struct i2c *i2c_base;
 	int i;
 	u16 status;
 	int i2c_error = 0;
 	int timeout = I2C_TIMEOUT;
 
+#ifdef CONFIG_SYS_I2C
+	i2c_base = omap24_get_base(adap);
+#else
+	struct omap24_i2c_bus *i2c_bus;
+
+	i2c_bus = dev_get_priv(adap);
+	i2c_base = i2c_bus->i2c_base;
+#endif
+
 	if (alen < 0) {
 		puts("I2C write: addr len < 0\n");
 		return 1;
@@ -519,8 +663,13 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 		/* Try to identify bus that is not padconf'd for I2C */
 		if (status == I2C_STAT_XRDY) {
 			i2c_error = 2;
+#ifdef CONFIG_SYS_I2C
 			printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
 			       adap->hwadapnr, status);
+#else
+			printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
+			       i2c_bus->bus_num, status);
+#endif
 			goto wr_exit;
 		}
 		if (status == 0 || (status & I2C_STAT_NACK)) {
@@ -579,12 +728,25 @@ wr_exit:
  * Wait for the bus to be free by checking the Bus Busy (BB)
  * bit to become clear
  */
+#ifdef CONFIG_SYS_I2C
 static int wait_for_bb(struct i2c_adapter *adap)
+#else
+static int wait_for_bb(struct udevice *adap)
+#endif
 {
-	struct i2c *i2c_base = omap24_get_base(adap);
+	struct i2c *i2c_base;
 	int timeout = I2C_TIMEOUT;
 	u16 stat;
 
+#ifdef CONFIG_SYS_I2C
+	i2c_base = omap24_get_base(adap);
+#else
+	struct omap24_i2c_bus *i2c_bus;
+
+	i2c_bus = dev_get_priv(adap);
+	i2c_base = i2c_bus->i2c_base;
+#endif
+
 	writew(0xFFFF, &i2c_base->stat);	/* clear current interrupts...*/
 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
 	while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
@@ -594,7 +756,11 @@ static int wait_for_bb(struct i2c_adapter *adap)
 		I2C_STAT_BB) && timeout--) {
 #endif
 		writew(stat, &i2c_base->stat);
+#ifdef CONFIG_SYS_I2C
 		udelay(adap->waitdelay);
+#else
+		udelay(i2c_bus->waitdelay);
+#endif
 	}
 
 	if (timeout <= 0) {
@@ -610,14 +776,31 @@ static int wait_for_bb(struct i2c_adapter *adap)
  * Wait for the I2C controller to complete current action
  * and update status
  */
+#ifdef CONFIG_SYS_I2C
 static u16 wait_for_event(struct i2c_adapter *adap)
+#else
+static u16 wait_for_event(struct udevice *adap)
+#endif
 {
-	struct i2c *i2c_base = omap24_get_base(adap);
+	struct i2c *i2c_base;
 	u16 status;
 	int timeout = I2C_TIMEOUT;
 
+#ifdef CONFIG_SYS_I2C
+	i2c_base = omap24_get_base(adap);
+#else
+	struct omap24_i2c_bus *i2c_bus;
+
+	i2c_bus = dev_get_priv(adap);
+	i2c_base = i2c_bus->i2c_base;
+#endif
+
 	do {
+#ifdef CONFIG_SYS_I2C
 		udelay(adap->waitdelay);
+#else
+		udelay(i2c_bus->waitdelay);
+#endif
 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
 		status = readw(&i2c_base->stat);
 #else
@@ -636,8 +819,13 @@ static u16 wait_for_event(struct i2c_adapter *adap)
 		 * If status is still 0 here, probably the bus pads have
 		 * not been configured for I2C, and/or pull-ups are missing.
 		 */
+#ifdef CONFIG_SYS_I2C
 		printf("Check if pads/pull-ups of bus %d are properly configured\n",
 		       adap->hwadapnr);
+#else
+		printf("Check if pads/pull-ups of bus %d are properly configured\n",
+		       i2c_bus->bus_num);
+#endif
 		writew(0xFFFF, &i2c_base->stat);
 		status = 0;
 	}
@@ -645,6 +833,7 @@ static u16 wait_for_event(struct i2c_adapter *adap)
 	return status;
 }
 
+#ifdef CONFIG_SYS_I2C
 static struct i2c *omap24_get_base(struct i2c_adapter *adap)
 {
 	switch (adap->hwadapnr) {
@@ -735,3 +924,72 @@ U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
 #endif
 #endif
 #endif
+#endif
+
+#ifdef CONFIG_DM_I2C
+static int omap24_i2c_xfer(struct udevice *adap, struct i2c_msg *msg,
+			   int nmsgs)
+{
+	int ret;
+
+	for (; nmsgs > 0; nmsgs--, msg++) {
+		if (msg->flags & I2C_M_RD) {
+			ret = omap24_i2c_read(adap, msg->addr, 0, 0, msg->buf,
+					      msg->len);
+		} else {
+			ret = omap24_i2c_write(adap, msg->addr, 0, 0, msg->buf,
+					       msg->len);
+		}
+
+		if (ret)
+			return -EREMOTEIO;
+	}
+
+	return 0;
+}
+
+static int omap24_i2c_ofdata_to_platdata(struct udevice *adap)
+{
+	const void *blob = gd->fdt_blob;
+	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
+	int node;
+
+	node = adap->of_offset;
+
+	i2c_bus->clock_frequency = fdtdec_get_int(blob, node,
+						  "clock-frequency", 100000);
+	i2c_bus->i2c_base = (struct i2c *)dev_get_addr(adap);
+	i2c_bus->waitdelay = (10000000 / i2c_bus->clock_frequency) * 2; /* wait for 20 clkperiods */
+
+	i2c_bus->bus_num = adap->seq;
+
+	omap24_i2c_init(adap, i2c_bus->clock_frequency, 1);
+
+	return 0;
+}
+
+static const struct dm_i2c_ops omap24_i2c_ops = {
+	.xfer           = omap24_i2c_xfer,
+	.probe_chip     = omap24_i2c_probe,
+	.set_bus_speed  = omap24_i2c_setspeed,
+	.deblock	= omap24_i2c_deblock,
+};
+
+static const struct udevice_id omap24_i2c_ids[] = {
+	{ .compatible = "ti,omap3-i2c" },
+	{ .compatible = "ti,omap4-i2c" },
+	{ .compatible = "ti,omap2430-i2c" },
+	{ .compatible = "ti,omap2420-i2c" },
+	{ }
+};
+
+U_BOOT_DRIVER(omap_i2c) = {
+	.name   = "omap_i2c",
+	.id     = UCLASS_I2C,
+	.of_match = omap24_i2c_ids,
+	.ofdata_to_platdata = omap24_i2c_ofdata_to_platdata,
+	.per_child_auto_alloc_size = sizeof(struct dm_i2c_chip),
+	.priv_auto_alloc_size = sizeof(struct omap24_i2c_bus),
+	.ops    = &omap24_i2c_ops,
+};
+#endif
-- 
2.5.0

[U-Boot] [PATCH 2/5] i2c: omap24xx: Fix waitdelay value for I2C HS

[Christophe Ricard]

After several testings and experiment, it appears that waitdelay calculation
formula was giving different behavior on the i2c status registers.

Experiment shows waitdelay needs to be extended at least 4 times to get
proper results.

Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
---

 drivers/i2c/omap24xx_i2c.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index f3a4d96..d6e5fe9 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -168,6 +168,13 @@ static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
 		scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
 		sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
 
+#ifdef CONFIG_SYS_I2C
+		adap->speed	= speed;
+		adap->waitdelay = (10000000 / speed) * 8; /* wait for 20 clkperiods */
+#else
+		i2c_bus->clock_frequency = speed;
+		i2c_bus->waitdelay = (10000000 / speed) * 8; /* wait for 20 clkperiods */
+#endif
 	} else {
 		/* Standard and fast speed */
 		psc = omap24_i2c_findpsc(&scll, &sclh, speed);
@@ -175,15 +182,15 @@ static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
 			puts("Error : I2C initializing clock\n");
 			return -1;
 		}
-	}
 
 #ifdef CONFIG_SYS_I2C
-	adap->speed	= speed;
-	adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
+		adap->speed	= speed;
+		adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
 #else
-	i2c_bus->clock_frequency = speed;
-	i2c_bus->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
+		i2c_bus->clock_frequency = speed;
+		i2c_bus->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
 #endif
+	}
 
 	writew(0, &i2c_base->con);
 	writew(psc, &i2c_base->psc);
@@ -467,7 +474,6 @@ static int omap24_i2c_read(struct udevice *adap, uchar chip, uint addr,
 	i2c_bus = dev_get_priv(adap);
 	i2c_base = i2c_bus->i2c_base;
 #endif
-
 	if (alen < 0) {
 		puts("I2C read: addr len < 0\n");
 		return 1;
-- 
2.5.0

[U-Boot] [PATCH 3/5] i2c: omap24xx: Remove unused I2C_WAIT macro

[Christophe Ricard]

I2C_WAIT macro is not used in the code.
200 is bound to a fixed 100000 Hz i2c speed based on an existing formula:
( 10000000 / speed ) * 2 where speed = 100 000.

Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
---

 drivers/i2c/omap24xx_i2c.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index d6e5fe9..48ca446 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -55,9 +55,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define I2C_TIMEOUT	1000
 
-/* Absolutely safe for status update at 100 kHz I2C: */
-#define I2C_WAIT	200
-
 #ifdef CONFIG_DM_I2C
 struct omap24_i2c_bus {
 	int bus_num;
-- 
2.5.0

[U-Boot] [PATCH 4/5] i2c: omap24xx: Fix high speed trimming calculation

[Christophe Ricard]

Work based on i2c-omap.c from linux kernel.

fsscll/fssclh and hsscll/hssclh was always negative in high speed.

i2c high speed frequency start after 400Khz.

Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
---

 drivers/i2c/omap24xx_i2c.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 48ca446..774edaf 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -129,7 +129,9 @@ static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
 	i2c_base = i2c_bus->i2c_base;
 #endif
 
-	if (speed >= OMAP_I2C_HIGH_SPEED) {
+	if (speed > 400000) {
+		unsigned long scl;
+
 		/* High speed */
 		psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
 		psc -= 1;
@@ -139,12 +141,11 @@ static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
 		}
 
 		/* For first phase of HS mode */
-		fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
+		scl = I2C_INTERNAL_SAMPLING_CLK / 400000;
 
-		fssclh = fsscll;
+		fsscll = scl - (scl / 3) - 7;
+		fssclh = (scl / 3)  - 5;
 
-		fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
-		fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
 		if (((fsscll < 0) || (fssclh < 0)) ||
 		    ((fsscll > 255) || (fssclh > 255))) {
 			puts("Error : I2C initializing first phase clock\n");
@@ -152,10 +153,10 @@ static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
 		}
 
 		/* For second phase of HS mode */
-		hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
+		scl = I2C_IP_CLK / speed;
+		hsscll = scl - (scl / 3) - 7;
+		hssclh = (scl / 3) - 5;
 
-		hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
-		hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
 		if (((fsscll < 0) || (fssclh < 0)) ||
 		    ((fsscll > 255) || (fssclh > 255))) {
 			puts("Error : I2C initializing second phase clock\n");
-- 
2.5.0

[U-Boot] [PATCH 5/5] i2c: omap24xx: Convert fully to DM_I2C

[Christophe Ricard]

For several reasons:
- code clarity
- DM trends in u-boot
...

It is better to make omap24xx_i2c driver 100% DM_I2C based.

Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
---

 drivers/i2c/omap24xx_i2c.c | 447 +++++++++++++++++----------------------------
 drivers/i2c/omap24xx_i2c.h | 154 ----------------
 2 files changed, 163 insertions(+), 438 deletions(-)
 delete mode 100644 drivers/i2c/omap24xx_i2c.h

diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 774edaf..baccb89 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -49,31 +49,164 @@
 #include <asm/io.h>
 #include <asm/errno.h>
 
-#include "omap24xx_i2c.h"
-
 DECLARE_GLOBAL_DATA_PTR;
 
+/* I2C masks */
+
+/* I2C Interrupt Enable Register (I2C_IE): */
+#define I2C_IE_GC_IE	(1 << 5)
+#define I2C_IE_XRDY_IE	(1 << 4) /* Transmit data ready interrupt enable */
+#define I2C_IE_RRDY_IE	(1 << 3) /* Receive data ready interrupt enable */
+#define I2C_IE_ARDY_IE	(1 << 2) /* Register access ready interrupt enable */
+#define I2C_IE_NACK_IE	(1 << 1) /* No acknowledgment interrupt enable */
+#define I2C_IE_AL_IE	(1 << 0) /* Arbitration lost interrupt enable */
+
+/* I2C Status Register (I2C_STAT): */
+
+#define I2C_STAT_SBD	(1 << 15) /* Single byte data */
+#define I2C_STAT_BB	(1 << 12) /* Bus busy */
+#define I2C_STAT_ROVR	(1 << 11) /* Receive overrun */
+#define I2C_STAT_XUDF	(1 << 10) /* Transmit underflow */
+#define I2C_STAT_AAS	(1 << 9)  /* Address as slave */
+#define I2C_STAT_GC	(1 << 5)
+#define I2C_STAT_XRDY	(1 << 4)  /* Transmit data ready */
+#define I2C_STAT_RRDY	(1 << 3)  /* Receive data ready */
+#define I2C_STAT_ARDY	(1 << 2)  /* Register access ready */
+#define I2C_STAT_NACK	(1 << 1)  /* No acknowledgment interrupt enable */
+#define I2C_STAT_AL	(1 << 0)  /* Arbitration lost interrupt enable */
+
+/* I2C Interrupt Code Register (I2C_INTCODE): */
+
+#define I2C_INTCODE_MASK	7
+#define I2C_INTCODE_NONE	0
+#define I2C_INTCODE_AL		1	/* Arbitration lost */
+#define I2C_INTCODE_NAK		2	/* No acknowledgement/general call */
+#define I2C_INTCODE_ARDY	3	/* Register access ready */
+#define I2C_INTCODE_RRDY	4	/* Rcv data ready */
+#define I2C_INTCODE_XRDY	5	/* Xmit data ready */
+
+/* I2C Buffer Configuration Register (I2C_BUF): */
+
+#define I2C_BUF_RDMA_EN		(1 << 15) /* Receive DMA channel enable */
+#define I2C_BUF_XDMA_EN		(1 << 7)  /* Transmit DMA channel enable */
+
+/* I2C Configuration Register (I2C_CON): */
+
+#define I2C_CON_EN	(1 << 15)  /* I2C module enable */
+#define I2C_CON_BE	(1 << 14)  /* Big endian mode */
+#define I2C_CON_STB	(1 << 11)  /* Start byte mode (master mode only) */
+#define I2C_CON_MST	(1 << 10)  /* Master/slave mode */
+#define I2C_CON_TRX	(1 << 9)   /* Transmitter/receiver mode */
+				   /* (master mode only) */
+#define I2C_CON_XA	(1 << 8)   /* Expand address */
+#define I2C_CON_STP	(1 << 1)   /* Stop condition (master mode only) */
+#define I2C_CON_STT	(1 << 0)   /* Start condition (master mode only) */
+
+/* I2C System Test Register (I2C_SYSTEST): */
+
+#define I2C_SYSTEST_ST_EN	(1 << 15) /* System test enable */
+#define I2C_SYSTEST_FREE	(1 << 14) /* Free running mode, on brkpoint) */
+#define I2C_SYSTEST_TMODE_MASK	(3 << 12) /* Test mode select */
+#define I2C_SYSTEST_TMODE_SHIFT	(12)	  /* Test mode select */
+#define I2C_SYSTEST_SCL_I	(1 << 3)  /* SCL line sense input value */
+#define I2C_SYSTEST_SCL_O	(1 << 2)  /* SCL line drive output value */
+#define I2C_SYSTEST_SDA_I	(1 << 1)  /* SDA line sense input value */
+#define I2C_SYSTEST_SDA_O	(1 << 0)  /* SDA line drive output value */
+
+/* I2C System Status Register (I2C_SYSS): */
+
+#define I2C_SYSS_RDONE          (1 << 0)  /* Internel reset monitoring */
+
+#define I2C_SCLL_SCLL		0
+#define I2C_SCLL_SCLL_M		0xFF
+#define I2C_SCLL_HSSCLL		8
+#define I2C_SCLH_HSSCLL_M	0xFF
+#define I2C_SCLH_SCLH		0
+#define I2C_SCLH_SCLH_M		0xFF
+#define I2C_SCLH_HSSCLH		8
+#define I2C_SCLH_HSSCLH_M	0xFF
+
+#define OMAP_I2C_STANDARD	100000
+#define OMAP_I2C_FAST_MODE	400000
+#define OMAP_I2C_HIGH_SPEED	3400000
+
+#define SYSTEM_CLOCK_12		12000000
+#define SYSTEM_CLOCK_13		13000000
+#define SYSTEM_CLOCK_192	19200000
+#define SYSTEM_CLOCK_96		96000000
+
+/* Use the reference value of 96MHz if not explicitly set by the board */
+#ifndef I2C_IP_CLK
+#define I2C_IP_CLK		SYSTEM_CLOCK_96
+#endif
+
+/*
+ * The reference minimum clock for high speed is 19.2MHz.
+ * The linux 2.6.30 kernel uses this value.
+ * The reference minimum clock for fast mode is 9.6MHz
+ * The reference minimum clock for standard mode is 4MHz
+ * In TRM, the value of 12MHz is used.
+ */
+#ifndef I2C_INTERNAL_SAMPLING_CLK
+#define I2C_INTERNAL_SAMPLING_CLK	19200000
+#endif
+
+/*
+ * The equation for the low and high time is
+ * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
+ * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
+ *
+ * If the duty cycle is 50%
+ *
+ * tlow = scll + scll_trim = sampling clock / (2 * speed)
+ * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
+ *
+ * In TRM
+ * scll_trim = 7
+ * sclh_trim = 5
+ *
+ * The linux 2.6.30 kernel uses
+ * scll_trim = 6
+ * sclh_trim = 6
+ *
+ * These are the trim values for standard and fast speed
+ */
+#ifndef I2C_FASTSPEED_SCLL_TRIM
+#define I2C_FASTSPEED_SCLL_TRIM		6
+#endif
+#ifndef I2C_FASTSPEED_SCLH_TRIM
+#define I2C_FASTSPEED_SCLH_TRIM		6
+#endif
+
+/* These are the trim values for high speed */
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM	I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM	I2C_FASTSPEED_SCLH_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM	I2C_FASTSPEED_SCLL_TRIM
+#endif
+#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
+#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM	I2C_FASTSPEED_SCLH_TRIM
+#endif
+
+#define I2C_PSC_MAX		0x0f
+#define I2C_PSC_MIN		0x00
+
 #define I2C_TIMEOUT	1000
 
-#ifdef CONFIG_DM_I2C
 struct omap24_i2c_bus {
 	int bus_num;
 	int waitdelay;
 	unsigned clock_frequency;
 	struct i2c *i2c_base;
 };
-#endif
 
-#ifdef CONFIG_SYS_I2C
-static int wait_for_bb(struct i2c_adapter *adap);
-static struct i2c *omap24_get_base(struct i2c_adapter *adap);
-static u16 wait_for_event(struct i2c_adapter *adap);
-static void flush_fifo(struct i2c_adapter *adap);
-#else
 static int wait_for_bb(struct udevice *dev);
 static u16 wait_for_event(struct udevice *dev);
 static void flush_fifo(struct udevice *dev);
-#endif
 
 static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
 {
@@ -109,26 +242,14 @@ static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
 	return -1;
 }
 
-#ifdef CONFIG_SYS_I2C
-static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
-#else
 static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
-#endif
 {
-	struct i2c *i2c_base;
+	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
+	struct i2c *i2c_base = i2c_bus->i2c_base;
 	int psc, fsscll = 0, fssclh = 0;
 	int hsscll = 0, hssclh = 0;
 	u32 scll = 0, sclh = 0;
 
-#ifdef CONFIG_SYS_I2C
-	i2c_base = omap24_get_base(adap);
-#else
-	struct omap24_i2c_bus *i2c_bus;
-
-	i2c_bus = dev_get_priv(adap);
-	i2c_base = i2c_bus->i2c_base;
-#endif
-
 	if (speed > 400000) {
 		unsigned long scl;
 
@@ -166,13 +287,8 @@ static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
 		scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
 		sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
 
-#ifdef CONFIG_SYS_I2C
-		adap->speed	= speed;
-		adap->waitdelay = (10000000 / speed) * 8; /* wait for 20 clkperiods */
-#else
 		i2c_bus->clock_frequency = speed;
 		i2c_bus->waitdelay = (10000000 / speed) * 8; /* wait for 20 clkperiods */
-#endif
 	} else {
 		/* Standard and fast speed */
 		psc = omap24_i2c_findpsc(&scll, &sclh, speed);
@@ -181,13 +297,8 @@ static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
 			return -1;
 		}
 
-#ifdef CONFIG_SYS_I2C
-		adap->speed	= speed;
-		adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
-#else
 		i2c_bus->clock_frequency = speed;
 		i2c_bus->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
-#endif
 	}
 
 	writew(0, &i2c_base->con);
@@ -200,26 +311,14 @@ static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
 	return 0;
 }
 
-#ifdef CONFIG_SYS_I2C
-static void omap24_i2c_deblock(struct i2c_adapter *adap)
-#else
 static int omap24_i2c_deblock(struct udevice *adap)
-#endif
 {
-	struct i2c *i2c_base;
+	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
+	struct i2c *i2c_base = i2c_bus->i2c_base;
 	int i;
 	u16 systest;
 	u16 orgsystest;
 
-#ifdef CONFIG_SYS_I2C
-	i2c_base = omap24_get_base(adap);
-#else
-	struct omap24_i2c_bus *i2c_bus;
-
-	i2c_bus = dev_get_priv(adap);
-	i2c_base = i2c_bus->i2c_base;
-#endif
-
 	/* set test mode ST_EN = 1 */
 	orgsystest = readw(&i2c_base->systest);
 	systest = orgsystest;
@@ -258,30 +357,16 @@ static int omap24_i2c_deblock(struct udevice *adap)
 	/* restore original mode */
 	writew(orgsystest, &i2c_base->systest);
 
-#ifdef CONFIG_DM_I2C
 	return 0;
-#endif
 }
 
-#ifdef CONFIG_SYS_I2C
-static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
-#else
 static void omap24_i2c_init(struct udevice *adap, int speed, int slaveadd)
-#endif
 {
-	struct i2c *i2c_base;
+	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
+	struct i2c *i2c_base = i2c_bus->i2c_base;
 	int timeout = I2C_TIMEOUT;
 	int deblock = 1;
 
-#ifdef CONFIG_SYS_I2C
-	i2c_base = omap24_get_base(adap);
-#else
-	struct omap24_i2c_bus *i2c_bus;
-
-	i2c_bus = dev_get_priv(adap);
-	i2c_base = i2c_bus->i2c_base;
-#endif
-
 retry:
 	if (readw(&i2c_base->con) & I2C_CON_EN) {
 		writew(0, &i2c_base->con);
@@ -329,24 +414,12 @@ retry:
 		}
 }
 
-#ifdef CONFIG_SYS_I2C
-static void flush_fifo(struct i2c_adapter *adap)
-#else
 static void flush_fifo(struct udevice *adap)
-#endif
 {
-	struct i2c *i2c_base;
+	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
+	struct i2c *i2c_base = i2c_bus->i2c_base;
 	u16 stat;
 
-#ifdef CONFIG_SYS_I2C
-	i2c_base = omap24_get_base(adap);
-#else
-	struct omap24_i2c_bus *i2c_bus;
-
-	i2c_bus = dev_get_priv(adap);
-	i2c_base = i2c_bus->i2c_base;
-#endif
-
 	/*
 	 * note: if you try and read data when its not there or ready
 	 * you get a bus error
@@ -366,25 +439,13 @@ static void flush_fifo(struct udevice *adap)
  * i2c_probe: Use write access. Allows to identify addresses that are
  *            write-only (like the config register of dual-port EEPROMs)
  */
-#ifdef CONFIG_SYS_I2C
-static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
-#else
 static int omap24_i2c_probe(struct udevice *adap, uint chip, uint chip_flags)
-#endif
 {
-	struct i2c *i2c_base;
+	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
+	struct i2c *i2c_base = i2c_bus->i2c_base;
 	u16 status;
 	int res = 1; /* default = fail */
 
-#ifdef CONFIG_SYS_I2C
-	i2c_base = omap24_get_base(adap);
-#else
-	struct omap24_i2c_bus *i2c_bus;
-
-	i2c_bus = dev_get_priv(adap);
-	i2c_base = i2c_bus->i2c_base;
-#endif
-
 	if (chip == readw(&i2c_base->oa))
 		return res;
 
@@ -407,26 +468,16 @@ static int omap24_i2c_probe(struct udevice *adap, uint chip, uint chip_flags)
 		 * silent exit is desired upon unconfigured bus, remove the
 		 * following 'if' section:
 		 */
-		if (status == I2C_STAT_XRDY) {
-#ifdef CONFIG_SYS_I2C
-			printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
-			       adap->hwadapnr, status);
-#else
+		if (status == I2C_STAT_XRDY)
 			printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
 			       i2c_bus->bus_num, status);
-#endif
-		}
 		goto pr_exit;
 	}
 
 	/* Check for ACK (!NAK) */
 	if (!(status & I2C_STAT_NACK)) {
 		res = 0;				/* Device found */
-#ifdef CONFIG_SYS_I2C
-		udelay(adap->waitdelay);/* Required by AM335X in SPL */
-#else
 		udelay(i2c_bus->waitdelay);
-#endif
 		/* Abort transfer (force idle state) */
 		writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
 		udelay(1000);
@@ -452,26 +503,14 @@ pr_exit:
  *           or that do not need a register address at all (such as some clock
  *           distributors).
  */
-#ifdef CONFIG_SYS_I2C
-static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
-			   int alen, uchar *buffer, int len)
-#else
 static int omap24_i2c_read(struct udevice *adap, uchar chip, uint addr,
 			   int alen, uchar *buffer, int len)
-#endif
 {
-	struct i2c *i2c_base;
+	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
+	struct i2c *i2c_base = i2c_bus->i2c_base;
 	int i2c_error = 0;
 	u16 status;
 
-#ifdef CONFIG_SYS_I2C
-	i2c_base = omap24_get_base(adap);
-#else
-	struct omap24_i2c_bus *i2c_bus;
-
-	i2c_bus = dev_get_priv(adap);
-	i2c_base = i2c_bus->i2c_base;
-#endif
 	if (alen < 0) {
 		puts("I2C read: addr len < 0\n");
 		return 1;
@@ -521,13 +560,8 @@ static int omap24_i2c_read(struct udevice *adap, uchar chip, uint addr,
 			/* Try to identify bus that is not padconf'd for I2C */
 			if (status == I2C_STAT_XRDY) {
 				i2c_error = 2;
-#ifdef CONFIG_SYS_I2C
-				printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
-				       adap->hwadapnr, status);
-#else
 				printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
 				       i2c_bus->bus_num, status);
-#endif
 				goto rd_exit;
 			}
 			if (status == 0 || (status & I2C_STAT_NACK)) {
@@ -570,13 +604,8 @@ static int omap24_i2c_read(struct udevice *adap, uchar chip, uint addr,
 		 */
 		if (status == I2C_STAT_XRDY) {
 			i2c_error = 2;
-#ifdef CONFIG_SYS_I2C
-			printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
-			       adap->hwadapnr, status);
-#else
 			printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
 			       i2c_bus->bus_num, status);
-#endif
 			goto rd_exit;
 		}
 		if (status == 0 || (status & I2C_STAT_NACK)) {
@@ -600,29 +629,16 @@ rd_exit:
 }
 
 /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
-#ifdef CONFIG_SYS_I2C
-static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
-			    int alen, uchar *buffer, int len)
-#else
 static int omap24_i2c_write(struct udevice *adap, uchar chip, uint addr,
 			    int alen, uchar *buffer, int len)
-#endif
 {
-	struct i2c *i2c_base;
+	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
+	struct i2c *i2c_base = i2c_bus->i2c_base;
 	int i;
 	u16 status;
 	int i2c_error = 0;
 	int timeout = I2C_TIMEOUT;
 
-#ifdef CONFIG_SYS_I2C
-	i2c_base = omap24_get_base(adap);
-#else
-	struct omap24_i2c_bus *i2c_bus;
-
-	i2c_bus = dev_get_priv(adap);
-	i2c_base = i2c_bus->i2c_base;
-#endif
-
 	if (alen < 0) {
 		puts("I2C write: addr len < 0\n");
 		return 1;
@@ -667,13 +683,8 @@ static int omap24_i2c_write(struct udevice *adap, uchar chip, uint addr,
 		/* Try to identify bus that is not padconf'd for I2C */
 		if (status == I2C_STAT_XRDY) {
 			i2c_error = 2;
-#ifdef CONFIG_SYS_I2C
-			printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
-			       adap->hwadapnr, status);
-#else
 			printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
 			       i2c_bus->bus_num, status);
-#endif
 			goto wr_exit;
 		}
 		if (status == 0 || (status & I2C_STAT_NACK)) {
@@ -732,25 +743,13 @@ wr_exit:
  * Wait for the bus to be free by checking the Bus Busy (BB)
  * bit to become clear
  */
-#ifdef CONFIG_SYS_I2C
-static int wait_for_bb(struct i2c_adapter *adap)
-#else
 static int wait_for_bb(struct udevice *adap)
-#endif
 {
-	struct i2c *i2c_base;
+	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
+	struct i2c *i2c_base = i2c_bus->i2c_base;
 	int timeout = I2C_TIMEOUT;
 	u16 stat;
 
-#ifdef CONFIG_SYS_I2C
-	i2c_base = omap24_get_base(adap);
-#else
-	struct omap24_i2c_bus *i2c_bus;
-
-	i2c_bus = dev_get_priv(adap);
-	i2c_base = i2c_bus->i2c_base;
-#endif
-
 	writew(0xFFFF, &i2c_base->stat);	/* clear current interrupts...*/
 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
 	while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
@@ -760,11 +759,7 @@ static int wait_for_bb(struct udevice *adap)
 		I2C_STAT_BB) && timeout--) {
 #endif
 		writew(stat, &i2c_base->stat);
-#ifdef CONFIG_SYS_I2C
-		udelay(adap->waitdelay);
-#else
 		udelay(i2c_bus->waitdelay);
-#endif
 	}
 
 	if (timeout <= 0) {
@@ -780,31 +775,15 @@ static int wait_for_bb(struct udevice *adap)
  * Wait for the I2C controller to complete current action
  * and update status
  */
-#ifdef CONFIG_SYS_I2C
-static u16 wait_for_event(struct i2c_adapter *adap)
-#else
 static u16 wait_for_event(struct udevice *adap)
-#endif
 {
-	struct i2c *i2c_base;
+	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
+	struct i2c *i2c_base = i2c_bus->i2c_base;
 	u16 status;
 	int timeout = I2C_TIMEOUT;
 
-#ifdef CONFIG_SYS_I2C
-	i2c_base = omap24_get_base(adap);
-#else
-	struct omap24_i2c_bus *i2c_bus;
-
-	i2c_bus = dev_get_priv(adap);
-	i2c_base = i2c_bus->i2c_base;
-#endif
-
 	do {
-#ifdef CONFIG_SYS_I2C
-		udelay(adap->waitdelay);
-#else
 		udelay(i2c_bus->waitdelay);
-#endif
 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
 		status = readw(&i2c_base->stat);
 #else
@@ -823,13 +802,8 @@ static u16 wait_for_event(struct udevice *adap)
 		 * If status is still 0 here, probably the bus pads have
 		 * not been configured for I2C, and/or pull-ups are missing.
 		 */
-#ifdef CONFIG_SYS_I2C
-		printf("Check if pads/pull-ups of bus %d are properly configured\n",
-		       adap->hwadapnr);
-#else
 		printf("Check if pads/pull-ups of bus %d are properly configured\n",
 		       i2c_bus->bus_num);
-#endif
 		writew(0xFFFF, &i2c_base->stat);
 		status = 0;
 	}
@@ -837,100 +811,6 @@ static u16 wait_for_event(struct udevice *adap)
 	return status;
 }
 
-#ifdef CONFIG_SYS_I2C
-static struct i2c *omap24_get_base(struct i2c_adapter *adap)
-{
-	switch (adap->hwadapnr) {
-	case 0:
-		return (struct i2c *)I2C_BASE1;
-		break;
-	case 1:
-		return (struct i2c *)I2C_BASE2;
-		break;
-#if (I2C_BUS_MAX > 2)
-	case 2:
-		return (struct i2c *)I2C_BASE3;
-		break;
-#if (I2C_BUS_MAX > 3)
-	case 3:
-		return (struct i2c *)I2C_BASE4;
-		break;
-#if (I2C_BUS_MAX > 4)
-	case 4:
-		return (struct i2c *)I2C_BASE5;
-		break;
-#endif
-#endif
-#endif
-	default:
-		printf("wrong hwadapnr: %d\n", adap->hwadapnr);
-		break;
-	}
-	return NULL;
-}
-
-#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
-#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
-#endif
-#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
-#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
-#endif
-
-U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
-			 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
-			 CONFIG_SYS_OMAP24_I2C_SPEED,
-			 CONFIG_SYS_OMAP24_I2C_SLAVE,
-			 0)
-U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
-			 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
-			 CONFIG_SYS_OMAP24_I2C_SPEED1,
-			 CONFIG_SYS_OMAP24_I2C_SLAVE1,
-			 1)
-#if (I2C_BUS_MAX > 2)
-#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
-#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
-#endif
-#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
-#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
-#endif
-
-U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
-			 omap24_i2c_read, omap24_i2c_write, NULL,
-			 CONFIG_SYS_OMAP24_I2C_SPEED2,
-			 CONFIG_SYS_OMAP24_I2C_SLAVE2,
-			 2)
-#if (I2C_BUS_MAX > 3)
-#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
-#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
-#endif
-#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
-#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
-#endif
-
-U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
-			 omap24_i2c_read, omap24_i2c_write, NULL,
-			 CONFIG_SYS_OMAP24_I2C_SPEED3,
-			 CONFIG_SYS_OMAP24_I2C_SLAVE3,
-			 3)
-#if (I2C_BUS_MAX > 4)
-#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
-#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
-#endif
-#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
-#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
-#endif
-
-U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
-			 omap24_i2c_read, omap24_i2c_write, NULL,
-			 CONFIG_SYS_OMAP24_I2C_SPEED4,
-			 CONFIG_SYS_OMAP24_I2C_SLAVE4,
-			 4)
-#endif
-#endif
-#endif
-#endif
-
-#ifdef CONFIG_DM_I2C
 static int omap24_i2c_xfer(struct udevice *adap, struct i2c_msg *msg,
 			   int nmsgs)
 {
@@ -996,4 +876,3 @@ U_BOOT_DRIVER(omap_i2c) = {
 	.priv_auto_alloc_size = sizeof(struct omap24_i2c_bus),
 	.ops    = &omap24_i2c_ops,
 };
-#endif
diff --git a/drivers/i2c/omap24xx_i2c.h b/drivers/i2c/omap24xx_i2c.h
deleted file mode 100644
index 3dae295..0000000
--- a/drivers/i2c/omap24xx_i2c.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * (C) Copyright 2004-2010
- * Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _OMAP2PLUS_I2C_H_
-#define _OMAP2PLUS_I2C_H_
-
-/* I2C masks */
-
-/* I2C Interrupt Enable Register (I2C_IE): */
-#define I2C_IE_GC_IE	(1 << 5)
-#define I2C_IE_XRDY_IE	(1 << 4) /* Transmit data ready interrupt enable */
-#define I2C_IE_RRDY_IE	(1 << 3) /* Receive data ready interrupt enable */
-#define I2C_IE_ARDY_IE	(1 << 2) /* Register access ready interrupt enable */
-#define I2C_IE_NACK_IE	(1 << 1) /* No acknowledgment interrupt enable */
-#define I2C_IE_AL_IE	(1 << 0) /* Arbitration lost interrupt enable */
-
-/* I2C Status Register (I2C_STAT): */
-
-#define I2C_STAT_SBD	(1 << 15) /* Single byte data */
-#define I2C_STAT_BB	(1 << 12) /* Bus busy */
-#define I2C_STAT_ROVR	(1 << 11) /* Receive overrun */
-#define I2C_STAT_XUDF	(1 << 10) /* Transmit underflow */
-#define I2C_STAT_AAS	(1 << 9)  /* Address as slave */
-#define I2C_STAT_GC	(1 << 5)
-#define I2C_STAT_XRDY	(1 << 4)  /* Transmit data ready */
-#define I2C_STAT_RRDY	(1 << 3)  /* Receive data ready */
-#define I2C_STAT_ARDY	(1 << 2)  /* Register access ready */
-#define I2C_STAT_NACK	(1 << 1)  /* No acknowledgment interrupt enable */
-#define I2C_STAT_AL	(1 << 0)  /* Arbitration lost interrupt enable */
-
-/* I2C Interrupt Code Register (I2C_INTCODE): */
-
-#define I2C_INTCODE_MASK	7
-#define I2C_INTCODE_NONE	0
-#define I2C_INTCODE_AL		1	/* Arbitration lost */
-#define I2C_INTCODE_NAK		2	/* No acknowledgement/general call */
-#define I2C_INTCODE_ARDY	3	/* Register access ready */
-#define I2C_INTCODE_RRDY	4	/* Rcv data ready */
-#define I2C_INTCODE_XRDY	5	/* Xmit data ready */
-
-/* I2C Buffer Configuration Register (I2C_BUF): */
-
-#define I2C_BUF_RDMA_EN		(1 << 15) /* Receive DMA channel enable */
-#define I2C_BUF_XDMA_EN		(1 << 7)  /* Transmit DMA channel enable */
-
-/* I2C Configuration Register (I2C_CON): */
-
-#define I2C_CON_EN	(1 << 15)  /* I2C module enable */
-#define I2C_CON_BE	(1 << 14)  /* Big endian mode */
-#define I2C_CON_STB	(1 << 11)  /* Start byte mode (master mode only) */
-#define I2C_CON_MST	(1 << 10)  /* Master/slave mode */
-#define I2C_CON_TRX	(1 << 9)   /* Transmitter/receiver mode */
-				   /* (master mode only) */
-#define I2C_CON_XA	(1 << 8)   /* Expand address */
-#define I2C_CON_STP	(1 << 1)   /* Stop condition (master mode only) */
-#define I2C_CON_STT	(1 << 0)   /* Start condition (master mode only) */
-
-/* I2C System Test Register (I2C_SYSTEST): */
-
-#define I2C_SYSTEST_ST_EN	(1 << 15) /* System test enable */
-#define I2C_SYSTEST_FREE	(1 << 14) /* Free running mode, on brkpoint) */
-#define I2C_SYSTEST_TMODE_MASK	(3 << 12) /* Test mode select */
-#define I2C_SYSTEST_TMODE_SHIFT	(12)	  /* Test mode select */
-#define I2C_SYSTEST_SCL_I	(1 << 3)  /* SCL line sense input value */
-#define I2C_SYSTEST_SCL_O	(1 << 2)  /* SCL line drive output value */
-#define I2C_SYSTEST_SDA_I	(1 << 1)  /* SDA line sense input value */
-#define I2C_SYSTEST_SDA_O	(1 << 0)  /* SDA line drive output value */
-
-/* I2C System Status Register (I2C_SYSS): */
-
-#define I2C_SYSS_RDONE          (1 << 0)  /* Internel reset monitoring */
-
-#define I2C_SCLL_SCLL		0
-#define I2C_SCLL_SCLL_M		0xFF
-#define I2C_SCLL_HSSCLL		8
-#define I2C_SCLH_HSSCLL_M	0xFF
-#define I2C_SCLH_SCLH		0
-#define I2C_SCLH_SCLH_M		0xFF
-#define I2C_SCLH_HSSCLH		8
-#define I2C_SCLH_HSSCLH_M	0xFF
-
-#define OMAP_I2C_STANDARD	100000
-#define OMAP_I2C_FAST_MODE	400000
-#define OMAP_I2C_HIGH_SPEED	3400000
-
-#define SYSTEM_CLOCK_12		12000000
-#define SYSTEM_CLOCK_13		13000000
-#define SYSTEM_CLOCK_192	19200000
-#define SYSTEM_CLOCK_96		96000000
-
-/* Use the reference value of 96MHz if not explicitly set by the board */
-#ifndef I2C_IP_CLK
-#define I2C_IP_CLK		SYSTEM_CLOCK_96
-#endif
-
-/*
- * The reference minimum clock for high speed is 19.2MHz.
- * The linux 2.6.30 kernel uses this value.
- * The reference minimum clock for fast mode is 9.6MHz
- * The reference minimum clock for standard mode is 4MHz
- * In TRM, the value of 12MHz is used.
- */
-#ifndef I2C_INTERNAL_SAMPLING_CLK
-#define I2C_INTERNAL_SAMPLING_CLK	19200000
-#endif
-
-/*
- * The equation for the low and high time is
- * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
- * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
- *
- * If the duty cycle is 50%
- *
- * tlow = scll + scll_trim = sampling clock / (2 * speed)
- * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
- *
- * In TRM
- * scll_trim = 7
- * sclh_trim = 5
- *
- * The linux 2.6.30 kernel uses
- * scll_trim = 6
- * sclh_trim = 6
- *
- * These are the trim values for standard and fast speed
- */
-#ifndef I2C_FASTSPEED_SCLL_TRIM
-#define I2C_FASTSPEED_SCLL_TRIM		6
-#endif
-#ifndef I2C_FASTSPEED_SCLH_TRIM
-#define I2C_FASTSPEED_SCLH_TRIM		6
-#endif
-
-/* These are the trim values for high speed */
-#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
-#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM	I2C_FASTSPEED_SCLL_TRIM
-#endif
-#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
-#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM	I2C_FASTSPEED_SCLH_TRIM
-#endif
-#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
-#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM	I2C_FASTSPEED_SCLL_TRIM
-#endif
-#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
-#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM	I2C_FASTSPEED_SCLH_TRIM
-#endif
-
-#define I2C_PSC_MAX		0x0f
-#define I2C_PSC_MIN		0x00
-
-#endif /* _OMAP24XX_I2C_H_ */
-- 
2.5.0

[U-Boot] [PATCH 1/5] i2c: omap24xx: Convert to DM

[Heiko Schocher]

Hello Christophe,

Am 17.01.2016 um 12:09 schrieb Christophe Ricard:
> Convert omap24xx_i2c driver to DM
>
> Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
> ---
>
>   drivers/i2c/Kconfig        |   8 ++
>   drivers/i2c/omap24xx_i2c.c | 280 +++++++++++++++++++++++++++++++++++++++++++--
>   2 files changed, 277 insertions(+), 11 deletions(-)

Looks good to me, Thanks!

Acked-by: Heiko Schocher <hs@denx.de>

bye,
Heiko
>
> diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
> index 14adda2..3498af1 100644
> --- a/drivers/i2c/Kconfig
> +++ b/drivers/i2c/Kconfig
> @@ -58,6 +58,14 @@ config DM_I2C_GPIO
>   	  bindings are supported.
>   	  Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
>
> +config SYS_I2C_OMAP24XX
> +	bool "Texas Instrument OMAP I2C driver"
> +	depends on DM_I2C
> +	help
> +	  Enable support for the I2C interface on the Texas Instruments
> +	  OMAP1/2 family of processors. Like OMAP1510/1610/1710/5912 and OMAP242x.
> +	  For details see http://www.ti.com/omap.
> +
>   config SYS_I2C_ROCKCHIP
>   	bool "Rockchip I2C driver"
>   	depends on DM_I2C
> diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
> index 79a5c94..f3a4d96 100644
> --- a/drivers/i2c/omap24xx_i2c.c
> +++ b/drivers/i2c/omap24xx_i2c.c
> @@ -36,13 +36,18 @@
>    * Copyright (c) 2014 Hannes Schmelzer <oe5hpm@oevsv.at>, B&R
>    * - Added support for set_speed
>    *
> + * Copyright (c) 2016 Christophe Ricard <christophe.ricard@gmail.com>
> + * - Added support for DM_I2C
> + *
>    */
>
>   #include <common.h>
>   #include <i2c.h>
> +#include <dm.h>
>
>   #include <asm/arch/i2c.h>
>   #include <asm/io.h>
> +#include <asm/errno.h>
>
>   #include "omap24xx_i2c.h"
>
> @@ -53,10 +58,26 @@ DECLARE_GLOBAL_DATA_PTR;
>   /* Absolutely safe for status update at 100 kHz I2C: */
>   #define I2C_WAIT	200
>
> +#ifdef CONFIG_DM_I2C
> +struct omap24_i2c_bus {
> +	int bus_num;
> +	int waitdelay;
> +	unsigned clock_frequency;
> +	struct i2c *i2c_base;
> +};
> +#endif
> +
> +#ifdef CONFIG_SYS_I2C
>   static int wait_for_bb(struct i2c_adapter *adap);
>   static struct i2c *omap24_get_base(struct i2c_adapter *adap);
>   static u16 wait_for_event(struct i2c_adapter *adap);
>   static void flush_fifo(struct i2c_adapter *adap);
> +#else
> +static int wait_for_bb(struct udevice *dev);
> +static u16 wait_for_event(struct udevice *dev);
> +static void flush_fifo(struct udevice *dev);
> +#endif
> +
>   static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
>   {
>   	unsigned int sampleclk, prescaler;
> @@ -90,13 +111,27 @@ static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
>   	}
>   	return -1;
>   }
> +
> +#ifdef CONFIG_SYS_I2C
>   static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
> +#else
> +static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
> +#endif
>   {
> -	struct i2c *i2c_base = omap24_get_base(adap);
> +	struct i2c *i2c_base;
>   	int psc, fsscll = 0, fssclh = 0;
>   	int hsscll = 0, hssclh = 0;
>   	u32 scll = 0, sclh = 0;
>
> +#ifdef CONFIG_SYS_I2C
> +	i2c_base = omap24_get_base(adap);
> +#else
> +	struct omap24_i2c_bus *i2c_bus;
> +
> +	i2c_bus = dev_get_priv(adap);
> +	i2c_base = i2c_bus->i2c_base;
> +#endif
> +
>   	if (speed >= OMAP_I2C_HIGH_SPEED) {
>   		/* High speed */
>   		psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
> @@ -142,8 +177,14 @@ static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
>   		}
>   	}
>
> +#ifdef CONFIG_SYS_I2C
>   	adap->speed	= speed;
>   	adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
> +#else
> +	i2c_bus->clock_frequency = speed;
> +	i2c_bus->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
> +#endif
> +
>   	writew(0, &i2c_base->con);
>   	writew(psc, &i2c_base->psc);
>   	writew(scll, &i2c_base->scll);
> @@ -154,13 +195,26 @@ static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
>   	return 0;
>   }
>
> +#ifdef CONFIG_SYS_I2C
>   static void omap24_i2c_deblock(struct i2c_adapter *adap)
> +#else
> +static int omap24_i2c_deblock(struct udevice *adap)
> +#endif
>   {
> -	struct i2c *i2c_base = omap24_get_base(adap);
> +	struct i2c *i2c_base;
>   	int i;
>   	u16 systest;
>   	u16 orgsystest;
>
> +#ifdef CONFIG_SYS_I2C
> +	i2c_base = omap24_get_base(adap);
> +#else
> +	struct omap24_i2c_bus *i2c_bus;
> +
> +	i2c_bus = dev_get_priv(adap);
> +	i2c_base = i2c_bus->i2c_base;
> +#endif
> +
>   	/* set test mode ST_EN = 1 */
>   	orgsystest = readw(&i2c_base->systest);
>   	systest = orgsystest;
> @@ -198,14 +252,31 @@ static void omap24_i2c_deblock(struct i2c_adapter *adap)
>
>   	/* restore original mode */
>   	writew(orgsystest, &i2c_base->systest);
> +
> +#ifdef CONFIG_DM_I2C
> +	return 0;
> +#endif
>   }
>
> +#ifdef CONFIG_SYS_I2C
>   static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
> +#else
> +static void omap24_i2c_init(struct udevice *adap, int speed, int slaveadd)
> +#endif
>   {
> -	struct i2c *i2c_base = omap24_get_base(adap);
> +	struct i2c *i2c_base;
>   	int timeout = I2C_TIMEOUT;
>   	int deblock = 1;
>
> +#ifdef CONFIG_SYS_I2C
> +	i2c_base = omap24_get_base(adap);
> +#else
> +	struct omap24_i2c_bus *i2c_bus;
> +
> +	i2c_bus = dev_get_priv(adap);
> +	i2c_base = i2c_bus->i2c_base;
> +#endif
> +
>   retry:
>   	if (readw(&i2c_base->con) & I2C_CON_EN) {
>   		writew(0, &i2c_base->con);
> @@ -253,11 +324,24 @@ retry:
>   		}
>   }
>
> +#ifdef CONFIG_SYS_I2C
>   static void flush_fifo(struct i2c_adapter *adap)
> +#else
> +static void flush_fifo(struct udevice *adap)
> +#endif
>   {
> -	struct i2c *i2c_base = omap24_get_base(adap);
> +	struct i2c *i2c_base;
>   	u16 stat;
>
> +#ifdef CONFIG_SYS_I2C
> +	i2c_base = omap24_get_base(adap);
> +#else
> +	struct omap24_i2c_bus *i2c_bus;
> +
> +	i2c_bus = dev_get_priv(adap);
> +	i2c_base = i2c_bus->i2c_base;
> +#endif
> +
>   	/*
>   	 * note: if you try and read data when its not there or ready
>   	 * you get a bus error
> @@ -277,12 +361,25 @@ static void flush_fifo(struct i2c_adapter *adap)
>    * i2c_probe: Use write access. Allows to identify addresses that are
>    *            write-only (like the config register of dual-port EEPROMs)
>    */
> +#ifdef CONFIG_SYS_I2C
>   static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
> +#else
> +static int omap24_i2c_probe(struct udevice *adap, uint chip, uint chip_flags)
> +#endif
>   {
> -	struct i2c *i2c_base = omap24_get_base(adap);
> +	struct i2c *i2c_base;
>   	u16 status;
>   	int res = 1; /* default = fail */
>
> +#ifdef CONFIG_SYS_I2C
> +	i2c_base = omap24_get_base(adap);
> +#else
> +	struct omap24_i2c_bus *i2c_bus;
> +
> +	i2c_bus = dev_get_priv(adap);
> +	i2c_base = i2c_bus->i2c_base;
> +#endif
> +
>   	if (chip == readw(&i2c_base->oa))
>   		return res;
>
> @@ -305,17 +402,26 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
>   		 * silent exit is desired upon unconfigured bus, remove the
>   		 * following 'if' section:
>   		 */
> -		if (status == I2C_STAT_XRDY)
> +		if (status == I2C_STAT_XRDY) {
> +#ifdef CONFIG_SYS_I2C
>   			printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
>   			       adap->hwadapnr, status);
> -
> +#else
> +			printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
> +			       i2c_bus->bus_num, status);
> +#endif
> +		}
>   		goto pr_exit;
>   	}
>
>   	/* Check for ACK (!NAK) */
>   	if (!(status & I2C_STAT_NACK)) {
>   		res = 0;				/* Device found */
> +#ifdef CONFIG_SYS_I2C
>   		udelay(adap->waitdelay);/* Required by AM335X in SPL */
> +#else
> +		udelay(i2c_bus->waitdelay);
> +#endif
>   		/* Abort transfer (force idle state) */
>   		writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
>   		udelay(1000);
> @@ -341,13 +447,27 @@ pr_exit:
>    *           or that do not need a register address at all (such as some clock
>    *           distributors).
>    */
> +#ifdef CONFIG_SYS_I2C
>   static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
>   			   int alen, uchar *buffer, int len)
> +#else
> +static int omap24_i2c_read(struct udevice *adap, uchar chip, uint addr,
> +			   int alen, uchar *buffer, int len)
> +#endif
>   {
> -	struct i2c *i2c_base = omap24_get_base(adap);
> +	struct i2c *i2c_base;
>   	int i2c_error = 0;
>   	u16 status;
>
> +#ifdef CONFIG_SYS_I2C
> +	i2c_base = omap24_get_base(adap);
> +#else
> +	struct omap24_i2c_bus *i2c_bus;
> +
> +	i2c_bus = dev_get_priv(adap);
> +	i2c_base = i2c_bus->i2c_base;
> +#endif
> +
>   	if (alen < 0) {
>   		puts("I2C read: addr len < 0\n");
>   		return 1;
> @@ -397,8 +517,13 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
>   			/* Try to identify bus that is not padconf'd for I2C */
>   			if (status == I2C_STAT_XRDY) {
>   				i2c_error = 2;
> +#ifdef CONFIG_SYS_I2C
>   				printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
>   				       adap->hwadapnr, status);
> +#else
> +				printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
> +				       i2c_bus->bus_num, status);
> +#endif
>   				goto rd_exit;
>   			}
>   			if (status == 0 || (status & I2C_STAT_NACK)) {
> @@ -441,8 +566,13 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
>   		 */
>   		if (status == I2C_STAT_XRDY) {
>   			i2c_error = 2;
> +#ifdef CONFIG_SYS_I2C
>   			printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
>   			       adap->hwadapnr, status);
> +#else
> +			printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
> +			       i2c_bus->bus_num, status);
> +#endif
>   			goto rd_exit;
>   		}
>   		if (status == 0 || (status & I2C_STAT_NACK)) {
> @@ -466,15 +596,29 @@ rd_exit:
>   }
>
>   /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
> +#ifdef CONFIG_SYS_I2C
>   static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
>   			    int alen, uchar *buffer, int len)
> +#else
> +static int omap24_i2c_write(struct udevice *adap, uchar chip, uint addr,
> +			    int alen, uchar *buffer, int len)
> +#endif
>   {
> -	struct i2c *i2c_base = omap24_get_base(adap);
> +	struct i2c *i2c_base;
>   	int i;
>   	u16 status;
>   	int i2c_error = 0;
>   	int timeout = I2C_TIMEOUT;
>
> +#ifdef CONFIG_SYS_I2C
> +	i2c_base = omap24_get_base(adap);
> +#else
> +	struct omap24_i2c_bus *i2c_bus;
> +
> +	i2c_bus = dev_get_priv(adap);
> +	i2c_base = i2c_bus->i2c_base;
> +#endif
> +
>   	if (alen < 0) {
>   		puts("I2C write: addr len < 0\n");
>   		return 1;
> @@ -519,8 +663,13 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
>   		/* Try to identify bus that is not padconf'd for I2C */
>   		if (status == I2C_STAT_XRDY) {
>   			i2c_error = 2;
> +#ifdef CONFIG_SYS_I2C
>   			printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
>   			       adap->hwadapnr, status);
> +#else
> +			printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
> +			       i2c_bus->bus_num, status);
> +#endif
>   			goto wr_exit;
>   		}
>   		if (status == 0 || (status & I2C_STAT_NACK)) {
> @@ -579,12 +728,25 @@ wr_exit:
>    * Wait for the bus to be free by checking the Bus Busy (BB)
>    * bit to become clear
>    */
> +#ifdef CONFIG_SYS_I2C
>   static int wait_for_bb(struct i2c_adapter *adap)
> +#else
> +static int wait_for_bb(struct udevice *adap)
> +#endif
>   {
> -	struct i2c *i2c_base = omap24_get_base(adap);
> +	struct i2c *i2c_base;
>   	int timeout = I2C_TIMEOUT;
>   	u16 stat;
>
> +#ifdef CONFIG_SYS_I2C
> +	i2c_base = omap24_get_base(adap);
> +#else
> +	struct omap24_i2c_bus *i2c_bus;
> +
> +	i2c_bus = dev_get_priv(adap);
> +	i2c_base = i2c_bus->i2c_base;
> +#endif
> +
>   	writew(0xFFFF, &i2c_base->stat);	/* clear current interrupts...*/
>   #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
>   	while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
> @@ -594,7 +756,11 @@ static int wait_for_bb(struct i2c_adapter *adap)
>   		I2C_STAT_BB) && timeout--) {
>   #endif
>   		writew(stat, &i2c_base->stat);
> +#ifdef CONFIG_SYS_I2C
>   		udelay(adap->waitdelay);
> +#else
> +		udelay(i2c_bus->waitdelay);
> +#endif
>   	}
>
>   	if (timeout <= 0) {
> @@ -610,14 +776,31 @@ static int wait_for_bb(struct i2c_adapter *adap)
>    * Wait for the I2C controller to complete current action
>    * and update status
>    */
> +#ifdef CONFIG_SYS_I2C
>   static u16 wait_for_event(struct i2c_adapter *adap)
> +#else
> +static u16 wait_for_event(struct udevice *adap)
> +#endif
>   {
> -	struct i2c *i2c_base = omap24_get_base(adap);
> +	struct i2c *i2c_base;
>   	u16 status;
>   	int timeout = I2C_TIMEOUT;
>
> +#ifdef CONFIG_SYS_I2C
> +	i2c_base = omap24_get_base(adap);
> +#else
> +	struct omap24_i2c_bus *i2c_bus;
> +
> +	i2c_bus = dev_get_priv(adap);
> +	i2c_base = i2c_bus->i2c_base;
> +#endif
> +
>   	do {
> +#ifdef CONFIG_SYS_I2C
>   		udelay(adap->waitdelay);
> +#else
> +		udelay(i2c_bus->waitdelay);
> +#endif
>   #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
>   		status = readw(&i2c_base->stat);
>   #else
> @@ -636,8 +819,13 @@ static u16 wait_for_event(struct i2c_adapter *adap)
>   		 * If status is still 0 here, probably the bus pads have
>   		 * not been configured for I2C, and/or pull-ups are missing.
>   		 */
> +#ifdef CONFIG_SYS_I2C
>   		printf("Check if pads/pull-ups of bus %d are properly configured\n",
>   		       adap->hwadapnr);
> +#else
> +		printf("Check if pads/pull-ups of bus %d are properly configured\n",
> +		       i2c_bus->bus_num);
> +#endif
>   		writew(0xFFFF, &i2c_base->stat);
>   		status = 0;
>   	}
> @@ -645,6 +833,7 @@ static u16 wait_for_event(struct i2c_adapter *adap)
>   	return status;
>   }
>
> +#ifdef CONFIG_SYS_I2C
>   static struct i2c *omap24_get_base(struct i2c_adapter *adap)
>   {
>   	switch (adap->hwadapnr) {
> @@ -735,3 +924,72 @@ U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
>   #endif
>   #endif
>   #endif
> +#endif
> +
> +#ifdef CONFIG_DM_I2C
> +static int omap24_i2c_xfer(struct udevice *adap, struct i2c_msg *msg,
> +			   int nmsgs)
> +{
> +	int ret;
> +
> +	for (; nmsgs > 0; nmsgs--, msg++) {
> +		if (msg->flags & I2C_M_RD) {
> +			ret = omap24_i2c_read(adap, msg->addr, 0, 0, msg->buf,
> +					      msg->len);
> +		} else {
> +			ret = omap24_i2c_write(adap, msg->addr, 0, 0, msg->buf,
> +					       msg->len);
> +		}
> +
> +		if (ret)
> +			return -EREMOTEIO;
> +	}
> +
> +	return 0;
> +}
> +
> +static int omap24_i2c_ofdata_to_platdata(struct udevice *adap)
> +{
> +	const void *blob = gd->fdt_blob;
> +	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
> +	int node;
> +
> +	node = adap->of_offset;
> +
> +	i2c_bus->clock_frequency = fdtdec_get_int(blob, node,
> +						  "clock-frequency", 100000);
> +	i2c_bus->i2c_base = (struct i2c *)dev_get_addr(adap);
> +	i2c_bus->waitdelay = (10000000 / i2c_bus->clock_frequency) * 2; /* wait for 20 clkperiods */
> +
> +	i2c_bus->bus_num = adap->seq;
> +
> +	omap24_i2c_init(adap, i2c_bus->clock_frequency, 1);
> +
> +	return 0;
> +}
> +
> +static const struct dm_i2c_ops omap24_i2c_ops = {
> +	.xfer           = omap24_i2c_xfer,
> +	.probe_chip     = omap24_i2c_probe,
> +	.set_bus_speed  = omap24_i2c_setspeed,
> +	.deblock	= omap24_i2c_deblock,
> +};
> +
> +static const struct udevice_id omap24_i2c_ids[] = {
> +	{ .compatible = "ti,omap3-i2c" },
> +	{ .compatible = "ti,omap4-i2c" },
> +	{ .compatible = "ti,omap2430-i2c" },
> +	{ .compatible = "ti,omap2420-i2c" },
> +	{ }
> +};
> +
> +U_BOOT_DRIVER(omap_i2c) = {
> +	.name   = "omap_i2c",
> +	.id     = UCLASS_I2C,
> +	.of_match = omap24_i2c_ids,
> +	.ofdata_to_platdata = omap24_i2c_ofdata_to_platdata,
> +	.per_child_auto_alloc_size = sizeof(struct dm_i2c_chip),
> +	.priv_auto_alloc_size = sizeof(struct omap24_i2c_bus),
> +	.ops    = &omap24_i2c_ops,
> +};
> +#endif
>

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH 2/5] i2c: omap24xx: Fix waitdelay value for I2C HS

[Heiko Schocher]

Hello Christophe,

Am 17.01.2016 um 12:09 schrieb Christophe Ricard:
> After several testings and experiment, it appears that waitdelay calculation
> formula was giving different behavior on the i2c status registers.
>
> Experiment shows waitdelay needs to be extended at least 4 times to get
> proper results.
>
> Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
> ---
>
>   drivers/i2c/omap24xx_i2c.c | 18 ++++++++++++------
>   1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
> index f3a4d96..d6e5fe9 100644
> --- a/drivers/i2c/omap24xx_i2c.c
> +++ b/drivers/i2c/omap24xx_i2c.c
> @@ -168,6 +168,13 @@ static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
>   		scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
>   		sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
>
> +#ifdef CONFIG_SYS_I2C
> +		adap->speed	= speed;
> +		adap->waitdelay = (10000000 / speed) * 8; /* wait for 20 clkperiods */
> +#else
> +		i2c_bus->clock_frequency = speed;
> +		i2c_bus->waitdelay = (10000000 / speed) * 8; /* wait for 20 clkperiods */
> +#endif
>   	} else {
>   		/* Standard and fast speed */
>   		psc = omap24_i2c_findpsc(&scll, &sclh, speed);
> @@ -175,15 +182,15 @@ static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
>   			puts("Error : I2C initializing clock\n");
>   			return -1;
>   		}
> -	}
>
>   #ifdef CONFIG_SYS_I2C
> -	adap->speed	= speed;
> -	adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
> +		adap->speed	= speed;
> +		adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
>   #else
> -	i2c_bus->clock_frequency = speed;
> -	i2c_bus->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
> +		i2c_bus->clock_frequency = speed;
> +		i2c_bus->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
>   #endif
> +	}

You change here only the "speed >= OMAP_I2C_HIGH_SPEED" case ... Is this your intention?

If so, please add this info in your commit message.

Beside of this nitpick:

Acked-by: Heiko Schocher <hs@denx.de>

bye,
Heiko
>
>   	writew(0, &i2c_base->con);
>   	writew(psc, &i2c_base->psc);
> @@ -467,7 +474,6 @@ static int omap24_i2c_read(struct udevice *adap, uchar chip, uint addr,
>   	i2c_bus = dev_get_priv(adap);
>   	i2c_base = i2c_bus->i2c_base;
>   #endif
> -
>   	if (alen < 0) {
>   		puts("I2C read: addr len < 0\n");
>   		return 1;
>

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH 3/5] i2c: omap24xx: Remove unused I2C_WAIT macro

[Heiko Schocher]

Hello Christophe,

Am 17.01.2016 um 12:09 schrieb Christophe Ricard:
> I2C_WAIT macro is not used in the code.
> 200 is bound to a fixed 100000 Hz i2c speed based on an existing formula:
> ( 10000000 / speed ) * 2 where speed = 100 000.
>
> Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
> ---
>
>   drivers/i2c/omap24xx_i2c.c | 3 ---
>   1 file changed, 3 deletions(-)

Thanks!

Acked-by: Heiko Schocher <hs@denx.de>

bye,
Heiko
>
> diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
> index d6e5fe9..48ca446 100644
> --- a/drivers/i2c/omap24xx_i2c.c
> +++ b/drivers/i2c/omap24xx_i2c.c
> @@ -55,9 +55,6 @@ DECLARE_GLOBAL_DATA_PTR;
>
>   #define I2C_TIMEOUT	1000
>
> -/* Absolutely safe for status update at 100 kHz I2C: */
> -#define I2C_WAIT	200
> -
>   #ifdef CONFIG_DM_I2C
>   struct omap24_i2c_bus {
>   	int bus_num;
>

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH 4/5] i2c: omap24xx: Fix high speed trimming calculation

[Heiko Schocher]

Hello Christophe,

Am 17.01.2016 um 12:09 schrieb Christophe Ricard:
> Work based on i2c-omap.c from linux kernel.
>
> fsscll/fssclh and hsscll/hssclh was always negative in high speed.
>
> i2c high speed frequency start after 400Khz.
>
> Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
> ---
>
>   drivers/i2c/omap24xx_i2c.c | 17 +++++++++--------
>   1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
> index 48ca446..774edaf 100644
> --- a/drivers/i2c/omap24xx_i2c.c
> +++ b/drivers/i2c/omap24xx_i2c.c
> @@ -129,7 +129,9 @@ static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
>   	i2c_base = i2c_bus->i2c_base;
>   #endif
>
> -	if (speed >= OMAP_I2C_HIGH_SPEED) {
> +	if (speed > 400000) {

Why you remove the define?

> +		unsigned long scl;
> +
>   		/* High speed */
>   		psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
>   		psc -= 1;
> @@ -139,12 +141,11 @@ static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
>   		}
>
>   		/* For first phase of HS mode */
> -		fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
> +		scl = I2C_INTERNAL_SAMPLING_CLK / 400000;
>
> -		fssclh = fsscll;
> +		fsscll = scl - (scl / 3) - 7;
> +		fssclh = (scl / 3)  - 5;
>
> -		fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
> -		fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
>   		if (((fsscll < 0) || (fssclh < 0)) ||
>   		    ((fsscll > 255) || (fssclh > 255))) {
>   			puts("Error : I2C initializing first phase clock\n");
> @@ -152,10 +153,10 @@ static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
>   		}
>
>   		/* For second phase of HS mode */
> -		hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
> +		scl = I2C_IP_CLK / speed;
> +		hsscll = scl - (scl / 3) - 7;
> +		hssclh = (scl / 3) - 5;
>
> -		hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
> -		hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
>   		if (((fsscll < 0) || (fssclh < 0)) ||
>   		    ((fsscll > 255) || (fssclh > 255))) {
>   			puts("Error : I2C initializing second phase clock\n");
>

Reviewed-by: Heiko Schocher <hs@denx.de>

bye,
Heiko
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH 5/5] i2c: omap24xx: Convert fully to DM_I2C

[Heiko Schocher]

Hello Christophe,

Am 17.01.2016 um 12:09 schrieb Christophe Ricard:
> For several reasons:
> - code clarity
> - DM trends in u-boot
> ...
>
> It is better to make omap24xx_i2c driver 100% DM_I2C based.
>
> Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
> ---
>
>   drivers/i2c/omap24xx_i2c.c | 447 +++++++++++++++++----------------------------
>   drivers/i2c/omap24xx_i2c.h | 154 ----------------
>   2 files changed, 163 insertions(+), 438 deletions(-)
>   delete mode 100644 drivers/i2c/omap24xx_i2c.h

Full Ack .. but does this patch does not breeak boards, which use this
driver, and are not converted to DM ? I think, we could remove the
old style only, if all boards are converted ...

bye,
Heiko
>
> diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
> index 774edaf..baccb89 100644
> --- a/drivers/i2c/omap24xx_i2c.c
> +++ b/drivers/i2c/omap24xx_i2c.c
> @@ -49,31 +49,164 @@
>   #include <asm/io.h>
>   #include <asm/errno.h>
>
> -#include "omap24xx_i2c.h"
> -

?

Why do you remove the header file, and move all definitions into the
c file?

>   DECLARE_GLOBAL_DATA_PTR;
>
> +/* I2C masks */
> +
> +/* I2C Interrupt Enable Register (I2C_IE): */
> +#define I2C_IE_GC_IE	(1 << 5)
> +#define I2C_IE_XRDY_IE	(1 << 4) /* Transmit data ready interrupt enable */
> +#define I2C_IE_RRDY_IE	(1 << 3) /* Receive data ready interrupt enable */
> +#define I2C_IE_ARDY_IE	(1 << 2) /* Register access ready interrupt enable */
> +#define I2C_IE_NACK_IE	(1 << 1) /* No acknowledgment interrupt enable */
> +#define I2C_IE_AL_IE	(1 << 0) /* Arbitration lost interrupt enable */
> +
> +/* I2C Status Register (I2C_STAT): */
> +
> +#define I2C_STAT_SBD	(1 << 15) /* Single byte data */
> +#define I2C_STAT_BB	(1 << 12) /* Bus busy */
> +#define I2C_STAT_ROVR	(1 << 11) /* Receive overrun */
> +#define I2C_STAT_XUDF	(1 << 10) /* Transmit underflow */
> +#define I2C_STAT_AAS	(1 << 9)  /* Address as slave */
> +#define I2C_STAT_GC	(1 << 5)
> +#define I2C_STAT_XRDY	(1 << 4)  /* Transmit data ready */
> +#define I2C_STAT_RRDY	(1 << 3)  /* Receive data ready */
> +#define I2C_STAT_ARDY	(1 << 2)  /* Register access ready */
> +#define I2C_STAT_NACK	(1 << 1)  /* No acknowledgment interrupt enable */
> +#define I2C_STAT_AL	(1 << 0)  /* Arbitration lost interrupt enable */
> +
> +/* I2C Interrupt Code Register (I2C_INTCODE): */
> +
> +#define I2C_INTCODE_MASK	7
> +#define I2C_INTCODE_NONE	0
> +#define I2C_INTCODE_AL		1	/* Arbitration lost */
> +#define I2C_INTCODE_NAK		2	/* No acknowledgement/general call */
> +#define I2C_INTCODE_ARDY	3	/* Register access ready */
> +#define I2C_INTCODE_RRDY	4	/* Rcv data ready */
> +#define I2C_INTCODE_XRDY	5	/* Xmit data ready */
> +
> +/* I2C Buffer Configuration Register (I2C_BUF): */
> +
> +#define I2C_BUF_RDMA_EN		(1 << 15) /* Receive DMA channel enable */
> +#define I2C_BUF_XDMA_EN		(1 << 7)  /* Transmit DMA channel enable */
> +
> +/* I2C Configuration Register (I2C_CON): */
> +
> +#define I2C_CON_EN	(1 << 15)  /* I2C module enable */
> +#define I2C_CON_BE	(1 << 14)  /* Big endian mode */
> +#define I2C_CON_STB	(1 << 11)  /* Start byte mode (master mode only) */
> +#define I2C_CON_MST	(1 << 10)  /* Master/slave mode */
> +#define I2C_CON_TRX	(1 << 9)   /* Transmitter/receiver mode */
> +				   /* (master mode only) */
> +#define I2C_CON_XA	(1 << 8)   /* Expand address */
> +#define I2C_CON_STP	(1 << 1)   /* Stop condition (master mode only) */
> +#define I2C_CON_STT	(1 << 0)   /* Start condition (master mode only) */
> +
> +/* I2C System Test Register (I2C_SYSTEST): */
> +
> +#define I2C_SYSTEST_ST_EN	(1 << 15) /* System test enable */
> +#define I2C_SYSTEST_FREE	(1 << 14) /* Free running mode, on brkpoint) */
> +#define I2C_SYSTEST_TMODE_MASK	(3 << 12) /* Test mode select */
> +#define I2C_SYSTEST_TMODE_SHIFT	(12)	  /* Test mode select */
> +#define I2C_SYSTEST_SCL_I	(1 << 3)  /* SCL line sense input value */
> +#define I2C_SYSTEST_SCL_O	(1 << 2)  /* SCL line drive output value */
> +#define I2C_SYSTEST_SDA_I	(1 << 1)  /* SDA line sense input value */
> +#define I2C_SYSTEST_SDA_O	(1 << 0)  /* SDA line drive output value */
> +
> +/* I2C System Status Register (I2C_SYSS): */
> +
> +#define I2C_SYSS_RDONE          (1 << 0)  /* Internel reset monitoring */
> +
> +#define I2C_SCLL_SCLL		0
> +#define I2C_SCLL_SCLL_M		0xFF
> +#define I2C_SCLL_HSSCLL		8
> +#define I2C_SCLH_HSSCLL_M	0xFF
> +#define I2C_SCLH_SCLH		0
> +#define I2C_SCLH_SCLH_M		0xFF
> +#define I2C_SCLH_HSSCLH		8
> +#define I2C_SCLH_HSSCLH_M	0xFF
> +
> +#define OMAP_I2C_STANDARD	100000
> +#define OMAP_I2C_FAST_MODE	400000
> +#define OMAP_I2C_HIGH_SPEED	3400000
> +
> +#define SYSTEM_CLOCK_12		12000000
> +#define SYSTEM_CLOCK_13		13000000
> +#define SYSTEM_CLOCK_192	19200000
> +#define SYSTEM_CLOCK_96		96000000
> +
> +/* Use the reference value of 96MHz if not explicitly set by the board */
> +#ifndef I2C_IP_CLK
> +#define I2C_IP_CLK		SYSTEM_CLOCK_96
> +#endif
> +
> +/*
> + * The reference minimum clock for high speed is 19.2MHz.
> + * The linux 2.6.30 kernel uses this value.
> + * The reference minimum clock for fast mode is 9.6MHz
> + * The reference minimum clock for standard mode is 4MHz
> + * In TRM, the value of 12MHz is used.
> + */
> +#ifndef I2C_INTERNAL_SAMPLING_CLK
> +#define I2C_INTERNAL_SAMPLING_CLK	19200000
> +#endif
> +
> +/*
> + * The equation for the low and high time is
> + * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
> + * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
> + *
> + * If the duty cycle is 50%
> + *
> + * tlow = scll + scll_trim = sampling clock / (2 * speed)
> + * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
> + *
> + * In TRM
> + * scll_trim = 7
> + * sclh_trim = 5
> + *
> + * The linux 2.6.30 kernel uses
> + * scll_trim = 6
> + * sclh_trim = 6
> + *
> + * These are the trim values for standard and fast speed
> + */
> +#ifndef I2C_FASTSPEED_SCLL_TRIM
> +#define I2C_FASTSPEED_SCLL_TRIM		6
> +#endif
> +#ifndef I2C_FASTSPEED_SCLH_TRIM
> +#define I2C_FASTSPEED_SCLH_TRIM		6
> +#endif
> +
> +/* These are the trim values for high speed */
> +#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
> +#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM	I2C_FASTSPEED_SCLL_TRIM
> +#endif
> +#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
> +#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM	I2C_FASTSPEED_SCLH_TRIM
> +#endif
> +#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
> +#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM	I2C_FASTSPEED_SCLL_TRIM
> +#endif
> +#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
> +#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM	I2C_FASTSPEED_SCLH_TRIM
> +#endif
> +
> +#define I2C_PSC_MAX		0x0f
> +#define I2C_PSC_MIN		0x00
> +
>   #define I2C_TIMEOUT	1000
>
> -#ifdef CONFIG_DM_I2C
>   struct omap24_i2c_bus {
>   	int bus_num;
>   	int waitdelay;
>   	unsigned clock_frequency;
>   	struct i2c *i2c_base;
>   };
> -#endif
>
> -#ifdef CONFIG_SYS_I2C
> -static int wait_for_bb(struct i2c_adapter *adap);
> -static struct i2c *omap24_get_base(struct i2c_adapter *adap);
> -static u16 wait_for_event(struct i2c_adapter *adap);
> -static void flush_fifo(struct i2c_adapter *adap);
> -#else
>   static int wait_for_bb(struct udevice *dev);
>   static u16 wait_for_event(struct udevice *dev);
>   static void flush_fifo(struct udevice *dev);
> -#endif
>
>   static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
>   {
> @@ -109,26 +242,14 @@ static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
>   	return -1;
>   }
>
> -#ifdef CONFIG_SYS_I2C
> -static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
> -#else
>   static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
> -#endif
>   {
> -	struct i2c *i2c_base;
> +	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
> +	struct i2c *i2c_base = i2c_bus->i2c_base;
>   	int psc, fsscll = 0, fssclh = 0;
>   	int hsscll = 0, hssclh = 0;
>   	u32 scll = 0, sclh = 0;
>
> -#ifdef CONFIG_SYS_I2C
> -	i2c_base = omap24_get_base(adap);
> -#else
> -	struct omap24_i2c_bus *i2c_bus;
> -
> -	i2c_bus = dev_get_priv(adap);
> -	i2c_base = i2c_bus->i2c_base;
> -#endif
> -
>   	if (speed > 400000) {
>   		unsigned long scl;
>
> @@ -166,13 +287,8 @@ static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
>   		scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
>   		sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
>
> -#ifdef CONFIG_SYS_I2C
> -		adap->speed	= speed;
> -		adap->waitdelay = (10000000 / speed) * 8; /* wait for 20 clkperiods */
> -#else
>   		i2c_bus->clock_frequency = speed;
>   		i2c_bus->waitdelay = (10000000 / speed) * 8; /* wait for 20 clkperiods */
> -#endif
>   	} else {
>   		/* Standard and fast speed */
>   		psc = omap24_i2c_findpsc(&scll, &sclh, speed);
> @@ -181,13 +297,8 @@ static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
>   			return -1;
>   		}
>
> -#ifdef CONFIG_SYS_I2C
> -		adap->speed	= speed;
> -		adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
> -#else
>   		i2c_bus->clock_frequency = speed;
>   		i2c_bus->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
> -#endif
>   	}
>
>   	writew(0, &i2c_base->con);
> @@ -200,26 +311,14 @@ static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
>   	return 0;
>   }
>
> -#ifdef CONFIG_SYS_I2C
> -static void omap24_i2c_deblock(struct i2c_adapter *adap)
> -#else
>   static int omap24_i2c_deblock(struct udevice *adap)
> -#endif
>   {
> -	struct i2c *i2c_base;
> +	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
> +	struct i2c *i2c_base = i2c_bus->i2c_base;
>   	int i;
>   	u16 systest;
>   	u16 orgsystest;
>
> -#ifdef CONFIG_SYS_I2C
> -	i2c_base = omap24_get_base(adap);
> -#else
> -	struct omap24_i2c_bus *i2c_bus;
> -
> -	i2c_bus = dev_get_priv(adap);
> -	i2c_base = i2c_bus->i2c_base;
> -#endif
> -
>   	/* set test mode ST_EN = 1 */
>   	orgsystest = readw(&i2c_base->systest);
>   	systest = orgsystest;
> @@ -258,30 +357,16 @@ static int omap24_i2c_deblock(struct udevice *adap)
>   	/* restore original mode */
>   	writew(orgsystest, &i2c_base->systest);
>
> -#ifdef CONFIG_DM_I2C
>   	return 0;
> -#endif
>   }
>
> -#ifdef CONFIG_SYS_I2C
> -static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
> -#else
>   static void omap24_i2c_init(struct udevice *adap, int speed, int slaveadd)
> -#endif
>   {
> -	struct i2c *i2c_base;
> +	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
> +	struct i2c *i2c_base = i2c_bus->i2c_base;
>   	int timeout = I2C_TIMEOUT;
>   	int deblock = 1;
>
> -#ifdef CONFIG_SYS_I2C
> -	i2c_base = omap24_get_base(adap);
> -#else
> -	struct omap24_i2c_bus *i2c_bus;
> -
> -	i2c_bus = dev_get_priv(adap);
> -	i2c_base = i2c_bus->i2c_base;
> -#endif
> -
>   retry:
>   	if (readw(&i2c_base->con) & I2C_CON_EN) {
>   		writew(0, &i2c_base->con);
> @@ -329,24 +414,12 @@ retry:
>   		}
>   }
>
> -#ifdef CONFIG_SYS_I2C
> -static void flush_fifo(struct i2c_adapter *adap)
> -#else
>   static void flush_fifo(struct udevice *adap)
> -#endif
>   {
> -	struct i2c *i2c_base;
> +	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
> +	struct i2c *i2c_base = i2c_bus->i2c_base;
>   	u16 stat;
>
> -#ifdef CONFIG_SYS_I2C
> -	i2c_base = omap24_get_base(adap);
> -#else
> -	struct omap24_i2c_bus *i2c_bus;
> -
> -	i2c_bus = dev_get_priv(adap);
> -	i2c_base = i2c_bus->i2c_base;
> -#endif
> -
>   	/*
>   	 * note: if you try and read data when its not there or ready
>   	 * you get a bus error
> @@ -366,25 +439,13 @@ static void flush_fifo(struct udevice *adap)
>    * i2c_probe: Use write access. Allows to identify addresses that are
>    *            write-only (like the config register of dual-port EEPROMs)
>    */
> -#ifdef CONFIG_SYS_I2C
> -static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
> -#else
>   static int omap24_i2c_probe(struct udevice *adap, uint chip, uint chip_flags)
> -#endif
>   {
> -	struct i2c *i2c_base;
> +	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
> +	struct i2c *i2c_base = i2c_bus->i2c_base;
>   	u16 status;
>   	int res = 1; /* default = fail */
>
> -#ifdef CONFIG_SYS_I2C
> -	i2c_base = omap24_get_base(adap);
> -#else
> -	struct omap24_i2c_bus *i2c_bus;
> -
> -	i2c_bus = dev_get_priv(adap);
> -	i2c_base = i2c_bus->i2c_base;
> -#endif
> -
>   	if (chip == readw(&i2c_base->oa))
>   		return res;
>
> @@ -407,26 +468,16 @@ static int omap24_i2c_probe(struct udevice *adap, uint chip, uint chip_flags)
>   		 * silent exit is desired upon unconfigured bus, remove the
>   		 * following 'if' section:
>   		 */
> -		if (status == I2C_STAT_XRDY) {
> -#ifdef CONFIG_SYS_I2C
> -			printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
> -			       adap->hwadapnr, status);
> -#else
> +		if (status == I2C_STAT_XRDY)
>   			printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
>   			       i2c_bus->bus_num, status);
> -#endif
> -		}
>   		goto pr_exit;
>   	}
>
>   	/* Check for ACK (!NAK) */
>   	if (!(status & I2C_STAT_NACK)) {
>   		res = 0;				/* Device found */
> -#ifdef CONFIG_SYS_I2C
> -		udelay(adap->waitdelay);/* Required by AM335X in SPL */
> -#else
>   		udelay(i2c_bus->waitdelay);
> -#endif
>   		/* Abort transfer (force idle state) */
>   		writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
>   		udelay(1000);
> @@ -452,26 +503,14 @@ pr_exit:
>    *           or that do not need a register address at all (such as some clock
>    *           distributors).
>    */
> -#ifdef CONFIG_SYS_I2C
> -static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
> -			   int alen, uchar *buffer, int len)
> -#else
>   static int omap24_i2c_read(struct udevice *adap, uchar chip, uint addr,
>   			   int alen, uchar *buffer, int len)
> -#endif
>   {
> -	struct i2c *i2c_base;
> +	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
> +	struct i2c *i2c_base = i2c_bus->i2c_base;
>   	int i2c_error = 0;
>   	u16 status;
>
> -#ifdef CONFIG_SYS_I2C
> -	i2c_base = omap24_get_base(adap);
> -#else
> -	struct omap24_i2c_bus *i2c_bus;
> -
> -	i2c_bus = dev_get_priv(adap);
> -	i2c_base = i2c_bus->i2c_base;
> -#endif
>   	if (alen < 0) {
>   		puts("I2C read: addr len < 0\n");
>   		return 1;
> @@ -521,13 +560,8 @@ static int omap24_i2c_read(struct udevice *adap, uchar chip, uint addr,
>   			/* Try to identify bus that is not padconf'd for I2C */
>   			if (status == I2C_STAT_XRDY) {
>   				i2c_error = 2;
> -#ifdef CONFIG_SYS_I2C
> -				printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
> -				       adap->hwadapnr, status);
> -#else
>   				printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
>   				       i2c_bus->bus_num, status);
> -#endif
>   				goto rd_exit;
>   			}
>   			if (status == 0 || (status & I2C_STAT_NACK)) {
> @@ -570,13 +604,8 @@ static int omap24_i2c_read(struct udevice *adap, uchar chip, uint addr,
>   		 */
>   		if (status == I2C_STAT_XRDY) {
>   			i2c_error = 2;
> -#ifdef CONFIG_SYS_I2C
> -			printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
> -			       adap->hwadapnr, status);
> -#else
>   			printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
>   			       i2c_bus->bus_num, status);
> -#endif
>   			goto rd_exit;
>   		}
>   		if (status == 0 || (status & I2C_STAT_NACK)) {
> @@ -600,29 +629,16 @@ rd_exit:
>   }
>
>   /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
> -#ifdef CONFIG_SYS_I2C
> -static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
> -			    int alen, uchar *buffer, int len)
> -#else
>   static int omap24_i2c_write(struct udevice *adap, uchar chip, uint addr,
>   			    int alen, uchar *buffer, int len)
> -#endif
>   {
> -	struct i2c *i2c_base;
> +	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
> +	struct i2c *i2c_base = i2c_bus->i2c_base;
>   	int i;
>   	u16 status;
>   	int i2c_error = 0;
>   	int timeout = I2C_TIMEOUT;
>
> -#ifdef CONFIG_SYS_I2C
> -	i2c_base = omap24_get_base(adap);
> -#else
> -	struct omap24_i2c_bus *i2c_bus;
> -
> -	i2c_bus = dev_get_priv(adap);
> -	i2c_base = i2c_bus->i2c_base;
> -#endif
> -
>   	if (alen < 0) {
>   		puts("I2C write: addr len < 0\n");
>   		return 1;
> @@ -667,13 +683,8 @@ static int omap24_i2c_write(struct udevice *adap, uchar chip, uint addr,
>   		/* Try to identify bus that is not padconf'd for I2C */
>   		if (status == I2C_STAT_XRDY) {
>   			i2c_error = 2;
> -#ifdef CONFIG_SYS_I2C
> -			printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
> -			       adap->hwadapnr, status);
> -#else
>   			printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
>   			       i2c_bus->bus_num, status);
> -#endif
>   			goto wr_exit;
>   		}
>   		if (status == 0 || (status & I2C_STAT_NACK)) {
> @@ -732,25 +743,13 @@ wr_exit:
>    * Wait for the bus to be free by checking the Bus Busy (BB)
>    * bit to become clear
>    */
> -#ifdef CONFIG_SYS_I2C
> -static int wait_for_bb(struct i2c_adapter *adap)
> -#else
>   static int wait_for_bb(struct udevice *adap)
> -#endif
>   {
> -	struct i2c *i2c_base;
> +	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
> +	struct i2c *i2c_base = i2c_bus->i2c_base;
>   	int timeout = I2C_TIMEOUT;
>   	u16 stat;
>
> -#ifdef CONFIG_SYS_I2C
> -	i2c_base = omap24_get_base(adap);
> -#else
> -	struct omap24_i2c_bus *i2c_bus;
> -
> -	i2c_bus = dev_get_priv(adap);
> -	i2c_base = i2c_bus->i2c_base;
> -#endif
> -
>   	writew(0xFFFF, &i2c_base->stat);	/* clear current interrupts...*/
>   #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
>   	while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
> @@ -760,11 +759,7 @@ static int wait_for_bb(struct udevice *adap)
>   		I2C_STAT_BB) && timeout--) {
>   #endif
>   		writew(stat, &i2c_base->stat);
> -#ifdef CONFIG_SYS_I2C
> -		udelay(adap->waitdelay);
> -#else
>   		udelay(i2c_bus->waitdelay);
> -#endif
>   	}
>
>   	if (timeout <= 0) {
> @@ -780,31 +775,15 @@ static int wait_for_bb(struct udevice *adap)
>    * Wait for the I2C controller to complete current action
>    * and update status
>    */
> -#ifdef CONFIG_SYS_I2C
> -static u16 wait_for_event(struct i2c_adapter *adap)
> -#else
>   static u16 wait_for_event(struct udevice *adap)
> -#endif
>   {
> -	struct i2c *i2c_base;
> +	struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
> +	struct i2c *i2c_base = i2c_bus->i2c_base;
>   	u16 status;
>   	int timeout = I2C_TIMEOUT;
>
> -#ifdef CONFIG_SYS_I2C
> -	i2c_base = omap24_get_base(adap);
> -#else
> -	struct omap24_i2c_bus *i2c_bus;
> -
> -	i2c_bus = dev_get_priv(adap);
> -	i2c_base = i2c_bus->i2c_base;
> -#endif
> -
>   	do {
> -#ifdef CONFIG_SYS_I2C
> -		udelay(adap->waitdelay);
> -#else
>   		udelay(i2c_bus->waitdelay);
> -#endif
>   #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
>   		status = readw(&i2c_base->stat);
>   #else
> @@ -823,13 +802,8 @@ static u16 wait_for_event(struct udevice *adap)
>   		 * If status is still 0 here, probably the bus pads have
>   		 * not been configured for I2C, and/or pull-ups are missing.
>   		 */
> -#ifdef CONFIG_SYS_I2C
> -		printf("Check if pads/pull-ups of bus %d are properly configured\n",
> -		       adap->hwadapnr);
> -#else
>   		printf("Check if pads/pull-ups of bus %d are properly configured\n",
>   		       i2c_bus->bus_num);
> -#endif
>   		writew(0xFFFF, &i2c_base->stat);
>   		status = 0;
>   	}
> @@ -837,100 +811,6 @@ static u16 wait_for_event(struct udevice *adap)
>   	return status;
>   }
>
> -#ifdef CONFIG_SYS_I2C
> -static struct i2c *omap24_get_base(struct i2c_adapter *adap)
> -{
> -	switch (adap->hwadapnr) {
> -	case 0:
> -		return (struct i2c *)I2C_BASE1;
> -		break;
> -	case 1:
> -		return (struct i2c *)I2C_BASE2;
> -		break;
> -#if (I2C_BUS_MAX > 2)
> -	case 2:
> -		return (struct i2c *)I2C_BASE3;
> -		break;
> -#if (I2C_BUS_MAX > 3)
> -	case 3:
> -		return (struct i2c *)I2C_BASE4;
> -		break;
> -#if (I2C_BUS_MAX > 4)
> -	case 4:
> -		return (struct i2c *)I2C_BASE5;
> -		break;
> -#endif
> -#endif
> -#endif
> -	default:
> -		printf("wrong hwadapnr: %d\n", adap->hwadapnr);
> -		break;
> -	}
> -	return NULL;
> -}
> -
> -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
> -#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
> -#endif
> -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
> -#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
> -#endif
> -
> -U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
> -			 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
> -			 CONFIG_SYS_OMAP24_I2C_SPEED,
> -			 CONFIG_SYS_OMAP24_I2C_SLAVE,
> -			 0)
> -U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
> -			 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
> -			 CONFIG_SYS_OMAP24_I2C_SPEED1,
> -			 CONFIG_SYS_OMAP24_I2C_SLAVE1,
> -			 1)
> -#if (I2C_BUS_MAX > 2)
> -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
> -#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
> -#endif
> -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
> -#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
> -#endif
> -
> -U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
> -			 omap24_i2c_read, omap24_i2c_write, NULL,
> -			 CONFIG_SYS_OMAP24_I2C_SPEED2,
> -			 CONFIG_SYS_OMAP24_I2C_SLAVE2,
> -			 2)
> -#if (I2C_BUS_MAX > 3)
> -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
> -#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
> -#endif
> -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
> -#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
> -#endif
> -
> -U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
> -			 omap24_i2c_read, omap24_i2c_write, NULL,
> -			 CONFIG_SYS_OMAP24_I2C_SPEED3,
> -			 CONFIG_SYS_OMAP24_I2C_SLAVE3,
> -			 3)
> -#if (I2C_BUS_MAX > 4)
> -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
> -#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
> -#endif
> -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
> -#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
> -#endif
> -
> -U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
> -			 omap24_i2c_read, omap24_i2c_write, NULL,
> -			 CONFIG_SYS_OMAP24_I2C_SPEED4,
> -			 CONFIG_SYS_OMAP24_I2C_SLAVE4,
> -			 4)
> -#endif
> -#endif
> -#endif
> -#endif
> -
> -#ifdef CONFIG_DM_I2C
>   static int omap24_i2c_xfer(struct udevice *adap, struct i2c_msg *msg,
>   			   int nmsgs)
>   {
> @@ -996,4 +876,3 @@ U_BOOT_DRIVER(omap_i2c) = {
>   	.priv_auto_alloc_size = sizeof(struct omap24_i2c_bus),
>   	.ops    = &omap24_i2c_ops,
>   };
> -#endif
> diff --git a/drivers/i2c/omap24xx_i2c.h b/drivers/i2c/omap24xx_i2c.h
> deleted file mode 100644
> index 3dae295..0000000
> --- a/drivers/i2c/omap24xx_i2c.h
> +++ /dev/null
> @@ -1,154 +0,0 @@
> -/*
> - * (C) Copyright 2004-2010
> - * Texas Instruments, <www.ti.com>
> - *
> - * SPDX-License-Identifier:	GPL-2.0+
> - */
> -#ifndef _OMAP2PLUS_I2C_H_
> -#define _OMAP2PLUS_I2C_H_
> -
> -/* I2C masks */
> -
> -/* I2C Interrupt Enable Register (I2C_IE): */
> -#define I2C_IE_GC_IE	(1 << 5)
> -#define I2C_IE_XRDY_IE	(1 << 4) /* Transmit data ready interrupt enable */
> -#define I2C_IE_RRDY_IE	(1 << 3) /* Receive data ready interrupt enable */
> -#define I2C_IE_ARDY_IE	(1 << 2) /* Register access ready interrupt enable */
> -#define I2C_IE_NACK_IE	(1 << 1) /* No acknowledgment interrupt enable */
> -#define I2C_IE_AL_IE	(1 << 0) /* Arbitration lost interrupt enable */
> -
> -/* I2C Status Register (I2C_STAT): */
> -
> -#define I2C_STAT_SBD	(1 << 15) /* Single byte data */
> -#define I2C_STAT_BB	(1 << 12) /* Bus busy */
> -#define I2C_STAT_ROVR	(1 << 11) /* Receive overrun */
> -#define I2C_STAT_XUDF	(1 << 10) /* Transmit underflow */
> -#define I2C_STAT_AAS	(1 << 9)  /* Address as slave */
> -#define I2C_STAT_GC	(1 << 5)
> -#define I2C_STAT_XRDY	(1 << 4)  /* Transmit data ready */
> -#define I2C_STAT_RRDY	(1 << 3)  /* Receive data ready */
> -#define I2C_STAT_ARDY	(1 << 2)  /* Register access ready */
> -#define I2C_STAT_NACK	(1 << 1)  /* No acknowledgment interrupt enable */
> -#define I2C_STAT_AL	(1 << 0)  /* Arbitration lost interrupt enable */
> -
> -/* I2C Interrupt Code Register (I2C_INTCODE): */
> -
> -#define I2C_INTCODE_MASK	7
> -#define I2C_INTCODE_NONE	0
> -#define I2C_INTCODE_AL		1	/* Arbitration lost */
> -#define I2C_INTCODE_NAK		2	/* No acknowledgement/general call */
> -#define I2C_INTCODE_ARDY	3	/* Register access ready */
> -#define I2C_INTCODE_RRDY	4	/* Rcv data ready */
> -#define I2C_INTCODE_XRDY	5	/* Xmit data ready */
> -
> -/* I2C Buffer Configuration Register (I2C_BUF): */
> -
> -#define I2C_BUF_RDMA_EN		(1 << 15) /* Receive DMA channel enable */
> -#define I2C_BUF_XDMA_EN		(1 << 7)  /* Transmit DMA channel enable */
> -
> -/* I2C Configuration Register (I2C_CON): */
> -
> -#define I2C_CON_EN	(1 << 15)  /* I2C module enable */
> -#define I2C_CON_BE	(1 << 14)  /* Big endian mode */
> -#define I2C_CON_STB	(1 << 11)  /* Start byte mode (master mode only) */
> -#define I2C_CON_MST	(1 << 10)  /* Master/slave mode */
> -#define I2C_CON_TRX	(1 << 9)   /* Transmitter/receiver mode */
> -				   /* (master mode only) */
> -#define I2C_CON_XA	(1 << 8)   /* Expand address */
> -#define I2C_CON_STP	(1 << 1)   /* Stop condition (master mode only) */
> -#define I2C_CON_STT	(1 << 0)   /* Start condition (master mode only) */
> -
> -/* I2C System Test Register (I2C_SYSTEST): */
> -
> -#define I2C_SYSTEST_ST_EN	(1 << 15) /* System test enable */
> -#define I2C_SYSTEST_FREE	(1 << 14) /* Free running mode, on brkpoint) */
> -#define I2C_SYSTEST_TMODE_MASK	(3 << 12) /* Test mode select */
> -#define I2C_SYSTEST_TMODE_SHIFT	(12)	  /* Test mode select */
> -#define I2C_SYSTEST_SCL_I	(1 << 3)  /* SCL line sense input value */
> -#define I2C_SYSTEST_SCL_O	(1 << 2)  /* SCL line drive output value */
> -#define I2C_SYSTEST_SDA_I	(1 << 1)  /* SDA line sense input value */
> -#define I2C_SYSTEST_SDA_O	(1 << 0)  /* SDA line drive output value */
> -
> -/* I2C System Status Register (I2C_SYSS): */
> -
> -#define I2C_SYSS_RDONE          (1 << 0)  /* Internel reset monitoring */
> -
> -#define I2C_SCLL_SCLL		0
> -#define I2C_SCLL_SCLL_M		0xFF
> -#define I2C_SCLL_HSSCLL		8
> -#define I2C_SCLH_HSSCLL_M	0xFF
> -#define I2C_SCLH_SCLH		0
> -#define I2C_SCLH_SCLH_M		0xFF
> -#define I2C_SCLH_HSSCLH		8
> -#define I2C_SCLH_HSSCLH_M	0xFF
> -
> -#define OMAP_I2C_STANDARD	100000
> -#define OMAP_I2C_FAST_MODE	400000
> -#define OMAP_I2C_HIGH_SPEED	3400000
> -
> -#define SYSTEM_CLOCK_12		12000000
> -#define SYSTEM_CLOCK_13		13000000
> -#define SYSTEM_CLOCK_192	19200000
> -#define SYSTEM_CLOCK_96		96000000
> -
> -/* Use the reference value of 96MHz if not explicitly set by the board */
> -#ifndef I2C_IP_CLK
> -#define I2C_IP_CLK		SYSTEM_CLOCK_96
> -#endif
> -
> -/*
> - * The reference minimum clock for high speed is 19.2MHz.
> - * The linux 2.6.30 kernel uses this value.
> - * The reference minimum clock for fast mode is 9.6MHz
> - * The reference minimum clock for standard mode is 4MHz
> - * In TRM, the value of 12MHz is used.
> - */
> -#ifndef I2C_INTERNAL_SAMPLING_CLK
> -#define I2C_INTERNAL_SAMPLING_CLK	19200000
> -#endif
> -
> -/*
> - * The equation for the low and high time is
> - * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
> - * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
> - *
> - * If the duty cycle is 50%
> - *
> - * tlow = scll + scll_trim = sampling clock / (2 * speed)
> - * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
> - *
> - * In TRM
> - * scll_trim = 7
> - * sclh_trim = 5
> - *
> - * The linux 2.6.30 kernel uses
> - * scll_trim = 6
> - * sclh_trim = 6
> - *
> - * These are the trim values for standard and fast speed
> - */
> -#ifndef I2C_FASTSPEED_SCLL_TRIM
> -#define I2C_FASTSPEED_SCLL_TRIM		6
> -#endif
> -#ifndef I2C_FASTSPEED_SCLH_TRIM
> -#define I2C_FASTSPEED_SCLH_TRIM		6
> -#endif
> -
> -/* These are the trim values for high speed */
> -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
> -#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM	I2C_FASTSPEED_SCLL_TRIM
> -#endif
> -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
> -#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM	I2C_FASTSPEED_SCLH_TRIM
> -#endif
> -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
> -#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM	I2C_FASTSPEED_SCLL_TRIM
> -#endif
> -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
> -#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM	I2C_FASTSPEED_SCLH_TRIM
> -#endif
> -
> -#define I2C_PSC_MAX		0x0f
> -#define I2C_PSC_MIN		0x00
> -
> -#endif /* _OMAP24XX_I2C_H_ */
>

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH 5/5] i2c: omap24xx: Convert fully to DM_I2C

[Christophe Ricard]

Hi Heiko,

I was expecting such kind of feedback on this one :).
I had myself to hack around between the MLO and the u-boot.img to get it
working.

For omap, i think twlxxxx drivers are kind of the main item to convert.

Would you accept to take the first 4 patches until the board are fully
ready for the 5th one ?

Best Regards
Christophe

2016-01-18 7:04 GMT+01:00 Heiko Schocher <hs@denx.de>:

> Hello Christophe,
>
> Am 17.01.2016 um 12:09 schrieb Christophe Ricard:
>
>> For several reasons:
>> - code clarity
>> - DM trends in u-boot
>> ...
>>
>> It is better to make omap24xx_i2c driver 100% DM_I2C based.
>>
>> Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
>> ---
>>
>>   drivers/i2c/omap24xx_i2c.c | 447
>> +++++++++++++++++----------------------------
>>   drivers/i2c/omap24xx_i2c.h | 154 ----------------
>>   2 files changed, 163 insertions(+), 438 deletions(-)
>>   delete mode 100644 drivers/i2c/omap24xx_i2c.h
>>
>
> Full Ack .. but does this patch does not breeak boards, which use this
> driver, and are not converted to DM ? I think, we could remove the
> old style only, if all boards are converted ...
>
> bye,
> Heiko
>
>>
>> diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
>> index 774edaf..baccb89 100644
>> --- a/drivers/i2c/omap24xx_i2c.c
>> +++ b/drivers/i2c/omap24xx_i2c.c
>> @@ -49,31 +49,164 @@
>>   #include <asm/io.h>
>>   #include <asm/errno.h>
>>
>> -#include "omap24xx_i2c.h"
>> -
>>
>
> ?
>
> Why do you remove the header file, and move all definitions into the
> c file?
>
>
>   DECLARE_GLOBAL_DATA_PTR;
>>
>> +/* I2C masks */
>> +
>> +/* I2C Interrupt Enable Register (I2C_IE): */
>> +#define I2C_IE_GC_IE   (1 << 5)
>> +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable
>> */
>> +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
>> +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt
>> enable */
>> +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
>> +#define I2C_IE_AL_IE   (1 << 0) /* Arbitration lost interrupt enable */
>> +
>> +/* I2C Status Register (I2C_STAT): */
>> +
>> +#define I2C_STAT_SBD   (1 << 15) /* Single byte data */
>> +#define I2C_STAT_BB    (1 << 12) /* Bus busy */
>> +#define I2C_STAT_ROVR  (1 << 11) /* Receive overrun */
>> +#define I2C_STAT_XUDF  (1 << 10) /* Transmit underflow */
>> +#define I2C_STAT_AAS   (1 << 9)  /* Address as slave */
>> +#define I2C_STAT_GC    (1 << 5)
>> +#define I2C_STAT_XRDY  (1 << 4)  /* Transmit data ready */
>> +#define I2C_STAT_RRDY  (1 << 3)  /* Receive data ready */
>> +#define I2C_STAT_ARDY  (1 << 2)  /* Register access ready */
>> +#define I2C_STAT_NACK  (1 << 1)  /* No acknowledgment interrupt enable */
>> +#define I2C_STAT_AL    (1 << 0)  /* Arbitration lost interrupt enable */
>> +
>> +/* I2C Interrupt Code Register (I2C_INTCODE): */
>> +
>> +#define I2C_INTCODE_MASK       7
>> +#define I2C_INTCODE_NONE       0
>> +#define I2C_INTCODE_AL         1       /* Arbitration lost */
>> +#define I2C_INTCODE_NAK                2       /* No
>> acknowledgement/general call */
>> +#define I2C_INTCODE_ARDY       3       /* Register access ready */
>> +#define I2C_INTCODE_RRDY       4       /* Rcv data ready */
>> +#define I2C_INTCODE_XRDY       5       /* Xmit data ready */
>> +
>> +/* I2C Buffer Configuration Register (I2C_BUF): */
>> +
>> +#define I2C_BUF_RDMA_EN                (1 << 15) /* Receive DMA channel
>> enable */
>> +#define I2C_BUF_XDMA_EN                (1 << 7)  /* Transmit DMA channel
>> enable */
>> +
>> +/* I2C Configuration Register (I2C_CON): */
>> +
>> +#define I2C_CON_EN     (1 << 15)  /* I2C module enable */
>> +#define I2C_CON_BE     (1 << 14)  /* Big endian mode */
>> +#define I2C_CON_STB    (1 << 11)  /* Start byte mode (master mode only)
>> */
>> +#define I2C_CON_MST    (1 << 10)  /* Master/slave mode */
>> +#define I2C_CON_TRX    (1 << 9)   /* Transmitter/receiver mode */
>> +                                  /* (master mode only) */
>> +#define I2C_CON_XA     (1 << 8)   /* Expand address */
>> +#define I2C_CON_STP    (1 << 1)   /* Stop condition (master mode only) */
>> +#define I2C_CON_STT    (1 << 0)   /* Start condition (master mode only)
>> */
>> +
>> +/* I2C System Test Register (I2C_SYSTEST): */
>> +
>> +#define I2C_SYSTEST_ST_EN      (1 << 15) /* System test enable */
>> +#define I2C_SYSTEST_FREE       (1 << 14) /* Free running mode, on
>> brkpoint) */
>> +#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
>> +#define I2C_SYSTEST_TMODE_SHIFT        (12)      /* Test mode select */
>> +#define I2C_SYSTEST_SCL_I      (1 << 3)  /* SCL line sense input value */
>> +#define I2C_SYSTEST_SCL_O      (1 << 2)  /* SCL line drive output value
>> */
>> +#define I2C_SYSTEST_SDA_I      (1 << 1)  /* SDA line sense input value */
>> +#define I2C_SYSTEST_SDA_O      (1 << 0)  /* SDA line drive output value
>> */
>> +
>> +/* I2C System Status Register (I2C_SYSS): */
>> +
>> +#define I2C_SYSS_RDONE          (1 << 0)  /* Internel reset monitoring */
>> +
>> +#define I2C_SCLL_SCLL          0
>> +#define I2C_SCLL_SCLL_M                0xFF
>> +#define I2C_SCLL_HSSCLL                8
>> +#define I2C_SCLH_HSSCLL_M      0xFF
>> +#define I2C_SCLH_SCLH          0
>> +#define I2C_SCLH_SCLH_M                0xFF
>> +#define I2C_SCLH_HSSCLH                8
>> +#define I2C_SCLH_HSSCLH_M      0xFF
>> +
>> +#define OMAP_I2C_STANDARD      100000
>> +#define OMAP_I2C_FAST_MODE     400000
>> +#define OMAP_I2C_HIGH_SPEED    3400000
>> +
>> +#define SYSTEM_CLOCK_12                12000000
>> +#define SYSTEM_CLOCK_13                13000000
>> +#define SYSTEM_CLOCK_192       19200000
>> +#define SYSTEM_CLOCK_96                96000000
>> +
>> +/* Use the reference value of 96MHz if not explicitly set by the board */
>> +#ifndef I2C_IP_CLK
>> +#define I2C_IP_CLK             SYSTEM_CLOCK_96
>> +#endif
>> +
>> +/*
>> + * The reference minimum clock for high speed is 19.2MHz.
>> + * The linux 2.6.30 kernel uses this value.
>> + * The reference minimum clock for fast mode is 9.6MHz
>> + * The reference minimum clock for standard mode is 4MHz
>> + * In TRM, the value of 12MHz is used.
>> + */
>> +#ifndef I2C_INTERNAL_SAMPLING_CLK
>> +#define I2C_INTERNAL_SAMPLING_CLK      19200000
>> +#endif
>> +
>> +/*
>> + * The equation for the low and high time is
>> + * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
>> + * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
>> + *
>> + * If the duty cycle is 50%
>> + *
>> + * tlow = scll + scll_trim = sampling clock / (2 * speed)
>> + * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
>> + *
>> + * In TRM
>> + * scll_trim = 7
>> + * sclh_trim = 5
>> + *
>> + * The linux 2.6.30 kernel uses
>> + * scll_trim = 6
>> + * sclh_trim = 6
>> + *
>> + * These are the trim values for standard and fast speed
>> + */
>> +#ifndef I2C_FASTSPEED_SCLL_TRIM
>> +#define I2C_FASTSPEED_SCLL_TRIM                6
>> +#endif
>> +#ifndef I2C_FASTSPEED_SCLH_TRIM
>> +#define I2C_FASTSPEED_SCLH_TRIM                6
>> +#endif
>> +
>> +/* These are the trim values for high speed */
>> +#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
>> +#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM      I2C_FASTSPEED_SCLL_TRIM
>> +#endif
>> +#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
>> +#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM      I2C_FASTSPEED_SCLH_TRIM
>> +#endif
>> +#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
>> +#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM      I2C_FASTSPEED_SCLL_TRIM
>> +#endif
>> +#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
>> +#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM      I2C_FASTSPEED_SCLH_TRIM
>> +#endif
>> +
>> +#define I2C_PSC_MAX            0x0f
>> +#define I2C_PSC_MIN            0x00
>> +
>>   #define I2C_TIMEOUT   1000
>>
>> -#ifdef CONFIG_DM_I2C
>>   struct omap24_i2c_bus {
>>         int bus_num;
>>         int waitdelay;
>>         unsigned clock_frequency;
>>         struct i2c *i2c_base;
>>   };
>> -#endif
>>
>> -#ifdef CONFIG_SYS_I2C
>> -static int wait_for_bb(struct i2c_adapter *adap);
>> -static struct i2c *omap24_get_base(struct i2c_adapter *adap);
>> -static u16 wait_for_event(struct i2c_adapter *adap);
>> -static void flush_fifo(struct i2c_adapter *adap);
>> -#else
>>   static int wait_for_bb(struct udevice *dev);
>>   static u16 wait_for_event(struct udevice *dev);
>>   static void flush_fifo(struct udevice *dev);
>> -#endif
>>
>>   static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
>>   {
>> @@ -109,26 +242,14 @@ static int omap24_i2c_findpsc(u32 *pscl, u32 *psch,
>> uint speed)
>>         return -1;
>>   }
>>
>> -#ifdef CONFIG_SYS_I2C
>> -static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
>> -#else
>>   static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
>> -#endif
>>   {
>> -       struct i2c *i2c_base;
>> +       struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
>> +       struct i2c *i2c_base = i2c_bus->i2c_base;
>>         int psc, fsscll = 0, fssclh = 0;
>>         int hsscll = 0, hssclh = 0;
>>         u32 scll = 0, sclh = 0;
>>
>> -#ifdef CONFIG_SYS_I2C
>> -       i2c_base = omap24_get_base(adap);
>> -#else
>> -       struct omap24_i2c_bus *i2c_bus;
>> -
>> -       i2c_bus = dev_get_priv(adap);
>> -       i2c_base = i2c_bus->i2c_base;
>> -#endif
>> -
>>         if (speed > 400000) {
>>                 unsigned long scl;
>>
>> @@ -166,13 +287,8 @@ static int omap24_i2c_setspeed(struct udevice *adap,
>> unsigned int speed)
>>                 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
>>                 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
>>
>> -#ifdef CONFIG_SYS_I2C
>> -               adap->speed     = speed;
>> -               adap->waitdelay = (10000000 / speed) * 8; /* wait for 20
>> clkperiods */
>> -#else
>>                 i2c_bus->clock_frequency = speed;
>>                 i2c_bus->waitdelay = (10000000 / speed) * 8; /* wait for
>> 20 clkperiods */
>> -#endif
>>         } else {
>>                 /* Standard and fast speed */
>>                 psc = omap24_i2c_findpsc(&scll, &sclh, speed);
>> @@ -181,13 +297,8 @@ static int omap24_i2c_setspeed(struct udevice *adap,
>> unsigned int speed)
>>                         return -1;
>>                 }
>>
>> -#ifdef CONFIG_SYS_I2C
>> -               adap->speed     = speed;
>> -               adap->waitdelay = (10000000 / speed) * 2; /* wait for 20
>> clkperiods */
>> -#else
>>                 i2c_bus->clock_frequency = speed;
>>                 i2c_bus->waitdelay = (10000000 / speed) * 2; /* wait for
>> 20 clkperiods */
>> -#endif
>>         }
>>
>>         writew(0, &i2c_base->con);
>> @@ -200,26 +311,14 @@ static int omap24_i2c_setspeed(struct udevice
>> *adap, unsigned int speed)
>>         return 0;
>>   }
>>
>> -#ifdef CONFIG_SYS_I2C
>> -static void omap24_i2c_deblock(struct i2c_adapter *adap)
>> -#else
>>   static int omap24_i2c_deblock(struct udevice *adap)
>> -#endif
>>   {
>> -       struct i2c *i2c_base;
>> +       struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
>> +       struct i2c *i2c_base = i2c_bus->i2c_base;
>>         int i;
>>         u16 systest;
>>         u16 orgsystest;
>>
>> -#ifdef CONFIG_SYS_I2C
>> -       i2c_base = omap24_get_base(adap);
>> -#else
>> -       struct omap24_i2c_bus *i2c_bus;
>> -
>> -       i2c_bus = dev_get_priv(adap);
>> -       i2c_base = i2c_bus->i2c_base;
>> -#endif
>> -
>>         /* set test mode ST_EN = 1 */
>>         orgsystest = readw(&i2c_base->systest);
>>         systest = orgsystest;
>> @@ -258,30 +357,16 @@ static int omap24_i2c_deblock(struct udevice *adap)
>>         /* restore original mode */
>>         writew(orgsystest, &i2c_base->systest);
>>
>> -#ifdef CONFIG_DM_I2C
>>         return 0;
>> -#endif
>>   }
>>
>> -#ifdef CONFIG_SYS_I2C
>> -static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int
>> slaveadd)
>> -#else
>>   static void omap24_i2c_init(struct udevice *adap, int speed, int
>> slaveadd)
>> -#endif
>>   {
>> -       struct i2c *i2c_base;
>> +       struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
>> +       struct i2c *i2c_base = i2c_bus->i2c_base;
>>         int timeout = I2C_TIMEOUT;
>>         int deblock = 1;
>>
>> -#ifdef CONFIG_SYS_I2C
>> -       i2c_base = omap24_get_base(adap);
>> -#else
>> -       struct omap24_i2c_bus *i2c_bus;
>> -
>> -       i2c_bus = dev_get_priv(adap);
>> -       i2c_base = i2c_bus->i2c_base;
>> -#endif
>> -
>>   retry:
>>         if (readw(&i2c_base->con) & I2C_CON_EN) {
>>                 writew(0, &i2c_base->con);
>> @@ -329,24 +414,12 @@ retry:
>>                 }
>>   }
>>
>> -#ifdef CONFIG_SYS_I2C
>> -static void flush_fifo(struct i2c_adapter *adap)
>> -#else
>>   static void flush_fifo(struct udevice *adap)
>> -#endif
>>   {
>> -       struct i2c *i2c_base;
>> +       struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
>> +       struct i2c *i2c_base = i2c_bus->i2c_base;
>>         u16 stat;
>>
>> -#ifdef CONFIG_SYS_I2C
>> -       i2c_base = omap24_get_base(adap);
>> -#else
>> -       struct omap24_i2c_bus *i2c_bus;
>> -
>> -       i2c_bus = dev_get_priv(adap);
>> -       i2c_base = i2c_bus->i2c_base;
>> -#endif
>> -
>>         /*
>>          * note: if you try and read data when its not there or ready
>>          * you get a bus error
>> @@ -366,25 +439,13 @@ static void flush_fifo(struct udevice *adap)
>>    * i2c_probe: Use write access. Allows to identify addresses that are
>>    *            write-only (like the config register of dual-port EEPROMs)
>>    */
>> -#ifdef CONFIG_SYS_I2C
>> -static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
>> -#else
>>   static int omap24_i2c_probe(struct udevice *adap, uint chip, uint
>> chip_flags)
>> -#endif
>>   {
>> -       struct i2c *i2c_base;
>> +       struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
>> +       struct i2c *i2c_base = i2c_bus->i2c_base;
>>         u16 status;
>>         int res = 1; /* default = fail */
>>
>> -#ifdef CONFIG_SYS_I2C
>> -       i2c_base = omap24_get_base(adap);
>> -#else
>> -       struct omap24_i2c_bus *i2c_bus;
>> -
>> -       i2c_bus = dev_get_priv(adap);
>> -       i2c_base = i2c_bus->i2c_base;
>> -#endif
>> -
>>         if (chip == readw(&i2c_base->oa))
>>                 return res;
>>
>> @@ -407,26 +468,16 @@ static int omap24_i2c_probe(struct udevice *adap,
>> uint chip, uint chip_flags)
>>                  * silent exit is desired upon unconfigured bus, remove
>> the
>>                  * following 'if' section:
>>                  */
>> -               if (status == I2C_STAT_XRDY) {
>> -#ifdef CONFIG_SYS_I2C
>> -                       printf("i2c_probe: pads on bus %d probably not
>> configured (status=0x%x)\n",
>> -                              adap->hwadapnr, status);
>> -#else
>> +               if (status == I2C_STAT_XRDY)
>>                         printf("i2c_probe: pads on bus %d probably not
>> configured (status=0x%x)\n",
>>                                i2c_bus->bus_num, status);
>> -#endif
>> -               }
>>                 goto pr_exit;
>>         }
>>
>>         /* Check for ACK (!NAK) */
>>         if (!(status & I2C_STAT_NACK)) {
>>                 res = 0;                                /* Device found */
>> -#ifdef CONFIG_SYS_I2C
>> -               udelay(adap->waitdelay);/* Required by AM335X in SPL */
>> -#else
>>                 udelay(i2c_bus->waitdelay);
>> -#endif
>>                 /* Abort transfer (force idle state) */
>>                 writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /*
>> Reset */
>>                 udelay(1000);
>> @@ -452,26 +503,14 @@ pr_exit:
>>    *           or that do not need a register address at all (such as
>> some clock
>>    *           distributors).
>>    */
>> -#ifdef CONFIG_SYS_I2C
>> -static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint
>> addr,
>> -                          int alen, uchar *buffer, int len)
>> -#else
>>   static int omap24_i2c_read(struct udevice *adap, uchar chip, uint addr,
>>                            int alen, uchar *buffer, int len)
>> -#endif
>>   {
>> -       struct i2c *i2c_base;
>> +       struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
>> +       struct i2c *i2c_base = i2c_bus->i2c_base;
>>         int i2c_error = 0;
>>         u16 status;
>>
>> -#ifdef CONFIG_SYS_I2C
>> -       i2c_base = omap24_get_base(adap);
>> -#else
>> -       struct omap24_i2c_bus *i2c_bus;
>> -
>> -       i2c_bus = dev_get_priv(adap);
>> -       i2c_base = i2c_bus->i2c_base;
>> -#endif
>>         if (alen < 0) {
>>                 puts("I2C read: addr len < 0\n");
>>                 return 1;
>> @@ -521,13 +560,8 @@ static int omap24_i2c_read(struct udevice *adap,
>> uchar chip, uint addr,
>>                         /* Try to identify bus that is not padconf'd for
>> I2C */
>>                         if (status == I2C_STAT_XRDY) {
>>                                 i2c_error = 2;
>> -#ifdef CONFIG_SYS_I2C
>> -                               printf("i2c_read (addr phase): pads on
>> bus %d probably not configured (status=0x%x)\n",
>> -                                      adap->hwadapnr, status);
>> -#else
>>                                 printf("i2c_read (addr phase): pads on
>> bus %d probably not configured (status=0x%x)\n",
>>                                        i2c_bus->bus_num, status);
>> -#endif
>>                                 goto rd_exit;
>>                         }
>>                         if (status == 0 || (status & I2C_STAT_NACK)) {
>> @@ -570,13 +604,8 @@ static int omap24_i2c_read(struct udevice *adap,
>> uchar chip, uint addr,
>>                  */
>>                 if (status == I2C_STAT_XRDY) {
>>                         i2c_error = 2;
>> -#ifdef CONFIG_SYS_I2C
>> -                       printf("i2c_read (data phase): pads on bus %d
>> probably not configured (status=0x%x)\n",
>> -                              adap->hwadapnr, status);
>> -#else
>>                         printf("i2c_read (data phase): pads on bus %d
>> probably not configured (status=0x%x)\n",
>>                                i2c_bus->bus_num, status);
>> -#endif
>>                         goto rd_exit;
>>                 }
>>                 if (status == 0 || (status & I2C_STAT_NACK)) {
>> @@ -600,29 +629,16 @@ rd_exit:
>>   }
>>
>>   /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
>> -#ifdef CONFIG_SYS_I2C
>> -static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint
>> addr,
>> -                           int alen, uchar *buffer, int len)
>> -#else
>>   static int omap24_i2c_write(struct udevice *adap, uchar chip, uint addr,
>>                             int alen, uchar *buffer, int len)
>> -#endif
>>   {
>> -       struct i2c *i2c_base;
>> +       struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
>> +       struct i2c *i2c_base = i2c_bus->i2c_base;
>>         int i;
>>         u16 status;
>>         int i2c_error = 0;
>>         int timeout = I2C_TIMEOUT;
>>
>> -#ifdef CONFIG_SYS_I2C
>> -       i2c_base = omap24_get_base(adap);
>> -#else
>> -       struct omap24_i2c_bus *i2c_bus;
>> -
>> -       i2c_bus = dev_get_priv(adap);
>> -       i2c_base = i2c_bus->i2c_base;
>> -#endif
>> -
>>         if (alen < 0) {
>>                 puts("I2C write: addr len < 0\n");
>>                 return 1;
>> @@ -667,13 +683,8 @@ static int omap24_i2c_write(struct udevice *adap,
>> uchar chip, uint addr,
>>                 /* Try to identify bus that is not padconf'd for I2C */
>>                 if (status == I2C_STAT_XRDY) {
>>                         i2c_error = 2;
>> -#ifdef CONFIG_SYS_I2C
>> -                       printf("i2c_write: pads on bus %d probably not
>> configured (status=0x%x)\n",
>> -                              adap->hwadapnr, status);
>> -#else
>>                         printf("i2c_write: pads on bus %d probably not
>> configured (status=0x%x)\n",
>>                                i2c_bus->bus_num, status);
>> -#endif
>>                         goto wr_exit;
>>                 }
>>                 if (status == 0 || (status & I2C_STAT_NACK)) {
>> @@ -732,25 +743,13 @@ wr_exit:
>>    * Wait for the bus to be free by checking the Bus Busy (BB)
>>    * bit to become clear
>>    */
>> -#ifdef CONFIG_SYS_I2C
>> -static int wait_for_bb(struct i2c_adapter *adap)
>> -#else
>>   static int wait_for_bb(struct udevice *adap)
>> -#endif
>>   {
>> -       struct i2c *i2c_base;
>> +       struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
>> +       struct i2c *i2c_base = i2c_bus->i2c_base;
>>         int timeout = I2C_TIMEOUT;
>>         u16 stat;
>>
>> -#ifdef CONFIG_SYS_I2C
>> -       i2c_base = omap24_get_base(adap);
>> -#else
>> -       struct omap24_i2c_bus *i2c_bus;
>> -
>> -       i2c_bus = dev_get_priv(adap);
>> -       i2c_base = i2c_bus->i2c_base;
>> -#endif
>> -
>>         writew(0xFFFF, &i2c_base->stat);        /* clear current
>> interrupts...*/
>>   #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
>>         while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) &&
>> timeout--) {
>> @@ -760,11 +759,7 @@ static int wait_for_bb(struct udevice *adap)
>>                 I2C_STAT_BB) && timeout--) {
>>   #endif
>>                 writew(stat, &i2c_base->stat);
>> -#ifdef CONFIG_SYS_I2C
>> -               udelay(adap->waitdelay);
>> -#else
>>                 udelay(i2c_bus->waitdelay);
>> -#endif
>>         }
>>
>>         if (timeout <= 0) {
>> @@ -780,31 +775,15 @@ static int wait_for_bb(struct udevice *adap)
>>    * Wait for the I2C controller to complete current action
>>    * and update status
>>    */
>> -#ifdef CONFIG_SYS_I2C
>> -static u16 wait_for_event(struct i2c_adapter *adap)
>> -#else
>>   static u16 wait_for_event(struct udevice *adap)
>> -#endif
>>   {
>> -       struct i2c *i2c_base;
>> +       struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
>> +       struct i2c *i2c_base = i2c_bus->i2c_base;
>>         u16 status;
>>         int timeout = I2C_TIMEOUT;
>>
>> -#ifdef CONFIG_SYS_I2C
>> -       i2c_base = omap24_get_base(adap);
>> -#else
>> -       struct omap24_i2c_bus *i2c_bus;
>> -
>> -       i2c_bus = dev_get_priv(adap);
>> -       i2c_base = i2c_bus->i2c_base;
>> -#endif
>> -
>>         do {
>> -#ifdef CONFIG_SYS_I2C
>> -               udelay(adap->waitdelay);
>> -#else
>>                 udelay(i2c_bus->waitdelay);
>> -#endif
>>   #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
>>                 status = readw(&i2c_base->stat);
>>   #else
>> @@ -823,13 +802,8 @@ static u16 wait_for_event(struct udevice *adap)
>>                  * If status is still 0 here, probably the bus pads have
>>                  * not been configured for I2C, and/or pull-ups are
>> missing.
>>                  */
>> -#ifdef CONFIG_SYS_I2C
>> -               printf("Check if pads/pull-ups of bus %d are properly
>> configured\n",
>> -                      adap->hwadapnr);
>> -#else
>>                 printf("Check if pads/pull-ups of bus %d are properly
>> configured\n",
>>                        i2c_bus->bus_num);
>> -#endif
>>                 writew(0xFFFF, &i2c_base->stat);
>>                 status = 0;
>>         }
>> @@ -837,100 +811,6 @@ static u16 wait_for_event(struct udevice *adap)
>>         return status;
>>   }
>>
>> -#ifdef CONFIG_SYS_I2C
>> -static struct i2c *omap24_get_base(struct i2c_adapter *adap)
>> -{
>> -       switch (adap->hwadapnr) {
>> -       case 0:
>> -               return (struct i2c *)I2C_BASE1;
>> -               break;
>> -       case 1:
>> -               return (struct i2c *)I2C_BASE2;
>> -               break;
>> -#if (I2C_BUS_MAX > 2)
>> -       case 2:
>> -               return (struct i2c *)I2C_BASE3;
>> -               break;
>> -#if (I2C_BUS_MAX > 3)
>> -       case 3:
>> -               return (struct i2c *)I2C_BASE4;
>> -               break;
>> -#if (I2C_BUS_MAX > 4)
>> -       case 4:
>> -               return (struct i2c *)I2C_BASE5;
>> -               break;
>> -#endif
>> -#endif
>> -#endif
>> -       default:
>> -               printf("wrong hwadapnr: %d\n", adap->hwadapnr);
>> -               break;
>> -       }
>> -       return NULL;
>> -}
>> -
>> -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
>> -#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
>> -#endif
>> -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
>> -#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
>> -#endif
>> -
>> -U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
>> -                        omap24_i2c_read, omap24_i2c_write,
>> omap24_i2c_setspeed,
>> -                        CONFIG_SYS_OMAP24_I2C_SPEED,
>> -                        CONFIG_SYS_OMAP24_I2C_SLAVE,
>> -                        0)
>> -U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
>> -                        omap24_i2c_read, omap24_i2c_write,
>> omap24_i2c_setspeed,
>> -                        CONFIG_SYS_OMAP24_I2C_SPEED1,
>> -                        CONFIG_SYS_OMAP24_I2C_SLAVE1,
>> -                        1)
>> -#if (I2C_BUS_MAX > 2)
>> -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
>> -#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
>> -#endif
>> -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
>> -#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
>> -#endif
>> -
>> -U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
>> -                        omap24_i2c_read, omap24_i2c_write, NULL,
>> -                        CONFIG_SYS_OMAP24_I2C_SPEED2,
>> -                        CONFIG_SYS_OMAP24_I2C_SLAVE2,
>> -                        2)
>> -#if (I2C_BUS_MAX > 3)
>> -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
>> -#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
>> -#endif
>> -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
>> -#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
>> -#endif
>> -
>> -U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
>> -                        omap24_i2c_read, omap24_i2c_write, NULL,
>> -                        CONFIG_SYS_OMAP24_I2C_SPEED3,
>> -                        CONFIG_SYS_OMAP24_I2C_SLAVE3,
>> -                        3)
>> -#if (I2C_BUS_MAX > 4)
>> -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
>> -#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
>> -#endif
>> -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
>> -#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
>> -#endif
>> -
>> -U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
>> -                        omap24_i2c_read, omap24_i2c_write, NULL,
>> -                        CONFIG_SYS_OMAP24_I2C_SPEED4,
>> -                        CONFIG_SYS_OMAP24_I2C_SLAVE4,
>> -                        4)
>> -#endif
>> -#endif
>> -#endif
>> -#endif
>> -
>> -#ifdef CONFIG_DM_I2C
>>   static int omap24_i2c_xfer(struct udevice *adap, struct i2c_msg *msg,
>>                            int nmsgs)
>>   {
>> @@ -996,4 +876,3 @@ U_BOOT_DRIVER(omap_i2c) = {
>>         .priv_auto_alloc_size = sizeof(struct omap24_i2c_bus),
>>         .ops    = &omap24_i2c_ops,
>>   };
>> -#endif
>> diff --git a/drivers/i2c/omap24xx_i2c.h b/drivers/i2c/omap24xx_i2c.h
>> deleted file mode 100644
>> index 3dae295..0000000
>> --- a/drivers/i2c/omap24xx_i2c.h
>> +++ /dev/null
>> @@ -1,154 +0,0 @@
>> -/*
>> - * (C) Copyright 2004-2010
>> - * Texas Instruments, <www.ti.com>
>> - *
>> - * SPDX-License-Identifier:    GPL-2.0+
>> - */
>> -#ifndef _OMAP2PLUS_I2C_H_
>> -#define _OMAP2PLUS_I2C_H_
>> -
>> -/* I2C masks */
>> -
>> -/* I2C Interrupt Enable Register (I2C_IE): */
>> -#define I2C_IE_GC_IE   (1 << 5)
>> -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable
>> */
>> -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
>> -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt
>> enable */
>> -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
>> -#define I2C_IE_AL_IE   (1 << 0) /* Arbitration lost interrupt enable */
>> -
>> -/* I2C Status Register (I2C_STAT): */
>> -
>> -#define I2C_STAT_SBD   (1 << 15) /* Single byte data */
>> -#define I2C_STAT_BB    (1 << 12) /* Bus busy */
>> -#define I2C_STAT_ROVR  (1 << 11) /* Receive overrun */
>> -#define I2C_STAT_XUDF  (1 << 10) /* Transmit underflow */
>> -#define I2C_STAT_AAS   (1 << 9)  /* Address as slave */
>> -#define I2C_STAT_GC    (1 << 5)
>> -#define I2C_STAT_XRDY  (1 << 4)  /* Transmit data ready */
>> -#define I2C_STAT_RRDY  (1 << 3)  /* Receive data ready */
>> -#define I2C_STAT_ARDY  (1 << 2)  /* Register access ready */
>> -#define I2C_STAT_NACK  (1 << 1)  /* No acknowledgment interrupt enable */
>> -#define I2C_STAT_AL    (1 << 0)  /* Arbitration lost interrupt enable */
>> -
>> -/* I2C Interrupt Code Register (I2C_INTCODE): */
>> -
>> -#define I2C_INTCODE_MASK       7
>> -#define I2C_INTCODE_NONE       0
>> -#define I2C_INTCODE_AL         1       /* Arbitration lost */
>> -#define I2C_INTCODE_NAK                2       /* No
>> acknowledgement/general call */
>> -#define I2C_INTCODE_ARDY       3       /* Register access ready */
>> -#define I2C_INTCODE_RRDY       4       /* Rcv data ready */
>> -#define I2C_INTCODE_XRDY       5       /* Xmit data ready */
>> -
>> -/* I2C Buffer Configuration Register (I2C_BUF): */
>> -
>> -#define I2C_BUF_RDMA_EN                (1 << 15) /* Receive DMA channel
>> enable */
>> -#define I2C_BUF_XDMA_EN                (1 << 7)  /* Transmit DMA channel
>> enable */
>> -
>> -/* I2C Configuration Register (I2C_CON): */
>> -
>> -#define I2C_CON_EN     (1 << 15)  /* I2C module enable */
>> -#define I2C_CON_BE     (1 << 14)  /* Big endian mode */
>> -#define I2C_CON_STB    (1 << 11)  /* Start byte mode (master mode only)
>> */
>> -#define I2C_CON_MST    (1 << 10)  /* Master/slave mode */
>> -#define I2C_CON_TRX    (1 << 9)   /* Transmitter/receiver mode */
>> -                                  /* (master mode only) */
>> -#define I2C_CON_XA     (1 << 8)   /* Expand address */
>> -#define I2C_CON_STP    (1 << 1)   /* Stop condition (master mode only) */
>> -#define I2C_CON_STT    (1 << 0)   /* Start condition (master mode only)
>> */
>> -
>> -/* I2C System Test Register (I2C_SYSTEST): */
>> -
>> -#define I2C_SYSTEST_ST_EN      (1 << 15) /* System test enable */
>> -#define I2C_SYSTEST_FREE       (1 << 14) /* Free running mode, on
>> brkpoint) */
>> -#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
>> -#define I2C_SYSTEST_TMODE_SHIFT        (12)      /* Test mode select */
>> -#define I2C_SYSTEST_SCL_I      (1 << 3)  /* SCL line sense input value */
>> -#define I2C_SYSTEST_SCL_O      (1 << 2)  /* SCL line drive output value
>> */
>> -#define I2C_SYSTEST_SDA_I      (1 << 1)  /* SDA line sense input value */
>> -#define I2C_SYSTEST_SDA_O      (1 << 0)  /* SDA line drive output value
>> */
>> -
>> -/* I2C System Status Register (I2C_SYSS): */
>> -
>> -#define I2C_SYSS_RDONE          (1 << 0)  /* Internel reset monitoring */
>> -
>> -#define I2C_SCLL_SCLL          0
>> -#define I2C_SCLL_SCLL_M                0xFF
>> -#define I2C_SCLL_HSSCLL                8
>> -#define I2C_SCLH_HSSCLL_M      0xFF
>> -#define I2C_SCLH_SCLH          0
>> -#define I2C_SCLH_SCLH_M                0xFF
>> -#define I2C_SCLH_HSSCLH                8
>> -#define I2C_SCLH_HSSCLH_M      0xFF
>> -
>> -#define OMAP_I2C_STANDARD      100000
>> -#define OMAP_I2C_FAST_MODE     400000
>> -#define OMAP_I2C_HIGH_SPEED    3400000
>> -
>> -#define SYSTEM_CLOCK_12                12000000
>> -#define SYSTEM_CLOCK_13                13000000
>> -#define SYSTEM_CLOCK_192       19200000
>> -#define SYSTEM_CLOCK_96                96000000
>> -
>> -/* Use the reference value of 96MHz if not explicitly set by the board */
>> -#ifndef I2C_IP_CLK
>> -#define I2C_IP_CLK             SYSTEM_CLOCK_96
>> -#endif
>> -
>> -/*
>> - * The reference minimum clock for high speed is 19.2MHz.
>> - * The linux 2.6.30 kernel uses this value.
>> - * The reference minimum clock for fast mode is 9.6MHz
>> - * The reference minimum clock for standard mode is 4MHz
>> - * In TRM, the value of 12MHz is used.
>> - */
>> -#ifndef I2C_INTERNAL_SAMPLING_CLK
>> -#define I2C_INTERNAL_SAMPLING_CLK      19200000
>> -#endif
>> -
>> -/*
>> - * The equation for the low and high time is
>> - * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
>> - * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
>> - *
>> - * If the duty cycle is 50%
>> - *
>> - * tlow = scll + scll_trim = sampling clock / (2 * speed)
>> - * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
>> - *
>> - * In TRM
>> - * scll_trim = 7
>> - * sclh_trim = 5
>> - *
>> - * The linux 2.6.30 kernel uses
>> - * scll_trim = 6
>> - * sclh_trim = 6
>> - *
>> - * These are the trim values for standard and fast speed
>> - */
>> -#ifndef I2C_FASTSPEED_SCLL_TRIM
>> -#define I2C_FASTSPEED_SCLL_TRIM                6
>> -#endif
>> -#ifndef I2C_FASTSPEED_SCLH_TRIM
>> -#define I2C_FASTSPEED_SCLH_TRIM                6
>> -#endif
>> -
>> -/* These are the trim values for high speed */
>> -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
>> -#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM      I2C_FASTSPEED_SCLL_TRIM
>> -#endif
>> -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
>> -#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM      I2C_FASTSPEED_SCLH_TRIM
>> -#endif
>> -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
>> -#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM      I2C_FASTSPEED_SCLL_TRIM
>> -#endif
>> -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
>> -#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM      I2C_FASTSPEED_SCLH_TRIM
>> -#endif
>> -
>> -#define I2C_PSC_MAX            0x0f
>> -#define I2C_PSC_MIN            0x00
>> -
>> -#endif /* _OMAP24XX_I2C_H_ */
>>
>>
> --
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>

[U-Boot] [PATCH 5/5] i2c: omap24xx: Convert fully to DM_I2C

[Heiko Schocher]

Hello Christophe,

Am 18.01.2016 um 22:22 schrieb Christophe Ricard:
> Hi Heiko,
>
> I was expecting such kind of feedback on this one :).
> I had myself to hack around between the MLO and the u-boot.img to get it working.
>
> For omap, i think twlxxxx drivers are kind of the main item to convert.
>
> Would you accept to take the first 4 patches until the board are fully ready for the 5th one ?

Yes. If they have no checkpatch errors and apply clean ;-)

I try to look at it, today.

bye,
Heiko
>
> Best Regards
> Christophe
>
> 2016-01-18 7:04 GMT+01:00 Heiko Schocher <hs at denx.de <mailto:hs@denx.de>>:
>
>     Hello Christophe,
>
>     Am 17.01.2016 um 12:09 schrieb Christophe Ricard:
>
>         For several reasons:
>         - code clarity
>         - DM trends in u-boot
>         ...
>
>         It is better to make omap24xx_i2c driver 100% DM_I2C based.
>
>         Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com
>         <mailto:christophe-h.ricard@st.com>>
>         ---
>
>            drivers/i2c/omap24xx_i2c.c | 447 +++++++++++++++++----------------------------
>            drivers/i2c/omap24xx_i2c.h | 154 ----------------
>            2 files changed, 163 insertions(+), 438 deletions(-)
>            delete mode 100644 drivers/i2c/omap24xx_i2c.h
>
>
>     Full Ack .. but does this patch does not breeak boards, which use this
>     driver, and are not converted to DM ? I think, we could remove the
>     old style only, if all boards are converted ...
>
>     bye,
>     Heiko
>
>
>         diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
>         index 774edaf..baccb89 100644
>         --- a/drivers/i2c/omap24xx_i2c.c
>         +++ b/drivers/i2c/omap24xx_i2c.c
>         @@ -49,31 +49,164 @@
>            #include <asm/io.h>
>            #include <asm/errno.h>
>
>         -#include "omap24xx_i2c.h"
>         -
>
>
>     ?
>
>     Why do you remove the header file, and move all definitions into the
>     c file?
>
>
>            DECLARE_GLOBAL_DATA_PTR;
>
>         +/* I2C masks */
>         +
>         +/* I2C Interrupt Enable Register (I2C_IE): */
>         +#define I2C_IE_GC_IE   (1 << 5)
>         +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
>         +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
>         +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
>         +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
>         +#define I2C_IE_AL_IE   (1 << 0) /* Arbitration lost interrupt enable */
>         +
>         +/* I2C Status Register (I2C_STAT): */
>         +
>         +#define I2C_STAT_SBD   (1 << 15) /* Single byte data */
>         +#define I2C_STAT_BB    (1 << 12) /* Bus busy */
>         +#define I2C_STAT_ROVR  (1 << 11) /* Receive overrun */
>         +#define I2C_STAT_XUDF  (1 << 10) /* Transmit underflow */
>         +#define I2C_STAT_AAS   (1 << 9)  /* Address as slave */
>         +#define I2C_STAT_GC    (1 << 5)
>         +#define I2C_STAT_XRDY  (1 << 4)  /* Transmit data ready */
>         +#define I2C_STAT_RRDY  (1 << 3)  /* Receive data ready */
>         +#define I2C_STAT_ARDY  (1 << 2)  /* Register access ready */
>         +#define I2C_STAT_NACK  (1 << 1)  /* No acknowledgment interrupt enable */
>         +#define I2C_STAT_AL    (1 << 0)  /* Arbitration lost interrupt enable */
>         +
>         +/* I2C Interrupt Code Register (I2C_INTCODE): */
>         +
>         +#define I2C_INTCODE_MASK       7
>         +#define I2C_INTCODE_NONE       0
>         +#define I2C_INTCODE_AL         1       /* Arbitration lost */
>         +#define I2C_INTCODE_NAK                2       /* No acknowledgement/general call */
>         +#define I2C_INTCODE_ARDY       3       /* Register access ready */
>         +#define I2C_INTCODE_RRDY       4       /* Rcv data ready */
>         +#define I2C_INTCODE_XRDY       5       /* Xmit data ready */
>         +
>         +/* I2C Buffer Configuration Register (I2C_BUF): */
>         +
>         +#define I2C_BUF_RDMA_EN                (1 << 15) /* Receive DMA channel enable */
>         +#define I2C_BUF_XDMA_EN                (1 << 7)  /* Transmit DMA channel enable */
>         +
>         +/* I2C Configuration Register (I2C_CON): */
>         +
>         +#define I2C_CON_EN     (1 << 15)  /* I2C module enable */
>         +#define I2C_CON_BE     (1 << 14)  /* Big endian mode */
>         +#define I2C_CON_STB    (1 << 11)  /* Start byte mode (master mode only) */
>         +#define I2C_CON_MST    (1 << 10)  /* Master/slave mode */
>         +#define I2C_CON_TRX    (1 << 9)   /* Transmitter/receiver mode */
>         +                                  /* (master mode only) */
>         +#define I2C_CON_XA     (1 << 8)   /* Expand address */
>         +#define I2C_CON_STP    (1 << 1)   /* Stop condition (master mode only) */
>         +#define I2C_CON_STT    (1 << 0)   /* Start condition (master mode only) */
>         +
>         +/* I2C System Test Register (I2C_SYSTEST): */
>         +
>         +#define I2C_SYSTEST_ST_EN      (1 << 15) /* System test enable */
>         +#define I2C_SYSTEST_FREE       (1 << 14) /* Free running mode, on brkpoint) */
>         +#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
>         +#define I2C_SYSTEST_TMODE_SHIFT        (12)      /* Test mode select */
>         +#define I2C_SYSTEST_SCL_I      (1 << 3)  /* SCL line sense input value */
>         +#define I2C_SYSTEST_SCL_O      (1 << 2)  /* SCL line drive output value */
>         +#define I2C_SYSTEST_SDA_I      (1 << 1)  /* SDA line sense input value */
>         +#define I2C_SYSTEST_SDA_O      (1 << 0)  /* SDA line drive output value */
>         +
>         +/* I2C System Status Register (I2C_SYSS): */
>         +
>         +#define I2C_SYSS_RDONE          (1 << 0)  /* Internel reset monitoring */
>         +
>         +#define I2C_SCLL_SCLL          0
>         +#define I2C_SCLL_SCLL_M                0xFF
>         +#define I2C_SCLL_HSSCLL                8
>         +#define I2C_SCLH_HSSCLL_M      0xFF
>         +#define I2C_SCLH_SCLH          0
>         +#define I2C_SCLH_SCLH_M                0xFF
>         +#define I2C_SCLH_HSSCLH                8
>         +#define I2C_SCLH_HSSCLH_M      0xFF
>         +
>         +#define OMAP_I2C_STANDARD      100000
>         +#define OMAP_I2C_FAST_MODE     400000
>         +#define OMAP_I2C_HIGH_SPEED    3400000
>         +
>         +#define SYSTEM_CLOCK_12                12000000
>         +#define SYSTEM_CLOCK_13                13000000
>         +#define SYSTEM_CLOCK_192       19200000
>         +#define SYSTEM_CLOCK_96                96000000
>         +
>         +/* Use the reference value of 96MHz if not explicitly set by the board */
>         +#ifndef I2C_IP_CLK
>         +#define I2C_IP_CLK             SYSTEM_CLOCK_96
>         +#endif
>         +
>         +/*
>         + * The reference minimum clock for high speed is 19.2MHz.
>         + * The linux 2.6.30 kernel uses this value.
>         + * The reference minimum clock for fast mode is 9.6MHz
>         + * The reference minimum clock for standard mode is 4MHz
>         + * In TRM, the value of 12MHz is used.
>         + */
>         +#ifndef I2C_INTERNAL_SAMPLING_CLK
>         +#define I2C_INTERNAL_SAMPLING_CLK      19200000
>         +#endif
>         +
>         +/*
>         + * The equation for the low and high time is
>         + * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
>         + * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
>         + *
>         + * If the duty cycle is 50%
>         + *
>         + * tlow = scll + scll_trim = sampling clock / (2 * speed)
>         + * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
>         + *
>         + * In TRM
>         + * scll_trim = 7
>         + * sclh_trim = 5
>         + *
>         + * The linux 2.6.30 kernel uses
>         + * scll_trim = 6
>         + * sclh_trim = 6
>         + *
>         + * These are the trim values for standard and fast speed
>         + */
>         +#ifndef I2C_FASTSPEED_SCLL_TRIM
>         +#define I2C_FASTSPEED_SCLL_TRIM                6
>         +#endif
>         +#ifndef I2C_FASTSPEED_SCLH_TRIM
>         +#define I2C_FASTSPEED_SCLH_TRIM                6
>         +#endif
>         +
>         +/* These are the trim values for high speed */
>         +#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
>         +#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM      I2C_FASTSPEED_SCLL_TRIM
>         +#endif
>         +#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
>         +#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM      I2C_FASTSPEED_SCLH_TRIM
>         +#endif
>         +#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
>         +#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM      I2C_FASTSPEED_SCLL_TRIM
>         +#endif
>         +#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
>         +#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM      I2C_FASTSPEED_SCLH_TRIM
>         +#endif
>         +
>         +#define I2C_PSC_MAX            0x0f
>         +#define I2C_PSC_MIN            0x00
>         +
>            #define I2C_TIMEOUT   1000
>
>         -#ifdef CONFIG_DM_I2C
>            struct omap24_i2c_bus {
>                  int bus_num;
>                  int waitdelay;
>                  unsigned clock_frequency;
>                  struct i2c *i2c_base;
>            };
>         -#endif
>
>         -#ifdef CONFIG_SYS_I2C
>         -static int wait_for_bb(struct i2c_adapter *adap);
>         -static struct i2c *omap24_get_base(struct i2c_adapter *adap);
>         -static u16 wait_for_event(struct i2c_adapter *adap);
>         -static void flush_fifo(struct i2c_adapter *adap);
>         -#else
>            static int wait_for_bb(struct udevice *dev);
>            static u16 wait_for_event(struct udevice *dev);
>            static void flush_fifo(struct udevice *dev);
>         -#endif
>
>            static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
>            {
>         @@ -109,26 +242,14 @@ static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
>                  return -1;
>            }
>
>         -#ifdef CONFIG_SYS_I2C
>         -static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
>         -#else
>            static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
>         -#endif
>            {
>         -       struct i2c *i2c_base;
>         +       struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
>         +       struct i2c *i2c_base = i2c_bus->i2c_base;
>                  int psc, fsscll = 0, fssclh = 0;
>                  int hsscll = 0, hssclh = 0;
>                  u32 scll = 0, sclh = 0;
>
>         -#ifdef CONFIG_SYS_I2C
>         -       i2c_base = omap24_get_base(adap);
>         -#else
>         -       struct omap24_i2c_bus *i2c_bus;
>         -
>         -       i2c_bus = dev_get_priv(adap);
>         -       i2c_base = i2c_bus->i2c_base;
>         -#endif
>         -
>                  if (speed > 400000) {
>                          unsigned long scl;
>
>         @@ -166,13 +287,8 @@ static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
>                          scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
>                          sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
>
>         -#ifdef CONFIG_SYS_I2C
>         -               adap->speed     = speed;
>         -               adap->waitdelay = (10000000 / speed) * 8; /* wait for 20 clkperiods */
>         -#else
>                          i2c_bus->clock_frequency = speed;
>                          i2c_bus->waitdelay = (10000000 / speed) * 8; /* wait for 20 clkperiods */
>         -#endif
>                  } else {
>                          /* Standard and fast speed */
>                          psc = omap24_i2c_findpsc(&scll, &sclh, speed);
>         @@ -181,13 +297,8 @@ static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
>                                  return -1;
>                          }
>
>         -#ifdef CONFIG_SYS_I2C
>         -               adap->speed     = speed;
>         -               adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
>         -#else
>                          i2c_bus->clock_frequency = speed;
>                          i2c_bus->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
>         -#endif
>                  }
>
>                  writew(0, &i2c_base->con);
>         @@ -200,26 +311,14 @@ static int omap24_i2c_setspeed(struct udevice *adap, unsigned int speed)
>                  return 0;
>            }
>
>         -#ifdef CONFIG_SYS_I2C
>         -static void omap24_i2c_deblock(struct i2c_adapter *adap)
>         -#else
>            static int omap24_i2c_deblock(struct udevice *adap)
>         -#endif
>            {
>         -       struct i2c *i2c_base;
>         +       struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
>         +       struct i2c *i2c_base = i2c_bus->i2c_base;
>                  int i;
>                  u16 systest;
>                  u16 orgsystest;
>
>         -#ifdef CONFIG_SYS_I2C
>         -       i2c_base = omap24_get_base(adap);
>         -#else
>         -       struct omap24_i2c_bus *i2c_bus;
>         -
>         -       i2c_bus = dev_get_priv(adap);
>         -       i2c_base = i2c_bus->i2c_base;
>         -#endif
>         -
>                  /* set test mode ST_EN = 1 */
>                  orgsystest = readw(&i2c_base->systest);
>                  systest = orgsystest;
>         @@ -258,30 +357,16 @@ static int omap24_i2c_deblock(struct udevice *adap)
>                  /* restore original mode */
>                  writew(orgsystest, &i2c_base->systest);
>
>         -#ifdef CONFIG_DM_I2C
>                  return 0;
>         -#endif
>            }
>
>         -#ifdef CONFIG_SYS_I2C
>         -static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
>         -#else
>            static void omap24_i2c_init(struct udevice *adap, int speed, int slaveadd)
>         -#endif
>            {
>         -       struct i2c *i2c_base;
>         +       struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
>         +       struct i2c *i2c_base = i2c_bus->i2c_base;
>                  int timeout = I2C_TIMEOUT;
>                  int deblock = 1;
>
>         -#ifdef CONFIG_SYS_I2C
>         -       i2c_base = omap24_get_base(adap);
>         -#else
>         -       struct omap24_i2c_bus *i2c_bus;
>         -
>         -       i2c_bus = dev_get_priv(adap);
>         -       i2c_base = i2c_bus->i2c_base;
>         -#endif
>         -
>            retry:
>                  if (readw(&i2c_base->con) & I2C_CON_EN) {
>                          writew(0, &i2c_base->con);
>         @@ -329,24 +414,12 @@ retry:
>                          }
>            }
>
>         -#ifdef CONFIG_SYS_I2C
>         -static void flush_fifo(struct i2c_adapter *adap)
>         -#else
>            static void flush_fifo(struct udevice *adap)
>         -#endif
>            {
>         -       struct i2c *i2c_base;
>         +       struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
>         +       struct i2c *i2c_base = i2c_bus->i2c_base;
>                  u16 stat;
>
>         -#ifdef CONFIG_SYS_I2C
>         -       i2c_base = omap24_get_base(adap);
>         -#else
>         -       struct omap24_i2c_bus *i2c_bus;
>         -
>         -       i2c_bus = dev_get_priv(adap);
>         -       i2c_base = i2c_bus->i2c_base;
>         -#endif
>         -
>                  /*
>                   * note: if you try and read data when its not there or ready
>                   * you get a bus error
>         @@ -366,25 +439,13 @@ static void flush_fifo(struct udevice *adap)
>             * i2c_probe: Use write access. Allows to identify addresses that are
>             *            write-only (like the config register of dual-port EEPROMs)
>             */
>         -#ifdef CONFIG_SYS_I2C
>         -static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
>         -#else
>            static int omap24_i2c_probe(struct udevice *adap, uint chip, uint chip_flags)
>         -#endif
>            {
>         -       struct i2c *i2c_base;
>         +       struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
>         +       struct i2c *i2c_base = i2c_bus->i2c_base;
>                  u16 status;
>                  int res = 1; /* default = fail */
>
>         -#ifdef CONFIG_SYS_I2C
>         -       i2c_base = omap24_get_base(adap);
>         -#else
>         -       struct omap24_i2c_bus *i2c_bus;
>         -
>         -       i2c_bus = dev_get_priv(adap);
>         -       i2c_base = i2c_bus->i2c_base;
>         -#endif
>         -
>                  if (chip == readw(&i2c_base->oa))
>                          return res;
>
>         @@ -407,26 +468,16 @@ static int omap24_i2c_probe(struct udevice *adap, uint chip, uint
>         chip_flags)
>                           * silent exit is desired upon unconfigured bus, remove the
>                           * following 'if' section:
>                           */
>         -               if (status == I2C_STAT_XRDY) {
>         -#ifdef CONFIG_SYS_I2C
>         -                       printf("i2c_probe: pads on bus %d probably not configured
>         (status=0x%x)\n",
>         -                              adap->hwadapnr, status);
>         -#else
>         +               if (status == I2C_STAT_XRDY)
>                                  printf("i2c_probe: pads on bus %d probably not configured
>         (status=0x%x)\n",
>                                         i2c_bus->bus_num, status);
>         -#endif
>         -               }
>                          goto pr_exit;
>                  }
>
>                  /* Check for ACK (!NAK) */
>                  if (!(status & I2C_STAT_NACK)) {
>                          res = 0;                                /* Device found */
>         -#ifdef CONFIG_SYS_I2C
>         -               udelay(adap->waitdelay);/* Required by AM335X in SPL */
>         -#else
>                          udelay(i2c_bus->waitdelay);
>         -#endif
>                          /* Abort transfer (force idle state) */
>                          writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
>                          udelay(1000);
>         @@ -452,26 +503,14 @@ pr_exit:
>             *           or that do not need a register address at all (such as some clock
>             *           distributors).
>             */
>         -#ifdef CONFIG_SYS_I2C
>         -static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
>         -                          int alen, uchar *buffer, int len)
>         -#else
>            static int omap24_i2c_read(struct udevice *adap, uchar chip, uint addr,
>                                     int alen, uchar *buffer, int len)
>         -#endif
>            {
>         -       struct i2c *i2c_base;
>         +       struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
>         +       struct i2c *i2c_base = i2c_bus->i2c_base;
>                  int i2c_error = 0;
>                  u16 status;
>
>         -#ifdef CONFIG_SYS_I2C
>         -       i2c_base = omap24_get_base(adap);
>         -#else
>         -       struct omap24_i2c_bus *i2c_bus;
>         -
>         -       i2c_bus = dev_get_priv(adap);
>         -       i2c_base = i2c_bus->i2c_base;
>         -#endif
>                  if (alen < 0) {
>                          puts("I2C read: addr len < 0\n");
>                          return 1;
>         @@ -521,13 +560,8 @@ static int omap24_i2c_read(struct udevice *adap, uchar chip, uint addr,
>                                  /* Try to identify bus that is not padconf'd for I2C */
>                                  if (status == I2C_STAT_XRDY) {
>                                          i2c_error = 2;
>         -#ifdef CONFIG_SYS_I2C
>         -                               printf("i2c_read (addr phase): pads on bus %d probably not
>         configured (status=0x%x)\n",
>         -                                      adap->hwadapnr, status);
>         -#else
>                                          printf("i2c_read (addr phase): pads on bus %d probably not
>         configured (status=0x%x)\n",
>                                                 i2c_bus->bus_num, status);
>         -#endif
>                                          goto rd_exit;
>                                  }
>                                  if (status == 0 || (status & I2C_STAT_NACK)) {
>         @@ -570,13 +604,8 @@ static int omap24_i2c_read(struct udevice *adap, uchar chip, uint addr,
>                           */
>                          if (status == I2C_STAT_XRDY) {
>                                  i2c_error = 2;
>         -#ifdef CONFIG_SYS_I2C
>         -                       printf("i2c_read (data phase): pads on bus %d probably not
>         configured (status=0x%x)\n",
>         -                              adap->hwadapnr, status);
>         -#else
>                                  printf("i2c_read (data phase): pads on bus %d probably not
>         configured (status=0x%x)\n",
>                                         i2c_bus->bus_num, status);
>         -#endif
>                                  goto rd_exit;
>                          }
>                          if (status == 0 || (status & I2C_STAT_NACK)) {
>         @@ -600,29 +629,16 @@ rd_exit:
>            }
>
>            /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
>         -#ifdef CONFIG_SYS_I2C
>         -static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
>         -                           int alen, uchar *buffer, int len)
>         -#else
>            static int omap24_i2c_write(struct udevice *adap, uchar chip, uint addr,
>                                      int alen, uchar *buffer, int len)
>         -#endif
>            {
>         -       struct i2c *i2c_base;
>         +       struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
>         +       struct i2c *i2c_base = i2c_bus->i2c_base;
>                  int i;
>                  u16 status;
>                  int i2c_error = 0;
>                  int timeout = I2C_TIMEOUT;
>
>         -#ifdef CONFIG_SYS_I2C
>         -       i2c_base = omap24_get_base(adap);
>         -#else
>         -       struct omap24_i2c_bus *i2c_bus;
>         -
>         -       i2c_bus = dev_get_priv(adap);
>         -       i2c_base = i2c_bus->i2c_base;
>         -#endif
>         -
>                  if (alen < 0) {
>                          puts("I2C write: addr len < 0\n");
>                          return 1;
>         @@ -667,13 +683,8 @@ static int omap24_i2c_write(struct udevice *adap, uchar chip, uint addr,
>                          /* Try to identify bus that is not padconf'd for I2C */
>                          if (status == I2C_STAT_XRDY) {
>                                  i2c_error = 2;
>         -#ifdef CONFIG_SYS_I2C
>         -                       printf("i2c_write: pads on bus %d probably not configured
>         (status=0x%x)\n",
>         -                              adap->hwadapnr, status);
>         -#else
>                                  printf("i2c_write: pads on bus %d probably not configured
>         (status=0x%x)\n",
>                                         i2c_bus->bus_num, status);
>         -#endif
>                                  goto wr_exit;
>                          }
>                          if (status == 0 || (status & I2C_STAT_NACK)) {
>         @@ -732,25 +743,13 @@ wr_exit:
>             * Wait for the bus to be free by checking the Bus Busy (BB)
>             * bit to become clear
>             */
>         -#ifdef CONFIG_SYS_I2C
>         -static int wait_for_bb(struct i2c_adapter *adap)
>         -#else
>            static int wait_for_bb(struct udevice *adap)
>         -#endif
>            {
>         -       struct i2c *i2c_base;
>         +       struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
>         +       struct i2c *i2c_base = i2c_bus->i2c_base;
>                  int timeout = I2C_TIMEOUT;
>                  u16 stat;
>
>         -#ifdef CONFIG_SYS_I2C
>         -       i2c_base = omap24_get_base(adap);
>         -#else
>         -       struct omap24_i2c_bus *i2c_bus;
>         -
>         -       i2c_bus = dev_get_priv(adap);
>         -       i2c_base = i2c_bus->i2c_base;
>         -#endif
>         -
>                  writew(0xFFFF, &i2c_base->stat);        /* clear current interrupts...*/
>            #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
>                  while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
>         @@ -760,11 +759,7 @@ static int wait_for_bb(struct udevice *adap)
>                          I2C_STAT_BB) && timeout--) {
>            #endif
>                          writew(stat, &i2c_base->stat);
>         -#ifdef CONFIG_SYS_I2C
>         -               udelay(adap->waitdelay);
>         -#else
>                          udelay(i2c_bus->waitdelay);
>         -#endif
>                  }
>
>                  if (timeout <= 0) {
>         @@ -780,31 +775,15 @@ static int wait_for_bb(struct udevice *adap)
>             * Wait for the I2C controller to complete current action
>             * and update status
>             */
>         -#ifdef CONFIG_SYS_I2C
>         -static u16 wait_for_event(struct i2c_adapter *adap)
>         -#else
>            static u16 wait_for_event(struct udevice *adap)
>         -#endif
>            {
>         -       struct i2c *i2c_base;
>         +       struct omap24_i2c_bus *i2c_bus = dev_get_priv(adap);
>         +       struct i2c *i2c_base = i2c_bus->i2c_base;
>                  u16 status;
>                  int timeout = I2C_TIMEOUT;
>
>         -#ifdef CONFIG_SYS_I2C
>         -       i2c_base = omap24_get_base(adap);
>         -#else
>         -       struct omap24_i2c_bus *i2c_bus;
>         -
>         -       i2c_bus = dev_get_priv(adap);
>         -       i2c_base = i2c_bus->i2c_base;
>         -#endif
>         -
>                  do {
>         -#ifdef CONFIG_SYS_I2C
>         -               udelay(adap->waitdelay);
>         -#else
>                          udelay(i2c_bus->waitdelay);
>         -#endif
>            #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
>                          status = readw(&i2c_base->stat);
>            #else
>         @@ -823,13 +802,8 @@ static u16 wait_for_event(struct udevice *adap)
>                           * If status is still 0 here, probably the bus pads have
>                           * not been configured for I2C, and/or pull-ups are missing.
>                           */
>         -#ifdef CONFIG_SYS_I2C
>         -               printf("Check if pads/pull-ups of bus %d are properly configured\n",
>         -                      adap->hwadapnr);
>         -#else
>                          printf("Check if pads/pull-ups of bus %d are properly configured\n",
>                                 i2c_bus->bus_num);
>         -#endif
>                          writew(0xFFFF, &i2c_base->stat);
>                          status = 0;
>                  }
>         @@ -837,100 +811,6 @@ static u16 wait_for_event(struct udevice *adap)
>                  return status;
>            }
>
>         -#ifdef CONFIG_SYS_I2C
>         -static struct i2c *omap24_get_base(struct i2c_adapter *adap)
>         -{
>         -       switch (adap->hwadapnr) {
>         -       case 0:
>         -               return (struct i2c *)I2C_BASE1;
>         -               break;
>         -       case 1:
>         -               return (struct i2c *)I2C_BASE2;
>         -               break;
>         -#if (I2C_BUS_MAX > 2)
>         -       case 2:
>         -               return (struct i2c *)I2C_BASE3;
>         -               break;
>         -#if (I2C_BUS_MAX > 3)
>         -       case 3:
>         -               return (struct i2c *)I2C_BASE4;
>         -               break;
>         -#if (I2C_BUS_MAX > 4)
>         -       case 4:
>         -               return (struct i2c *)I2C_BASE5;
>         -               break;
>         -#endif
>         -#endif
>         -#endif
>         -       default:
>         -               printf("wrong hwadapnr: %d\n", adap->hwadapnr);
>         -               break;
>         -       }
>         -       return NULL;
>         -}
>         -
>         -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
>         -#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
>         -#endif
>         -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
>         -#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
>         -#endif
>         -
>         -U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
>         -                        omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
>         -                        CONFIG_SYS_OMAP24_I2C_SPEED,
>         -                        CONFIG_SYS_OMAP24_I2C_SLAVE,
>         -                        0)
>         -U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
>         -                        omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
>         -                        CONFIG_SYS_OMAP24_I2C_SPEED1,
>         -                        CONFIG_SYS_OMAP24_I2C_SLAVE1,
>         -                        1)
>         -#if (I2C_BUS_MAX > 2)
>         -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
>         -#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
>         -#endif
>         -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
>         -#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
>         -#endif
>         -
>         -U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
>         -                        omap24_i2c_read, omap24_i2c_write, NULL,
>         -                        CONFIG_SYS_OMAP24_I2C_SPEED2,
>         -                        CONFIG_SYS_OMAP24_I2C_SLAVE2,
>         -                        2)
>         -#if (I2C_BUS_MAX > 3)
>         -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
>         -#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
>         -#endif
>         -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
>         -#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
>         -#endif
>         -
>         -U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
>         -                        omap24_i2c_read, omap24_i2c_write, NULL,
>         -                        CONFIG_SYS_OMAP24_I2C_SPEED3,
>         -                        CONFIG_SYS_OMAP24_I2C_SLAVE3,
>         -                        3)
>         -#if (I2C_BUS_MAX > 4)
>         -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
>         -#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
>         -#endif
>         -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
>         -#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
>         -#endif
>         -
>         -U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
>         -                        omap24_i2c_read, omap24_i2c_write, NULL,
>         -                        CONFIG_SYS_OMAP24_I2C_SPEED4,
>         -                        CONFIG_SYS_OMAP24_I2C_SLAVE4,
>         -                        4)
>         -#endif
>         -#endif
>         -#endif
>         -#endif
>         -
>         -#ifdef CONFIG_DM_I2C
>            static int omap24_i2c_xfer(struct udevice *adap, struct i2c_msg *msg,
>                                     int nmsgs)
>            {
>         @@ -996,4 +876,3 @@ U_BOOT_DRIVER(omap_i2c) = {
>                  .priv_auto_alloc_size = sizeof(struct omap24_i2c_bus),
>                  .ops    = &omap24_i2c_ops,
>            };
>         -#endif
>         diff --git a/drivers/i2c/omap24xx_i2c.h b/drivers/i2c/omap24xx_i2c.h
>         deleted file mode 100644
>         index 3dae295..0000000
>         --- a/drivers/i2c/omap24xx_i2c.h
>         +++ /dev/null
>         @@ -1,154 +0,0 @@
>         -/*
>         - * (C) Copyright 2004-2010
>         - * Texas Instruments, <www.ti.com <http://www.ti.com>>
>         - *
>         - * SPDX-License-Identifier:    GPL-2.0+
>         - */
>         -#ifndef _OMAP2PLUS_I2C_H_
>         -#define _OMAP2PLUS_I2C_H_
>         -
>         -/* I2C masks */
>         -
>         -/* I2C Interrupt Enable Register (I2C_IE): */
>         -#define I2C_IE_GC_IE   (1 << 5)
>         -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
>         -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
>         -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
>         -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
>         -#define I2C_IE_AL_IE   (1 << 0) /* Arbitration lost interrupt enable */
>         -
>         -/* I2C Status Register (I2C_STAT): */
>         -
>         -#define I2C_STAT_SBD   (1 << 15) /* Single byte data */
>         -#define I2C_STAT_BB    (1 << 12) /* Bus busy */
>         -#define I2C_STAT_ROVR  (1 << 11) /* Receive overrun */
>         -#define I2C_STAT_XUDF  (1 << 10) /* Transmit underflow */
>         -#define I2C_STAT_AAS   (1 << 9)  /* Address as slave */
>         -#define I2C_STAT_GC    (1 << 5)
>         -#define I2C_STAT_XRDY  (1 << 4)  /* Transmit data ready */
>         -#define I2C_STAT_RRDY  (1 << 3)  /* Receive data ready */
>         -#define I2C_STAT_ARDY  (1 << 2)  /* Register access ready */
>         -#define I2C_STAT_NACK  (1 << 1)  /* No acknowledgment interrupt enable */
>         -#define I2C_STAT_AL    (1 << 0)  /* Arbitration lost interrupt enable */
>         -
>         -/* I2C Interrupt Code Register (I2C_INTCODE): */
>         -
>         -#define I2C_INTCODE_MASK       7
>         -#define I2C_INTCODE_NONE       0
>         -#define I2C_INTCODE_AL         1       /* Arbitration lost */
>         -#define I2C_INTCODE_NAK                2       /* No acknowledgement/general call */
>         -#define I2C_INTCODE_ARDY       3       /* Register access ready */
>         -#define I2C_INTCODE_RRDY       4       /* Rcv data ready */
>         -#define I2C_INTCODE_XRDY       5       /* Xmit data ready */
>         -
>         -/* I2C Buffer Configuration Register (I2C_BUF): */
>         -
>         -#define I2C_BUF_RDMA_EN                (1 << 15) /* Receive DMA channel enable */
>         -#define I2C_BUF_XDMA_EN                (1 << 7)  /* Transmit DMA channel enable */
>         -
>         -/* I2C Configuration Register (I2C_CON): */
>         -
>         -#define I2C_CON_EN     (1 << 15)  /* I2C module enable */
>         -#define I2C_CON_BE     (1 << 14)  /* Big endian mode */
>         -#define I2C_CON_STB    (1 << 11)  /* Start byte mode (master mode only) */
>         -#define I2C_CON_MST    (1 << 10)  /* Master/slave mode */
>         -#define I2C_CON_TRX    (1 << 9)   /* Transmitter/receiver mode */
>         -                                  /* (master mode only) */
>         -#define I2C_CON_XA     (1 << 8)   /* Expand address */
>         -#define I2C_CON_STP    (1 << 1)   /* Stop condition (master mode only) */
>         -#define I2C_CON_STT    (1 << 0)   /* Start condition (master mode only) */
>         -
>         -/* I2C System Test Register (I2C_SYSTEST): */
>         -
>         -#define I2C_SYSTEST_ST_EN      (1 << 15) /* System test enable */
>         -#define I2C_SYSTEST_FREE       (1 << 14) /* Free running mode, on brkpoint) */
>         -#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
>         -#define I2C_SYSTEST_TMODE_SHIFT        (12)      /* Test mode select */
>         -#define I2C_SYSTEST_SCL_I      (1 << 3)  /* SCL line sense input value */
>         -#define I2C_SYSTEST_SCL_O      (1 << 2)  /* SCL line drive output value */
>         -#define I2C_SYSTEST_SDA_I      (1 << 1)  /* SDA line sense input value */
>         -#define I2C_SYSTEST_SDA_O      (1 << 0)  /* SDA line drive output value */
>         -
>         -/* I2C System Status Register (I2C_SYSS): */
>         -
>         -#define I2C_SYSS_RDONE          (1 << 0)  /* Internel reset monitoring */
>         -
>         -#define I2C_SCLL_SCLL          0
>         -#define I2C_SCLL_SCLL_M                0xFF
>         -#define I2C_SCLL_HSSCLL                8
>         -#define I2C_SCLH_HSSCLL_M      0xFF
>         -#define I2C_SCLH_SCLH          0
>         -#define I2C_SCLH_SCLH_M                0xFF
>         -#define I2C_SCLH_HSSCLH                8
>         -#define I2C_SCLH_HSSCLH_M      0xFF
>         -
>         -#define OMAP_I2C_STANDARD      100000
>         -#define OMAP_I2C_FAST_MODE     400000
>         -#define OMAP_I2C_HIGH_SPEED    3400000
>         -
>         -#define SYSTEM_CLOCK_12                12000000
>         -#define SYSTEM_CLOCK_13                13000000
>         -#define SYSTEM_CLOCK_192       19200000
>         -#define SYSTEM_CLOCK_96                96000000
>         -
>         -/* Use the reference value of 96MHz if not explicitly set by the board */
>         -#ifndef I2C_IP_CLK
>         -#define I2C_IP_CLK             SYSTEM_CLOCK_96
>         -#endif
>         -
>         -/*
>         - * The reference minimum clock for high speed is 19.2MHz.
>         - * The linux 2.6.30 kernel uses this value.
>         - * The reference minimum clock for fast mode is 9.6MHz
>         - * The reference minimum clock for standard mode is 4MHz
>         - * In TRM, the value of 12MHz is used.
>         - */
>         -#ifndef I2C_INTERNAL_SAMPLING_CLK
>         -#define I2C_INTERNAL_SAMPLING_CLK      19200000
>         -#endif
>         -
>         -/*
>         - * The equation for the low and high time is
>         - * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
>         - * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
>         - *
>         - * If the duty cycle is 50%
>         - *
>         - * tlow = scll + scll_trim = sampling clock / (2 * speed)
>         - * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
>         - *
>         - * In TRM
>         - * scll_trim = 7
>         - * sclh_trim = 5
>         - *
>         - * The linux 2.6.30 kernel uses
>         - * scll_trim = 6
>         - * sclh_trim = 6
>         - *
>         - * These are the trim values for standard and fast speed
>         - */
>         -#ifndef I2C_FASTSPEED_SCLL_TRIM
>         -#define I2C_FASTSPEED_SCLL_TRIM                6
>         -#endif
>         -#ifndef I2C_FASTSPEED_SCLH_TRIM
>         -#define I2C_FASTSPEED_SCLH_TRIM                6
>         -#endif
>         -
>         -/* These are the trim values for high speed */
>         -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
>         -#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM      I2C_FASTSPEED_SCLL_TRIM
>         -#endif
>         -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
>         -#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM      I2C_FASTSPEED_SCLH_TRIM
>         -#endif
>         -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
>         -#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM      I2C_FASTSPEED_SCLL_TRIM
>         -#endif
>         -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
>         -#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM      I2C_FASTSPEED_SCLH_TRIM
>         -#endif
>         -
>         -#define I2C_PSC_MAX            0x0f
>         -#define I2C_PSC_MIN            0x00
>         -
>         -#endif /* _OMAP24XX_I2C_H_ */
>
>
>     --
>     DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
>     HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>
>

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[U-Boot] [PATCH 1/5] i2c: omap24xx: Convert to DM

[Simon Glass]

On 17 January 2016 at 04:09, Christophe Ricard
<christophe.ricard@gmail.com> wrote:
> Convert omap24xx_i2c driver to DM
>
> Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com>
> ---
>
>  drivers/i2c/Kconfig        |   8 ++
>  drivers/i2c/omap24xx_i2c.c | 280 +++++++++++++++++++++++++++++++++++++++++++--
>  2 files changed, 277 insertions(+), 11 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 0/5] Convert omap24xx-i2c driver to Driver Model

[Heiko Schocher]

Hello Richard,

Am 17.01.2016 um 12:09 schrieb Christophe Ricard:
> Hi Simon,
>
> This patchset tries to convert the TI omap24xx_i2c driver to Driver Model.
> It has been tested on a TI BeagleBoard xM.

Sorry for the very late reply ...

Seems this patchset got not applied, as I have it now in my ToDo list...
I think, I thought it has to go through the DM subsystem ...

It does not apply clean anymore ... may you can rebase it against
current ML ?

Thanks!

bye,
Heiko
>
> Best Regards
> Christophe
>
>
>
> Christophe Ricard (5):
>    i2c: omap24xx: Convert to DM
>    i2c: omap24xx: Fix waitdelay value for I2C HS
>    i2c: omap24xx: Remove unused I2C_WAIT macro
>    i2c: omap24xx: Fix high speed trimming calculation
>    i2c: omap24xx: Convert fully to DM_I2C
>
>   drivers/i2c/Kconfig        |   8 +
>   drivers/i2c/omap24xx_i2c.c | 395 ++++++++++++++++++++++++++++++---------------
>   drivers/i2c/omap24xx_i2c.h | 154 ------------------
>   3 files changed, 276 insertions(+), 281 deletions(-)
>   delete mode 100644 drivers/i2c/omap24xx_i2c.h
>

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany