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From: Kever Yang <kever.yang@rock-chips.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [RESEND PATCH v2] mmc: rockchip_sdhci: add clock init for mmc
Date: Wed, 28 Dec 2016 09:12:29 +0800	[thread overview]
Message-ID: <5863117D.2060402@rock-chips.com> (raw)
In-Reply-To: <e0d8459b-aebc-3598-c03b-0199751a8f1b@samsung.com>

Hi Jaehoon,

On 12/28/2016 06:08 AM, Jaehoon Chung wrote:
> Hi Kever,
>
> On 12/27/2016 10:09 PM, Kever Yang wrote:
>> Init the clock rate to CONFIG_ROCKCHIP_SDHCI_MAX_FREQ with clock driver
>> api.
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>> Changes in v2:
>> - using the return value
>>
>>   drivers/mmc/rockchip_sdhci.c | 11 +++++++++++
>>   1 file changed, 11 insertions(+)
>>
>> diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
>> index c56e1a3..96049f3 100644
>> --- a/drivers/mmc/rockchip_sdhci.c
>> +++ b/drivers/mmc/rockchip_sdhci.c
>> @@ -12,6 +12,7 @@
>>   #include <libfdt.h>
>>   #include <malloc.h>
>>   #include <sdhci.h>
>> +#include <clk.h>
>>   
>>   /* 400KHz is max freq for card ID etc. Use that as min */
>>   #define EMMC_MIN_FREQ	400000
>> @@ -33,6 +34,16 @@ static int arasan_sdhci_probe(struct udevice *dev)
>>   	struct rockchip_sdhc *prv = dev_get_priv(dev);
>>   	struct sdhci_host *host = &prv->host;
>>   	int ret;
>> +	struct clk clk;
>> +
>> +	ret = clk_get_by_index(dev, 0, &clk);
>> +	if (!ret) {
>> +		ret = clk_set_rate(&clk, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ);
> How about getting clock value from dt?

SDHCI dts node is like below:
         sdhci: sdhci at fe330000 {
                 u-boot,dm-pre-reloc;
                 compatible = "rockchip,rk3399-sdhci-5.1", 
"arasan,sdhci-5.1";
                 reg = <0x0 0xfe330000 0x0 0x10000>;
                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
                 assigned-clocks = <&cru SCLK_EMMC>;
                 assigned-clock-rates = <200000000>;
                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
                 clock-names = "clk_xin", "clk_ahb";
                 phys = <&emmc_phy>;
                 phy-names = "phy_arasan";
                 status = "disabled";
         };

There is an assigned-clock-rates, which is parsed by clock driver in 
kernel,
but the U-Boot clk driver do not have this feature, is it OK for us to 
parse it in sdhci driver?

Thanks,
- Kever

>
> Best Regards,
> Jaehoon Chung
>
>> +		if (IS_ERR_VALUE(ret))
>> +			printf("%s clk set rate fail!\n", __func__);
>> +	} else {
>> +		printf("%s fail to get clk\n", __func__);
>> +	}
>>   
>>   	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
>>   
>>
>
>
>

  reply	other threads:[~2016-12-28  1:12 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20161227131000epcas2p346436031cb1af4ade4ff7b0374a2bd4b@epcas2p3.samsung.com>
2016-12-27 13:09 ` [U-Boot] [RESEND PATCH v2] mmc: rockchip_sdhci: add clock init for mmc Kever Yang
2016-12-27 22:08   ` Jaehoon Chung
2016-12-28  1:12     ` Kever Yang [this message]
2016-12-28  1:34       ` Jaehoon Chung
2016-12-28  1:45         ` Kever Yang
2016-12-28  2:03           ` Jaehoon Chung

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