* [U-Boot] Rockchip RK3288 boot trouble
@ 2017-01-15 19:05 Rick Bronson
2017-01-16 2:50 ` Simon Glass
0 siblings, 1 reply; 5+ messages in thread
From: Rick Bronson @ 2017-01-15 19:05 UTC (permalink / raw)
To: u-boot
Hi All,
I updated one of my two RK3288 boards (Viewsonic) with newer Android
factory firmware (using Windows) and now it won't boot mainline u-boot
when I use the same exact recipe that worked previously:
sudo ${UPGD} db rkbin/rk32/rk3288_boot.bin
sudo ${UPGD} wl 0x40 tftpboot/u-boot-dtb.bin
Been trying to figure out what's wrong. My theory is that the newer
firmware enabled one of the "boot areas" of the eMMC and the "wl 0x40"
command above only writes to the user area of the eMMC.
I can still load and run one of the Android u-boots using the
boot_merger method:
./tools/boot_merger --subfix ".10.bin" ./tools/rk_tools/RKBOOT/RK3288.ini
then flashing via:
sudo ${UPGD} ul u-boot-android/RK3288UbootLoader_V2.30.10.bin
But these u-boot's are virtually useless since they striped of
useful commands (like mmc commands).
I tried using the above boot_merger command on mainline u-boot but
it only boots this far (I've tried u-boot-dtb.bin and u-boot.bin):
--------------------------
U-Boot 2016.11-08467-g05b8ba7-dirty (Jan 15 2017 - 10:40:37 -0800)
Model: SCT36-RK3288
DRAM: 128 MiB
--------------------------
Note the incorrect DRAM size. My normal boot looks like:
--------------------------
U-Boot SPL 2016.11-08467-g05b8ba7-dirty (Dec 18 2016 - 11:00:14)
U-Boot 2016.11-08467-g05b8ba7-dirty (Dec 18 2016 - 11:00:14 -0800)
Model: SCT36-RK3288
DRAM: 2 GiB
MMC: dwmmc at ff0c0000: 0, dwmmc at ff0f0000: 1
...
--------------------------
Note that this runs SPL, then normal u-boot whereas the previous one
didn't run SPL.
Any ideas how I can get mainline u-boot running on this board?
Thanks much,
Rick
^ permalink raw reply [flat|nested] 5+ messages in thread* [U-Boot] Rockchip RK3288 boot trouble
2017-01-15 19:05 [U-Boot] Rockchip RK3288 boot trouble Rick Bronson
@ 2017-01-16 2:50 ` Simon Glass
2017-01-16 6:46 ` Kever Yang
0 siblings, 1 reply; 5+ messages in thread
From: Simon Glass @ 2017-01-16 2:50 UTC (permalink / raw)
To: u-boot
+Kever
Hi Rick,
On 15 January 2017 at 12:05, Rick Bronson <rick@efn.org> wrote:
> Hi All,
>
> I updated one of my two RK3288 boards (Viewsonic) with newer Android
> factory firmware (using Windows) and now it won't boot mainline u-boot
> when I use the same exact recipe that worked previously:
>
> sudo ${UPGD} db rkbin/rk32/rk3288_boot.bin
> sudo ${UPGD} wl 0x40 tftpboot/u-boot-dtb.bin
>
> Been trying to figure out what's wrong. My theory is that the newer
> firmware enabled one of the "boot areas" of the eMMC and the "wl 0x40"
> command above only writes to the user area of the eMMC.
>
> I can still load and run one of the Android u-boots using the
> boot_merger method:
>
> ./tools/boot_merger --subfix ".10.bin" ./tools/rk_tools/RKBOOT/RK3288.ini
>
> then flashing via:
>
> sudo ${UPGD} ul u-boot-android/RK3288UbootLoader_V2.30.10.bin
>
> But these u-boot's are virtually useless since they striped of
> useful commands (like mmc commands).
>
> I tried using the above boot_merger command on mainline u-boot but
> it only boots this far (I've tried u-boot-dtb.bin and u-boot.bin):
>
> --------------------------
> U-Boot 2016.11-08467-g05b8ba7-dirty (Jan 15 2017 - 10:40:37 -0800)
>
> Model: SCT36-RK3288
> DRAM: 128 MiB
> --------------------------
>
> Note the incorrect DRAM size. My normal boot looks like:
>
> --------------------------
> U-Boot SPL 2016.11-08467-g05b8ba7-dirty (Dec 18 2016 - 11:00:14)
>
> U-Boot 2016.11-08467-g05b8ba7-dirty (Dec 18 2016 - 11:00:14 -0800)
>
> Model: SCT36-RK3288
> DRAM: 2 GiB
> MMC: dwmmc at ff0c0000: 0, dwmmc at ff0f0000: 1
> ...
> --------------------------
>
> Note that this runs SPL, then normal u-boot whereas the previous one
> didn't run SPL.
>
> Any ideas how I can get mainline u-boot running on this board?
You might try a git bisect. We moved to auto-detected the RAM size
recently, so perhaps that changed something?
7d6c78f rk3288: sdram: auto-detect the capacity
>
> Thanks much,
>
> Rick
>
>
>
Regards,
Simon
^ permalink raw reply [flat|nested] 5+ messages in thread* [U-Boot] Rockchip RK3288 boot trouble
2017-01-16 2:50 ` Simon Glass
@ 2017-01-16 6:46 ` Kever Yang
0 siblings, 0 replies; 5+ messages in thread
From: Kever Yang @ 2017-01-16 6:46 UTC (permalink / raw)
To: u-boot
Hi Rick,
On 01/16/2017 10:50 AM, Simon Glass wrote:
> +Kever
>
> Hi Rick,
>
> On 15 January 2017 at 12:05, Rick Bronson <rick@efn.org> wrote:
>> Hi All,
>>
>> I updated one of my two RK3288 boards (Viewsonic) with newer Android
>> factory firmware (using Windows) and now it won't boot mainline u-boot
>> when I use the same exact recipe that worked previously:
>>
>> sudo ${UPGD} db rkbin/rk32/rk3288_boot.bin
>> sudo ${UPGD} wl 0x40 tftpboot/u-boot-dtb.bin
I didn't see your detail steps for getting u-boot-dtb.bin, does it
include SPL here?
We have two way to boot the RK3288 on upstream U-Boot SPL(pls reference to
doc/README.rockchip):
1. without "CONFIG_ROCKCHIP_SPL_BACK_TO_BROM", which is previous version,
To write an image that boots from an SD card (assumed to be /dev/sdc):
./firefly-rk3288/tools/mkimage -n rk3288 -T rksd -d \
firefly-rk3288/spl/u-boot-spl-dtb.bin out && \
sudo dd if=out of=/dev/sdc seek=64 && \
sudo dd if=firefly-rk3288/u-boot-dtb.img of=/dev/sdc seek=256
This puts the Rockchip header and SPL image first and then places the U-Boot
image at block 256.
2. with "CONFIG_ROCKCHIP_SPL_BACK_TO_BROM", which is default setting
recently,
The rockchip bootrom can load and boot an initial spl, then continue to
load a second-level bootloader(ie. U-BOOT) as soon as it returns to bootrom.
Therefore RK3288 has another loading sequence like RK3036.
You can create the image via the following operations:
./firefly-rk3288/tools/mkimage -n rk3288 -T rksd -d \
firefly-rk3288/spl/u-boot-spl-dtb.bin out && \
cat firefly-rk3288/u-boot-dtb.bin >> out && \
sudo dd if=out of=/dev/sdc seek=64
both way using upstream SPL + upstream u-boot.bin.
>> Been trying to figure out what's wrong. My theory is that the newer
>> firmware enabled one of the "boot areas" of the eMMC and the "wl 0x40"
>> command above only writes to the user area of the eMMC.
>>
>> I can still load and run one of the Android u-boots using the
>> boot_merger method:
>>
>> ./tools/boot_merger --subfix ".10.bin" ./tools/rk_tools/RKBOOT/RK3288.ini
boot_merger is a tool from Rockchip, which create image for Rockchip
bootrom,
you may need to modify RK3288.ini and keep everything else but replace the
FlashBoot with mainline U-Boot bin.
In this way, you are using Rockchip SPL(ddr init) and upstream U-Boot.
>> then flashing via:
>>
>> sudo ${UPGD} ul u-boot-android/RK3288UbootLoader_V2.30.10.bin
>>
>> But these u-boot's are virtually useless since they striped of
>> useful commands (like mmc commands).
>>
>> I tried using the above boot_merger command on mainline u-boot but
>> it only boots this far (I've tried u-boot-dtb.bin and u-boot.bin):
>>
>> --------------------------
>> U-Boot 2016.11-08467-g05b8ba7-dirty (Jan 15 2017 - 10:40:37 -0800)
>>
>> Model: SCT36-RK3288
>> DRAM: 128 MiB
>> --------------------------
>>
>> Note the incorrect DRAM size.
I'm confusing with this incorrect DRAM size, could you share the console
output
during you flash the image, there should have correct DRAM size info.
I'm not sure if the DRAM on your board is symmetric or not, or any else
special.
If you are using the upstream SPL, could you pls enable the DEBUG option and
dump a log, we may able to see what happen on your board.
>> My normal boot looks like:
>>
>> --------------------------
>> U-Boot SPL 2016.11-08467-g05b8ba7-dirty (Dec 18 2016 - 11:00:14)
>>
>> U-Boot 2016.11-08467-g05b8ba7-dirty (Dec 18 2016 - 11:00:14 -0800)
>>
>> Model: SCT36-RK3288
>> DRAM: 2 GiB
>> MMC: dwmmc at ff0c0000: 0, dwmmc at ff0f0000: 1
>> ...
>> --------------------------
>>
>> Note that this runs SPL, then normal u-boot whereas the previous one
>> didn't run SPL.
When you are using Rockchip SPL(DRAM INIT), there is no message with 'SPL',
but there do have some print about DRAM info, could you dump that message?
Thanks,
- Kever
>>
>> Any ideas how I can get mainline u-boot running on this board?
> You might try a git bisect. We moved to auto-detected the RAM size
> recently, so perhaps that changed something?
>
> 7d6c78f rk3288: sdram: auto-detect the capacity
>
>> Thanks much,
>>
>> Rick
>>
>>
>>
> Regards,
> Simon
>
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] Rockchip RK3288 boot trouble
@ 2017-01-19 18:29 Rick Bronson
2017-01-22 6:54 ` Kever Yang
0 siblings, 1 reply; 5+ messages in thread
From: Rick Bronson @ 2017-01-19 18:29 UTC (permalink / raw)
To: u-boot
Hi Kever and Simon,
Thanks very much for the help. Really appreciate it.
> I didn't see your detail steps for getting u-boot-dtb.bin, does it
> include SPL here?
I'm using this method:
> 2. with "CONFIG_ROCKCHIP_SPL_BACK_TO_BROM", which is default setting
...
> I'm confusing with this incorrect DRAM size, could you share the console
> output
> during you flash the image, there should have correct DRAM size info.
> I'm not sure if the DRAM on your board is symmetric or not, or any else
> special.
See below for the output. I noticed that I only have "Channel b"
and not "Channel a". On my other board that boots, I have both a and b. I
wonder if one bank of DDR3 went bad on this
board. What do you think?
Thanks again.
Rick
DDR Version 1.00 20160217
In
Channel b: DDR3 200MHz
Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=8 Size=1024MB
Memory OK
OUT
usb boot ver:20160218
ChipType = 8
...FlashInit enter...
FtlMallocOffset = 8040 8000
FtlMallocOffset = 10040 8000
FtlMallocOffset = 11040 1000
FtlMallocOffset = 19040 8000
FtlMallocOffset = 1a040 1000
1:0 0 7f7f05 22
...NandcInit enter...
0:1200 0 7f7f05 22
FtlMallocOffset = 23040 9000
gNandcVer = 6
SDC_BusRequest: CMD=8 SDC_RESP_TIMEOUT 1815
SDC_BusRequest: CMD=8 SDC_RESP_TIMEOUT 1815
SDC_BusRequest: CMD=8 SDC_RESP_TIMEOUT 1815
SDC_BusRequest: CMD=5 SDC_RESP_TIMEOUT 1815
SDC_BusRequest: CMD=5 SDC_RESP_TIMEOUT 1815
SDC_BusRequest: CMD=5 SDC_RESP_TIMEOUT 1815
SDC_BusRequest: CMD=55 SDC_RESP_TIMEOUT 1815
SDC_BusRequest: CMD=55 SDC_RESP_TIMEOUT 1815
SDC_BusRequest: CMD=55 SDC_RESP_TIMEOUT 1815
mmc Ext_csd, ret=0 ,
Ext[226]=20, bootSize=2000,
Ext[215]=1, Ext[214]=d5, Ext[213]=a0, Ext[212]=0,cap
=1d5a000 R
EL=1f
SdmmcInit=2 0
BootCapSize=2000
UserCapSize=1d5a000
FwPartOffset=2000 , 2000
UsbHook 622396
powerOn 623080
DDR Version 1.00 20160217
In
SRX
Channel b: DDR3 200MHz
Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=8 Size=1024MB
^ permalink raw reply [flat|nested] 5+ messages in thread* [U-Boot] Rockchip RK3288 boot trouble
2017-01-19 18:29 Rick Bronson
@ 2017-01-22 6:54 ` Kever Yang
0 siblings, 0 replies; 5+ messages in thread
From: Kever Yang @ 2017-01-22 6:54 UTC (permalink / raw)
To: u-boot
Hi Rick,
On 01/20/2017 02:29 AM, Rick Bronson wrote:
> Hi Kever and Simon,
>
> Thanks very much for the help. Really appreciate it.
>
>> I didn't see your detail steps for getting u-boot-dtb.bin, does it
>> include SPL here?
> I'm using this method:
>
>> 2. with "CONFIG_ROCKCHIP_SPL_BACK_TO_BROM", which is default setting
> ...
>
>> I'm confusing with this incorrect DRAM size, could you share the console
>> output
>> during you flash the image, there should have correct DRAM size info.
>> I'm not sure if the DRAM on your board is symmetric or not, or any else
>> special.
> See below for the output. I noticed that I only have "Channel b"
> and not "Channel a". On my other board that boots, I have both a and b. I
> wonder if one bank of DDR3 went bad on this
> board. What do you think?
Looks like there is something wrong on channel a DDR, and upstream
source code does not
support this kind of solution, but if you are using rockchip DRAM init
code, you board should
be still work only with one channel DRAM.
Thanks,
- Kever
>
> Thanks again.
>
> Rick
>
>
> DDR Version 1.00 20160217
> In
> Channel b: DDR3 200MHz
> Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=8 Size=1024MB
> Memory OK
> OUT
> usb boot ver:20160218
> ChipType = 8
> ...FlashInit enter...
> FtlMallocOffset = 8040 8000
> FtlMallocOffset = 10040 8000
> FtlMallocOffset = 11040 1000
> FtlMallocOffset = 19040 8000
> FtlMallocOffset = 1a040 1000
> 1:0 0 7f7f05 22
> ...NandcInit enter...
> 0:1200 0 7f7f05 22
> FtlMallocOffset = 23040 9000
> gNandcVer = 6
> SDC_BusRequest: CMD=8 SDC_RESP_TIMEOUT 1815
> SDC_BusRequest: CMD=8 SDC_RESP_TIMEOUT 1815
> SDC_BusRequest: CMD=8 SDC_RESP_TIMEOUT 1815
> SDC_BusRequest: CMD=5 SDC_RESP_TIMEOUT 1815
> SDC_BusRequest: CMD=5 SDC_RESP_TIMEOUT 1815
> SDC_BusRequest: CMD=5 SDC_RESP_TIMEOUT 1815
> SDC_BusRequest: CMD=55 SDC_RESP_TIMEOUT 1815
> SDC_BusRequest: CMD=55 SDC_RESP_TIMEOUT 1815
> SDC_BusRequest: CMD=55 SDC_RESP_TIMEOUT 1815
> mmc Ext_csd, ret=0 ,
> Ext[226]=20, bootSize=2000,
> Ext[215]=1, Ext[214]=d5, Ext[213]=a0, Ext[212]=0,cap
> =1d5a000 R
> EL=1f
> SdmmcInit=2 0
> BootCapSize=2000
> UserCapSize=1d5a000
> FwPartOffset=2000 , 2000
> UsbHook 622396
> powerOn 623080
> DDR Version 1.00 20160217
> In
> SRX
> Channel b: DDR3 200MHz
> Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=8 Size=1024MB
>
>
>
>
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
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2017-01-16 2:50 ` Simon Glass
2017-01-16 6:46 ` Kever Yang
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2017-01-22 6:54 ` Kever Yang
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