* [U-Boot] [PATCH 1/7] arm64: dts: add support for Rockchip rk3328 soc
2017-02-17 8:07 [U-Boot] [PATCH 0/7] add support for rk3328 SoC Kever Yang
@ 2017-02-17 8:07 ` Kever Yang
2017-02-21 18:06 ` Simon Glass
2017-02-17 8:07 ` [U-Boot] [PATCH 2/7] ARM64: rockchip: add support for rk3328 SoC Kever Yang
` (6 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Kever Yang @ 2017-02-17 8:07 UTC (permalink / raw)
To: u-boot
Add dts binding header for rk3328, files origin from kernel.
Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3328-evb.dts | 45 +
arch/arm/dts/rk3328.dtsi | 1477 ++++++++++++++++++++++++++++++++
include/dt-bindings/clock/rk3328-cru.h | 394 +++++++++
4 files changed, 1917 insertions(+)
create mode 100644 arch/arm/dts/rk3328-evb.dts
create mode 100644 arch/arm/dts/rk3328.dtsi
create mode 100644 include/dt-bindings/clock/rk3328-cru.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index eb68c20..1a6659c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -38,6 +38,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-fennec.dtb \
rk3288-tinker.dtb \
rk3288-popmetal.dtb \
+ rk3328-evb.dtb \
rk3399-evb.dtb
dtb-$(CONFIG_ARCH_MESON) += \
meson-gxbb-odroidc2.dtb
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
new file mode 100644
index 0000000..01794ed
--- /dev/null
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+
+/ {
+ model = "Rockchip RK3328 EVB";
+ compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ disable-wp;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
+ status = "okay";
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ supports-emmc;
+ disable-wp;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
new file mode 100644
index 0000000..8a98ee3
--- /dev/null
+++ b/arch/arm/dts/rk3328.dtsi
@@ -0,0 +1,1477 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/clock/rk3328-cru.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+ compatible = "rockchip,rk3328";
+
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+// clocks = <&cru ARMCLK>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ cpu1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+ cpu2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ };
+ cpu3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ };
+ };
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp at 408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp at 600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp at 816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp at 1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <40000>;
+ };
+ opp at 1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1225000>;
+ clock-latency-ns = <40000>;
+ };
+ opp at 1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1300000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ xin24m: xin24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ };
+
+ i2s0: i2s at ff000000 {
+ compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xff000000 0x0 0x1000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ dmas = <&dmac 11>, <&dmac 12>;
+ #dma-cells = <2>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2s1: i2s at ff010000 {
+ compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xff010000 0x0 0x1000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ dmas = <&dmac 14>, <&dmac 15>;
+ #dma-cells = <2>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2s2: i2s at ff020000 {
+ compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
+ reg = <0x0 0xff020000 0x0 0x1000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ dmas = <&dmac 0>, <&dmac 1>;
+ #dma-cells = <2>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2s2m0_mclk
+ &i2s2m0_sclk
+ &i2s2m0_lrcktx
+ &i2s2m0_lrckrx
+ &i2s2m0_sdo
+ &i2s2m0_sdi>;
+ pinctrl-1 = <&i2s2m0_sleep>;
+ status = "disabled";
+ };
+
+ spdif: spdif at ff030000 {
+ compatible = "rockchip,rk3328-spdif";
+ reg = <0x0 0xff030000 0x0 0x1000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac 10>;
+ #dma-cells = <1>;
+ dma-names = "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdifm2_tx>;
+ status = "disabled";
+ };
+
+ grf: syscon at ff100000 {
+ compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xff100000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ io_domains: io-domains {
+ compatible = "rockchip,rk3328-io-voltage-domain";
+ status = "disabled";
+ };
+ };
+
+ uart0: serial at ff110000 {
+ compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff110000 0x0 0x100>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 2>, <&dmac 3>;
+ #dma-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "disabled";
+ };
+
+ uart1: serial at ff120000 {
+ compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff120000 0x0 0x100>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "sclk_uart", "pclk_uart";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 4>, <&dmac 5>;
+ #dma-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
+ status = "disabled";
+ };
+
+ uart2: serial at ff130000 {
+ compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff130000 0x0 0x100>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ clock-frequency = <24000000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 6>, <&dmac 7>;
+ #dma-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m1_xfer>;
+ status = "disabled";
+ };
+
+ pmu: power-management at ff140000 {
+ compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
+ reg = <0x0 0xff140000 0x0 0x1000>;
+ };
+
+ i2c0: i2c at ff150000 {
+ compatible = "rockchip,rk3328-i2c";
+ reg = <0x0 0xff150000 0x0 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at ff160000 {
+ compatible = "rockchip,rk3328-i2c";
+ reg = <0x0 0xff160000 0x0 0x1000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_xfer>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at ff170000 {
+ compatible = "rockchip,rk3328-i2c";
+ reg = <0x0 0xff170000 0x0 0x1000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_xfer>;
+ status = "disabled";
+ };
+
+ i2c3: i2c at ff180000 {
+ compatible = "rockchip,rk3328-i2c";
+ reg = <0x0 0xff180000 0x0 0x1000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_xfer>;
+ status = "disabled";
+ };
+
+ spi0: spi at ff190000 {
+ compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0xff190000 0x0 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac 8>, <&dmac 9>;
+ #dma-cells = <2>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
+ status = "disabled";
+ };
+
+ wdt: watchdog at ff1a0000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0xff1a0000 0x0 0x100>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ amba {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dmac: dmac at ff1f0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xff1f0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ };
+ };
+
+ saradc: saradc at ff280000 {
+ compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
+ reg = <0x0 0xff280000 0x0 0x100>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_SARADC_P>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
+ cru: clock-controller at ff440000 {
+ compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
+ reg = <0x0 0xff440000 0x0 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ assigned-clocks =
+ <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
+ <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
+ <&cru SCLK_UART1>, <&cru SCLK_UART2>,
+ <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+ <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
+ <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
+ <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
+ <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
+ <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
+ <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
+ <&cru SCLK_WIFI>, <&cru ARMCLK>,
+ <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+ <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
+ <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+ <&cru HCLK_PERI>, <&cru PCLK_PERI>,
+ <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
+ <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
+ <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
+ <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
+ <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
+ <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
+ <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
+ <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
+ <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
+ assigned-clock-parents =
+ <&cru HDMIPHY>, <&cru PLL_APLL>,
+ <&cru PLL_GPLL>, <&xin24m>,
+ <&xin24m>, <&xin24m>;
+ assigned-clock-rates =
+ <0>, <61440000>,
+ <0>, <24000000>,
+ <24000000>, <24000000>,
+ <15000000>, <15000000>,
+ <100000000>, <100000000>,
+ <100000000>, <100000000>,
+ <50000000>, <100000000>,
+ <100000000>, <100000000>,
+ <50000000>, <50000000>,
+ <50000000>, <50000000>,
+ <24000000>, <600000000>,
+ <491520000>, <1200000000>,
+ <150000000>, <75000000>,
+ <75000000>, <150000000>,
+ <75000000>, <75000000>,
+ <300000000>, <100000000>,
+ <300000000>, <200000000>,
+ <400000000>, <500000000>,
+ <200000000>, <300000000>,
+ <300000000>, <250000000>,
+ <200000000>, <100000000>,
+ <24000000>, <100000000>,
+ <150000000>, <50000000>,
+ <32768>, <32768>;
+ };
+
+ sdmmc: rksdmmc at ff500000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff500000 0x0 0x4000>;
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sdio: dwmmc at ff510000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff510000 0x0 0x4000>;
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ emmc: rksdmmc at ff520000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff520000 0x0 0x4000>;
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sdmmc_ext: rksdmmc at ff5f0000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff5f0000 0x0 0x4000>;
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller at ffb70000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0xff811000 0 0x1000>,
+ <0x0 0xff812000 0 0x2000>,
+ <0x0 0xff814000 0 0x2000>,
+ <0x0 0xff816000 0 0x2000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3328-pinctrl";
+ rockchip,grf = <&grf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio0 at ff210000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff210000 0x0 0x100>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio1 at ff220000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff220000 0x0 0x100>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio2 at ff230000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff230000 0x0 0x100>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio3 at ff240000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff240000 0x0 0x100>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ pcfg_pull_down: pcfg-pull-down {
+ bias-pull-down;
+ };
+
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ pcfg_pull_none_2ma: pcfg-pull-none-2ma {
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ pcfg_pull_up_2ma: pcfg-pull-up-2ma {
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pcfg_pull_up_4ma: pcfg-pull-up-4ma {
+ bias-pull-up;
+ drive-strength = <4>;
+ };
+
+ pcfg_pull_none_4ma: pcfg-pull-none-4ma {
+ bias-disable;
+ drive-strength = <4>;
+ };
+
+ pcfg_pull_down_4ma: pcfg-pull-down-4ma {
+ bias-pull-down;
+ drive-strength = <4>;
+ };
+
+ pcfg_pull_none_8ma: pcfg-pull-none-8ma {
+ bias-disable;
+ drive-strength = <8>;
+ };
+
+ pcfg_pull_up_8ma: pcfg-pull-up-8ma {
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ pcfg_pull_none_12ma: pcfg-pull-none-12ma {
+ bias-disable;
+ drive-strength = <12>;
+ };
+
+ pcfg_pull_up_12ma: pcfg-pull-up-12ma {
+ bias-pull-up;
+ drive-strength = <12>;
+ };
+
+ pcfg_output_high: pcfg-output-high {
+ output-high;
+ };
+
+ pcfg_output_low: pcfg-output-low {
+ output-low;
+ };
+
+ pcfg_input_high: pcfg-input-high {
+ bias-pull-up;
+ input-enable;
+ };
+
+ pcfg_input: pcfg-input {
+ input-enable;
+ };
+
+ i2c0 {
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins =
+ <2 24 RK_FUNC_1 &pcfg_pull_none>,
+ <2 25 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c1 {
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins =
+ <2 4 RK_FUNC_2 &pcfg_pull_none>,
+ <2 5 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ i2c2 {
+ i2c2_xfer: i2c2-xfer {
+ rockchip,pins =
+ <2 13 RK_FUNC_1 &pcfg_pull_none>,
+ <2 14 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c3 {
+ i2c3_xfer: i2c3-xfer {
+ rockchip,pins =
+ <0 5 RK_FUNC_2 &pcfg_pull_none>,
+ <0 6 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ i2c3_gpio: i2c3-gpio {
+ rockchip,pins =
+ <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
+ <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ hdmi_i2c {
+ hdmii2c_xfer: hdmii2c-xfer {
+ rockchip,pins =
+ <0 5 RK_FUNC_1 &pcfg_pull_none>,
+ <0 6 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ uart0_xfer: uart0-xfer {
+ rockchip,pins =
+ <1 9 RK_FUNC_1 &pcfg_pull_up>,
+ <1 8 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_cts: uart0-cts {
+ rockchip,pins =
+ <1 11 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_rts: uart0-rts {
+ rockchip,pins =
+ <1 10 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_rts_gpio: uart0-rts-gpio {
+ rockchip,pins =
+ <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ uart1_xfer: uart1-xfer {
+ rockchip,pins =
+ <3 4 RK_FUNC_4 &pcfg_pull_up>,
+ <3 6 RK_FUNC_4 &pcfg_pull_none>;
+ };
+
+ uart1_cts: uart1-cts {
+ rockchip,pins =
+ <3 7 RK_FUNC_4 &pcfg_pull_none>;
+ };
+
+ uart1_rts: uart1-rts {
+ rockchip,pins =
+ <3 5 RK_FUNC_4 &pcfg_pull_none>;
+ };
+
+ uart1_rts_gpio: uart1-rts-gpio {
+ rockchip,pins =
+ <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ uart2-0 {
+ uart2m0_xfer: uart2m0-xfer {
+ rockchip,pins =
+ <1 0 RK_FUNC_2 &pcfg_pull_up>,
+ <1 1 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ uart2-1 {
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins =
+ <2 0 RK_FUNC_1 &pcfg_pull_up>,
+ <2 1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ spi0-0 {
+ spi0m0_clk: spi0m0-clk {
+ rockchip,pins =
+ <2 8 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ spi0m0_cs0: spi0m0-cs0 {
+ rockchip,pins =
+ <2 11 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ spi0m0_tx: spi0m0-tx {
+ rockchip,pins =
+ <2 9 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ spi0m0_rx: spi0m0-rx {
+ rockchip,pins =
+ <2 10 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ spi0m0_cs1: spi0m0-cs1 {
+ rockchip,pins =
+ <2 12 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
+ spi0-1 {
+ spi0m1_clk: spi0m1-clk {
+ rockchip,pins =
+ <3 23 RK_FUNC_2 &pcfg_pull_up>;
+ };
+
+ spi0m1_cs0: spi0m1-cs0 {
+ rockchip,pins =
+ <3 26 RK_FUNC_2 &pcfg_pull_up>;
+ };
+
+ spi0m1_tx: spi0m1-tx {
+ rockchip,pins =
+ <3 25 RK_FUNC_2 &pcfg_pull_up>;
+ };
+
+ spi0m1_rx: spi0m1-rx {
+ rockchip,pins =
+ <3 24 RK_FUNC_2 &pcfg_pull_up>;
+ };
+
+ spi0m1_cs1: spi0m1-cs1 {
+ rockchip,pins =
+ <3 27 RK_FUNC_2 &pcfg_pull_up>;
+ };
+ };
+
+ spi0-2 {
+ spi0m2_clk: spi0m2-clk {
+ rockchip,pins =
+ <3 0 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ spi0m2_cs0: spi0m2-cs0 {
+ rockchip,pins =
+ <3 8 RK_FUNC_3 &pcfg_pull_up>;
+ };
+
+ spi0m2_tx: spi0m2-tx {
+ rockchip,pins =
+ <3 1 RK_FUNC_4 &pcfg_pull_up>;
+ };
+
+ spi0m2_rx: spi0m2-rx {
+ rockchip,pins =
+ <3 2 RK_FUNC_4 &pcfg_pull_up>;
+ };
+ };
+
+ i2s1 {
+ i2s1_mclk: i2s1-mclk {
+ rockchip,pins =
+ <2 15 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ i2s1_sclk: i2s1-sclk {
+ rockchip,pins =
+ <2 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ i2s1_lrckrx: i2s1-lrckrx {
+ rockchip,pins =
+ <2 16 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ i2s1_lrcktx: i2s1-lrcktx {
+ rockchip,pins =
+ <2 17 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ i2s1_sdi: i2s1-sdi {
+ rockchip,pins =
+ <2 19 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ i2s1_sdo: i2s1-sdo {
+ rockchip,pins =
+ <2 23 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ i2s1_sdio1: i2s1-sdio1 {
+ rockchip,pins =
+ <2 20 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ i2s1_sdio2: i2s1-sdio2 {
+ rockchip,pins =
+ <2 21 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ i2s1_sdio3: i2s1-sdio3 {
+ rockchip,pins =
+ <2 22 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ i2s1_sleep: i2s1-sleep {
+ rockchip,pins =
+ <2 15 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 16 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 17 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 18 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 19 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 20 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 21 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 22 RK_FUNC_GPIO &pcfg_input_high>,
+ <2 23 RK_FUNC_GPIO &pcfg_input_high>;
+ };
+ };
+
+ i2s2-0 {
+ i2s2m0_mclk: i2s2m0-mclk {
+ rockchip,pins =
+ <1 21 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_sclk: i2s2m0-sclk {
+ rockchip,pins =
+ <1 22 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_lrckrx: i2s2m0-lrckrx {
+ rockchip,pins =
+ <1 26 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_lrcktx: i2s2m0-lrcktx {
+ rockchip,pins =
+ <1 23 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_sdi: i2s2m0-sdi {
+ rockchip,pins =
+ <1 24 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_sdo: i2s2m0-sdo {
+ rockchip,pins =
+ <1 25 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_sleep: i2s2m0-sleep {
+ rockchip,pins =
+ <1 21 RK_FUNC_GPIO &pcfg_input_high>,
+ <1 22 RK_FUNC_GPIO &pcfg_input_high>,
+ <1 26 RK_FUNC_GPIO &pcfg_input_high>,
+ <1 23 RK_FUNC_GPIO &pcfg_input_high>,
+ <1 24 RK_FUNC_GPIO &pcfg_input_high>,
+ <1 25 RK_FUNC_GPIO &pcfg_input_high>;
+ };
+ };
+
+ i2s2-1 {
+ i2s2m1_mclk: i2s2m1-mclk {
+ rockchip,pins =
+ <1 21 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ i2s2m1_sclk: i2s2m1-sclk {
+ rockchip,pins =
+ <3 0 RK_FUNC_6 &pcfg_pull_none>;
+ };
+
+ i2s2m1_lrckrx: i2sm1-lrckrx {
+ rockchip,pins =
+ <3 8 RK_FUNC_6 &pcfg_pull_none>;
+ };
+
+ i2s2m1_lrcktx: i2s2m1-lrcktx {
+ rockchip,pins =
+ <3 8 RK_FUNC_4 &pcfg_pull_none>;
+ };
+
+ i2s2m1_sdi: i2s2m1-sdi {
+ rockchip,pins =
+ <3 2 RK_FUNC_6 &pcfg_pull_none>;
+ };
+
+ i2s2m1_sdo: i2s2m1-sdo {
+ rockchip,pins =
+ <3 1 RK_FUNC_6 &pcfg_pull_none>;
+ };
+
+ i2s2m1_sleep: i2s2m1-sleep {
+ rockchip,pins =
+ <1 21 RK_FUNC_GPIO &pcfg_input_high>,
+ <3 0 RK_FUNC_GPIO &pcfg_input_high>,
+ <3 8 RK_FUNC_GPIO &pcfg_input_high>,
+ <3 2 RK_FUNC_GPIO &pcfg_input_high>,
+ <3 1 RK_FUNC_GPIO &pcfg_input_high>;
+ };
+ };
+
+ spdif-0 {
+ spdifm0_tx: spdifm0-tx {
+ rockchip,pins =
+ <0 27 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ spdif-1 {
+ spdifm1_tx: spdifm1-tx {
+ rockchip,pins =
+ <2 17 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ spdif-2 {
+ spdifm2_tx: spdifm2-tx {
+ rockchip,pins =
+ <0 2 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc0-0 {
+ sdmmc0m0_pwren: sdmmc0m0-pwren {
+ rockchip,pins =
+ <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0m0_gpio: sdmmc0m0-gpio {
+ rockchip,pins =
+ <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
+ };
+ };
+
+ sdmmc0-1 {
+ sdmmc0m1_pwren: sdmmc0m1-pwren {
+ rockchip,pins =
+ <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0m1_gpio: sdmmc0m1-gpio {
+ rockchip,pins =
+ <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
+ };
+ };
+
+ sdmmc0 {
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins =
+ <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
+ };
+
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins =
+ <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_dectn: sdmmc0-dectn {
+ rockchip,pins =
+ <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_wrprt: sdmmc0-wrprt {
+ rockchip,pins =
+ <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_bus1: sdmmc0-bus1 {
+ rockchip,pins =
+ <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins =
+ <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
+ <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
+ <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
+ <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0_gpio: sdmmc0-gpio {
+ rockchip,pins =
+ <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
+ };
+ };
+
+ sdmmc0ext {
+ sdmmc0ext_clk: sdmmc0ext-clk {
+ rockchip,pins =
+ <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
+ };
+
+ sdmmc0ext_cmd: sdmmc0ext-cmd {
+ rockchip,pins =
+ <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0ext_wrprt: sdmmc0ext-wrprt {
+ rockchip,pins =
+ <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0ext_dectn: sdmmc0ext-dectn {
+ rockchip,pins =
+ <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0ext_bus1: sdmmc0ext-bus1 {
+ rockchip,pins =
+ <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0ext_bus4: sdmmc0ext-bus4 {
+ rockchip,pins =
+ <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
+ <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
+ <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
+ <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0ext_gpio: sdmmc0ext-gpio {
+ rockchip,pins =
+ <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
+ };
+ };
+
+ sdmmc1 {
+ sdmmc1_clk: sdmmc1-clk {
+ rockchip,pins =
+ <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
+ };
+
+ sdmmc1_cmd: sdmmc1-cmd {
+ rockchip,pins =
+ <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc1_pwren: sdmmc1-pwren {
+ rockchip,pins =
+ <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc1_wrprt: sdmmc1-wrprt {
+ rockchip,pins =
+ <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc1_dectn: sdmmc1-dectn {
+ rockchip,pins =
+ <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc1_bus1: sdmmc1-bus1 {
+ rockchip,pins =
+ <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc1_bus4: sdmmc1-bus4 {
+ rockchip,pins =
+ <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
+ <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
+ <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
+ <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
+ };
+
+ sdmmc1_gpio: sdmmc1-gpio {
+ rockchip,pins =
+ <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
+ };
+ };
+
+ emmc {
+ emmc_clk: emmc-clk {
+ rockchip,pins =
+ <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
+ };
+
+ emmc_cmd: emmc-cmd {
+ rockchip,pins =
+ <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
+ };
+
+ emmc_pwren: emmc-pwren {
+ rockchip,pins =
+ <3 22 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ emmc_rstnout: emmc-rstnout {
+ rockchip,pins =
+ <3 20 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ emmc_bus1: emmc-bus1 {
+ rockchip,pins =
+ <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
+ };
+
+ emmc_bus4: emmc-bus4 {
+ rockchip,pins =
+ <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
+ <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
+ <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
+ <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
+ };
+
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+ <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
+ <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
+ <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
+ <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
+ <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
+ <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
+ <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
+ <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
+ };
+ };
+
+ pwm0 {
+ pwm0_pin: pwm0-pin {
+ rockchip,pins =
+ <2 4 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ pwm1_pin: pwm1-pin {
+ rockchip,pins =
+ <2 5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ pwm2_pin: pwm2-pin {
+ rockchip,pins =
+ <2 6 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ pwmir {
+ pwmir_pin: pwmir-pin {
+ rockchip,pins =
+ <2 2 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ gmac-0 {
+ rgmiim0_pins: rgmiim0-pins {
+ rockchip,pins =
+ /* mac_txclk */
+ <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_rxclk */
+ <0 10 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdio */
+ <0 11 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txen */
+ <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_clk */
+ <0 24 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxdv */
+ <0 25 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdc */
+ <0 19 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd1 */
+ <0 14 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd0 */
+ <0 15 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_txd0 */
+ <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_rxd3 */
+ <0 20 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd2 */
+ <0 21 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_txd2 */
+ <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
+ };
+
+ rmiim0_pins: rmiim0-pins {
+ rockchip,pins =
+ /* mac_mdio */
+ <0 11 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txen */
+ <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_clk */
+ <0 24 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxer */
+ <0 13 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxdv */
+ <0 25 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdc */
+ <0 19 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd1 */
+ <0 14 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd0 */
+ <0 15 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
+ /* mac_txd0 */
+ <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
+ };
+ };
+
+ gmac-1 {
+ rgmiim1_pins: rgmiim1-pins {
+ rockchip,pins =
+ /* mac_txclk */
+ <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
+ /* mac_rxclk */
+ <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ /* mac_mdio */
+ <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ /* mac_txen */
+ <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
+ /* mac_clk */
+ <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ /* mac_rxdv */
+ <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ /* mac_mdc */
+ <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ /* mac_rxd1 */
+ <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ /* mac_rxd0 */
+ <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ /* mac_txd1 */
+ <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
+ /* mac_txd0 */
+ <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
+ /* mac_rxd3 */
+ <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ /* mac_rxd2 */
+ <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ /* mac_txd3 */
+ <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
+ /* mac_txd2 */
+ <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
+
+ /* mac_txclk */
+ <0 8 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txen */
+ <0 12 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_clk */
+ <0 24 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <0 16 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd0 */
+ <0 17 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <0 23 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd2 */
+ <0 22 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ rmiim1_pins: rmiim1-pins {
+ rockchip,pins =
+ /* mac_mdio */
+ <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ /* mac_txen */
+ <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
+ /* mac_clk */
+ <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ /* mac_rxer */
+ <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ /* mac_rxdv */
+ <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ /* mac_mdc */
+ <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ /* mac_rxd1 */
+ <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ /* mac_rxd0 */
+ <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
+ /* mac_txd1 */
+ <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
+ /* mac_txd0 */
+ <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
+
+ /* mac_mdio */
+ <0 11 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txen */
+ <0 12 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_clk */
+ <0 24 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdc */
+ <0 19 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <0 16 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd0 */
+ <0 17 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ gmac2phy {
+ fephyled_speed100: fephyled-speed100 {
+ rockchip,pins =
+ <0 31 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ fephyled_speed10: fephyled-speed10 {
+ rockchip,pins =
+ <0 30 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ fephyled_duplex: fephyled-duplex {
+ rockchip,pins =
+ <0 30 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ fephyled_rxm0: fephyled-rxm0 {
+ rockchip,pins =
+ <0 29 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ fephyled_txm0: fephyled-txm0 {
+ rockchip,pins =
+ <0 29 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ fephyled_linkm0: fephyled-linkm0 {
+ rockchip,pins =
+ <0 28 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ fephyled_rxm1: fephyled-rxm1 {
+ rockchip,pins =
+ <2 25 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ fephyled_txm1: fephyled-txm1 {
+ rockchip,pins =
+ <2 25 RK_FUNC_3 &pcfg_pull_none>;
+ };
+
+ fephyled_linkm1: fephyled-linkm1 {
+ rockchip,pins =
+ <2 24 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ tsadc_pin {
+ tsadc_int: tsadc-int {
+ rockchip,pins =
+ <2 13 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ tsadc_gpio: tsadc-gpio {
+ rockchip,pins =
+ <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ hdmi_pin {
+ hdmi_cec: hdmi-cec {
+ rockchip,pins =
+ <0 3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ hdmi_hpd: hdmi-hpd {
+ rockchip,pins =
+ <0 4 RK_FUNC_1 &pcfg_pull_down>;
+ };
+ };
+
+ cif-0 {
+ dvp_d2d9_m0:dvp-d2d9-m0 {
+ rockchip,pins =
+ /* cif_d0 */
+ <3 4 RK_FUNC_2 &pcfg_pull_none>,
+ /* cif_d1 */
+ <3 5 RK_FUNC_2 &pcfg_pull_none>,
+ /* cif_d2 */
+ <3 6 RK_FUNC_2 &pcfg_pull_none>,
+ /* cif_d3 */
+ <3 7 RK_FUNC_2 &pcfg_pull_none>,
+ /* cif_d4 */
+ <3 8 RK_FUNC_2 &pcfg_pull_none>,
+ /* cif_d5m0 */
+ <3 9 RK_FUNC_2 &pcfg_pull_none>,
+ /* cif_d6m0 */
+ <3 10 RK_FUNC_2 &pcfg_pull_none>,
+ /* cif_d7m0 */
+ <3 11 RK_FUNC_2 &pcfg_pull_none>,
+ /* cif_href */
+ <3 1 RK_FUNC_2 &pcfg_pull_none>,
+ /* cif_vsync */
+ <3 0 RK_FUNC_2 &pcfg_pull_none>,
+ /* cif_clkoutm0 */
+ <3 3 RK_FUNC_2 &pcfg_pull_none>,
+ /* cif_clkin */
+ <3 2 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ cif-1 {
+ dvp_d2d9_m1:dvp-d2d9-m1 {
+ rockchip,pins =
+ /* cif_d0 */
+ <3 4 RK_FUNC_2 &pcfg_pull_none>,
+ /* cif_d1 */
+ <3 5 RK_FUNC_2 &pcfg_pull_none>,
+ /* cif_d2 */
+ <3 6 RK_FUNC_2 &pcfg_pull_none>,
+ /* cif_d3 */
+ <3 7 RK_FUNC_2 &pcfg_pull_none>,
+ /* cif_d4 */
+ <3 8 RK_FUNC_2 &pcfg_pull_none>,
+ /* cif_d5m1 */
+ <2 16 RK_FUNC_4 &pcfg_pull_none>,
+ /* cif_d6m1 */
+ <2 17 RK_FUNC_4 &pcfg_pull_none>,
+ /* cif_d7m1 */
+ <2 18 RK_FUNC_4 &pcfg_pull_none>,
+ /* cif_href */
+ <3 1 RK_FUNC_2 &pcfg_pull_none>,
+ /* cif_vsync */
+ <3 0 RK_FUNC_2 &pcfg_pull_none>,
+ /* cif_clkoutm1 */
+ <2 15 RK_FUNC_4 &pcfg_pull_none>,
+ /* cif_clkin */
+ <3 2 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+ };
+};
diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h
new file mode 100644
index 0000000..6d8bf13
--- /dev/null
+++ b/include/dt-bindings/clock/rk3328-cru.h
@@ -0,0 +1,394 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
+
+/* core clocks */
+#define PLL_APLL 1
+#define PLL_DPLL 2
+#define PLL_CPLL 3
+#define PLL_GPLL 4
+#define PLL_NPLL 5
+#define ARMCLK 6
+
+/* sclk gates (special clocks) */
+#define SCLK_RTC32K 30
+#define SCLK_SDMMC_EXT 31
+#define SCLK_SPI 32
+#define SCLK_SDMMC 33
+#define SCLK_SDIO 34
+#define SCLK_EMMC 35
+#define SCLK_TSADC 36
+#define SCLK_SARADC 37
+#define SCLK_UART0 38
+#define SCLK_UART1 39
+#define SCLK_UART2 40
+#define SCLK_I2S0 41
+#define SCLK_I2S1 42
+#define SCLK_I2S2 43
+#define SCLK_I2S1_OUT 44
+#define SCLK_I2S2_OUT 45
+#define SCLK_SPDIF 46
+#define SCLK_TIMER0 47
+#define SCLK_TIMER1 48
+#define SCLK_TIMER2 49
+#define SCLK_TIMER3 50
+#define SCLK_TIMER4 51
+#define SCLK_TIMER5 52
+#define SCLK_WIFI 53
+#define SCLK_CIF_OUT 54
+#define SCLK_I2C0 55
+#define SCLK_I2C1 56
+#define SCLK_I2C2 57
+#define SCLK_I2C3 58
+#define SCLK_CRYPTO 59
+#define SCLK_PWM 60
+#define SCLK_PDM 61
+#define SCLK_EFUSE 62
+#define SCLK_OTP 63
+#define SCLK_DDRCLK 64
+#define SCLK_VDEC_CABAC 65
+#define SCLK_VDEC_CORE 66
+#define SCLK_VENC_DSP 67
+#define SCLK_VENC_CORE 68
+#define SCLK_RGA 69
+#define SCLK_HDMI_SFC 70
+#define SCLK_HDMI_CEC 71
+#define SCLK_USB3_REF 72
+#define SCLK_USB3_SUSPEND 73
+#define SCLK_SDMMC_DRV 74
+#define SCLK_SDIO_DRV 75
+#define SCLK_EMMC_DRV 76
+#define SCLK_SDMMC_EXT_DRV 77
+#define SCLK_SDMMC_SAMPLE 78
+#define SCLK_SDIO_SAMPLE 79
+#define SCLK_EMMC_SAMPLE 80
+#define SCLK_SDMMC_EXT_SAMPLE 81
+#define SCLK_VOP 82
+#define SCLK_MAC2PHY_RXTX 83
+#define SCLK_MAC2PHY_SRC 84
+#define SCLK_MAC2PHY_REF 85
+#define SCLK_MAC2PHY_OUT 86
+#define SCLK_MAC2IO_RX 87
+#define SCLK_MAC2IO_TX 88
+#define SCLK_MAC2IO_REFOUT 89
+#define SCLK_MAC2IO_REF 90
+#define SCLK_MAC2IO_OUT 91
+#define SCLK_TSP 92
+#define SCLK_HSADC_TSP 93
+#define SCLK_USB3PHY_REF 94
+#define SCLK_REF_USB3OTG 95
+#define SCLK_USB3OTG_REF 96
+#define SCLK_USB3OTG_SUSPEND 97
+#define SCLK_REF_USB3OTG_SRC 98
+#define SCLK_MAC2IO_SRC 99
+
+/* dclk gates */
+#define DCLK_LCDC 180
+#define DCLK_HDMIPHY 181
+#define HDMIPHY 182
+#define USB480M 183
+#define DCLK_LCDC_SRC 184
+
+/* aclk gates */
+#define ACLK_AXISRAM 190
+#define ACLK_VOP_PRE 191
+#define ACLK_USB3OTG 192
+#define ACLK_RGA_PRE 193
+#define ACLK_DMAC 194
+#define ACLK_GPU 195
+#define ACLK_BUS_PRE 196
+#define ACLK_PERI_PRE 197
+#define ACLK_RKVDEC_PRE 198
+#define ACLK_RKVDEC 199
+#define ACLK_RKVENC 200
+#define ACLK_VPU_PRE 201
+#define ACLK_VIO_PRE 202
+#define ACLK_VPU 203
+#define ACLK_VIO 204
+#define ACLK_VOP 205
+#define ACLK_GMAC 206
+#define ACLK_H265 207
+#define ACLK_H264 208
+#define ACLK_MAC2PHY 209
+#define ACLK_MAC2IO 210
+#define ACLK_DCF 211
+#define ACLK_TSP 212
+#define ACLK_PERI 213
+#define ACLK_RGA 214
+#define ACLK_IEP 215
+#define ACLK_CIF 216
+#define ACLK_HDCP 217
+
+/* pclk gates */
+#define PCLK_GPIO0 300
+#define PCLK_GPIO1 301
+#define PCLK_GPIO2 302
+#define PCLK_GPIO3 303
+#define PCLK_GRF 304
+#define PCLK_I2C0 305
+#define PCLK_I2C1 306
+#define PCLK_I2C2 307
+#define PCLK_I2C3 308
+#define PCLK_SPI 309
+#define PCLK_UART0 310
+#define PCLK_UART1 311
+#define PCLK_UART2 312
+#define PCLK_TSADC 313
+#define PCLK_PWM 314
+#define PCLK_TIMER 315
+#define PCLK_BUS_PRE 316
+#define PCLK_PERI_PRE 317
+#define PCLK_HDMI_CTRL 318
+#define PCLK_HDMI_PHY 319
+#define PCLK_GMAC 320
+#define PCLK_H265 321
+#define PCLK_MAC2PHY 322
+#define PCLK_MAC2IO 323
+#define PCLK_USB3PHY_OTG 324
+#define PCLK_USB3PHY_PIPE 325
+#define PCLK_USB3_GRF 326
+#define PCLK_USB2_GRF 327
+#define PCLK_HDMIPHY 328
+#define PCLK_DDR 329
+#define PCLK_PERI 330
+#define PCLK_HDMI 331
+#define PCLK_HDCP 332
+#define PCLK_DCF 333
+#define PCLK_SARADC 334
+
+/* hclk gates */
+#define HCLK_PERI 408
+#define HCLK_TSP 409
+#define HCLK_GMAC 410
+#define HCLK_I2S0_8CH 411
+#define HCLK_I2S1_8CH 413
+#define HCLK_I2S2_2CH 413
+#define HCLK_SPDIF_8CH 414
+#define HCLK_VOP 415
+#define HCLK_NANDC 416
+#define HCLK_SDMMC 417
+#define HCLK_SDIO 418
+#define HCLK_EMMC 419
+#define HCLK_SDMMC_EXT 420
+#define HCLK_RKVDEC_PRE 421
+#define HCLK_RKVDEC 422
+#define HCLK_RKVENC 423
+#define HCLK_VPU_PRE 424
+#define HCLK_VIO_PRE 425
+#define HCLK_VPU 426
+#define HCLK_VIO 427
+#define HCLK_BUS_PRE 428
+#define HCLK_PERI_PRE 429
+#define HCLK_H264 430
+#define HCLK_CIF 431
+#define HCLK_OTG_PMU 432
+#define HCLK_OTG 433
+#define HCLK_HOST0 434
+#define HCLK_HOST0_ARB 435
+#define HCLK_CRYPTO_MST 436
+#define HCLK_CRYPTO_SLV 437
+#define HCLK_PDM 438
+#define HCLK_IEP 439
+#define HCLK_RGA 440
+#define HCLK_HDCP 441
+
+#define CLK_NR_CLKS (HCLK_HDCP + 1)
+
+#define SCLK_MAC2IO 0
+#define SCLK_MAC2PHY 1
+
+#define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0_PO 0
+#define SRST_CORE1_PO 1
+#define SRST_CORE2_PO 2
+#define SRST_CORE3_PO 3
+#define SRST_CORE0 4
+#define SRST_CORE1 5
+#define SRST_CORE2 6
+#define SRST_CORE3 7
+#define SRST_CORE0_DBG 8
+#define SRST_CORE1_DBG 9
+#define SRST_CORE2_DBG 10
+#define SRST_CORE3_DBG 11
+#define SRST_TOPDBG 12
+#define SRST_CORE_NIU 13
+#define SRST_STRC_A 14
+#define SRST_L2C 15
+
+#define SRST_A53_GIC 18
+#define SRST_DAP 19
+#define SRST_PMU_P 21
+#define SRST_EFUSE 22
+#define SRST_BUSSYS_H 23
+#define SRST_BUSSYS_P 24
+#define SRST_SPDIF 25
+#define SRST_INTMEM 26
+#define SRST_ROM 27
+#define SRST_GPIO0 28
+#define SRST_GPIO1 29
+#define SRST_GPIO2 30
+#define SRST_GPIO3 31
+
+#define SRST_I2S0 32
+#define SRST_I2S1 33
+#define SRST_I2S2 34
+#define SRST_I2S0_H 35
+#define SRST_I2S1_H 36
+#define SRST_I2S2_H 37
+#define SRST_UART0 38
+#define SRST_UART1 39
+#define SRST_UART2 40
+#define SRST_UART0_P 41
+#define SRST_UART1_P 42
+#define SRST_UART2_P 43
+#define SRST_I2C0 44
+#define SRST_I2C1 45
+#define SRST_I2C2 46
+#define SRST_I2C3 47
+
+#define SRST_I2C0_P 48
+#define SRST_I2C1_P 49
+#define SRST_I2C2_P 50
+#define SRST_I2C3_P 51
+#define SRST_EFUSE_SE_P 52
+#define SRST_EFUSE_NS_P 53
+#define SRST_PWM0 54
+#define SRST_PWM0_P 55
+#define SRST_DMA 56
+#define SRST_TSP_A 57
+#define SRST_TSP_H 58
+#define SRST_TSP 59
+#define SRST_TSP_HSADC 60
+#define SRST_DCF_A 61
+#define SRST_DCF_P 62
+
+#define SRST_SCR 64
+#define SRST_SPI 65
+#define SRST_TSADC 66
+#define SRST_TSADC_P 67
+#define SRST_CRYPTO 68
+#define SRST_SGRF 69
+#define SRST_GRF 70
+#define SRST_USB_GRF 71
+#define SRST_TIMER_6CH_P 72
+#define SRST_TIMER0 73
+#define SRST_TIMER1 74
+#define SRST_TIMER2 75
+#define SRST_TIMER3 76
+#define SRST_TIMER4 77
+#define SRST_TIMER5 78
+#define SRST_USB3GRF 79
+
+#define SRST_PHYNIU 80
+#define SRST_HDMIPHY 81
+#define SRST_VDAC 82
+#define SRST_ACODEC_p 83
+#define SRST_SARADC 85
+#define SRST_SARADC_P 86
+#define SRST_GRF_DDR 87
+#define SRST_DFIMON 88
+#define SRST_MSCH 89
+#define SRST_DDRMSCH 91
+#define SRST_DDRCTRL 92
+#define SRST_DDRCTRL_P 93
+#define SRST_DDRPHY 94
+#define SRST_DDRPHY_P 95
+
+#define SRST_GMAC_NIU_A 96
+#define SRST_GMAC_NIU_P 97
+#define SRST_GMAC2PHY_A 98
+#define SRST_GMAC2IO_A 99
+#define SRST_MACPHY 100
+#define SRST_OTP_PHY 101
+#define SRST_GPU_A 102
+#define SRST_GPU_NIU_A 103
+#define SRST_SDMMCEXT 104
+#define SRST_PERIPH_NIU_A 105
+#define SRST_PERIHP_NIU_H 106
+#define SRST_PERIHP_P 107
+#define SRST_PERIPHSYS_H 108
+#define SRST_MMC0 109
+#define SRST_SDIO 110
+#define SRST_EMMC 111
+
+#define SRST_USB2OTG_H 112
+#define SRST_USB2OTG 113
+#define SRST_USB2OTG_ADP 114
+#define SRST_USB2HOST_H 115
+#define SRST_USB2HOST_ARB 116
+#define SRST_USB2HOST_AUX 117
+#define SRST_USB2HOST_EHCIPHY 118
+#define SRST_USB2HOST_UTMI 119
+#define SRST_USB3OTG 120
+#define SRST_USBPOR 121
+#define SRST_USB2OTG_UTMI 122
+#define SRST_USB2HOST_PHY_UTMI 123
+#define SRST_USB3OTG_UTMI 124
+#define SRST_USB3PHY_U2 125
+#define SRST_USB3PHY_U3 126
+#define SRST_USB3PHY_PIPE 127
+
+#define SRST_VIO_A 128
+#define SRST_VIO_BUS_H 129
+#define SRST_VIO_H2P_H 130
+#define SRST_VIO_ARBI_H 131
+#define SRST_VOP_NIU_A 132
+#define SRST_VOP_A 133
+#define SRST_VOP_H 134
+#define SRST_VOP_D 135
+#define SRST_RGA 136
+#define SRST_RGA_NIU_A 137
+#define SRST_RGA_A 138
+#define SRST_RGA_H 139
+#define SRST_IEP_A 140
+#define SRST_IEP_H 141
+#define SRST_HDMI 142
+#define SRST_HDMI_P 143
+
+#define SRST_HDCP_A 144
+#define SRST_HDCP 145
+#define SRST_HDCP_H 146
+#define SRST_CIF_A 147
+#define SRST_CIF_H 148
+#define SRST_CIF_P 149
+#define SRST_OTP_P 150
+#define SRST_OTP_SBPI 151
+#define SRST_OTP_USER 152
+#define SRST_DDRCTRL_A 153
+#define SRST_DDRSTDY_P 154
+#define SRST_DDRSTDY 155
+#define SRST_PDM_H 156
+#define SRST_PDM 157
+#define SRST_USB3PHY_OTG_P 158
+#define SRST_USB3PHY_PIPE_P 159
+
+#define SRST_VCODEC_A 160
+#define SRST_VCODEC_NIU_A 161
+#define SRST_VCODEC_H 162
+#define SRST_VCODEC_NIU_H 163
+#define SRST_VDEC_A 164
+#define SRST_VDEC_NIU_A 165
+#define SRST_VDEC_H 166
+#define SRST_VDEC_NIU_H 167
+#define SRST_VDEC_CORE 168
+#define SRST_VDEC_CABAC 169
+#define SRST_DDRPHYDIV 175
+
+#define SRST_RKVENC_NIU_A 176
+#define SRST_RKVENC_NIU_H 177
+#define SRST_RKVENC_H265_A 178
+#define SRST_RKVENC_H265_P 179
+#define SRST_RKVENC_H265_CORE 180
+#define SRST_RKVENC_H265_DSP 181
+#define SRST_RKVENC_H264_A 182
+#define SRST_RKVENC_H264_H 183
+#define SRST_RKVENC_INTMEM 184
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [U-Boot] [PATCH 1/7] arm64: dts: add support for Rockchip rk3328 soc
2017-02-17 8:07 ` [U-Boot] [PATCH 1/7] arm64: dts: add support for Rockchip rk3328 soc Kever Yang
@ 2017-02-21 18:06 ` Simon Glass
0 siblings, 0 replies; 18+ messages in thread
From: Simon Glass @ 2017-02-21 18:06 UTC (permalink / raw)
To: u-boot
On 17 February 2017 at 01:07, Kever Yang <kever.yang@rock-chips.com> wrote:
> Add dts binding header for rk3328, files origin from kernel.
>
> Signed-off-by: William Zhang <william.zhang@rock-chips.com>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3328-evb.dts | 45 +
> arch/arm/dts/rk3328.dtsi | 1477 ++++++++++++++++++++++++++++++++
> include/dt-bindings/clock/rk3328-cru.h | 394 +++++++++
> 4 files changed, 1917 insertions(+)
> create mode 100644 arch/arm/dts/rk3328-evb.dts
> create mode 100644 arch/arm/dts/rk3328.dtsi
> create mode 100644 include/dt-bindings/clock/rk3328-cru.h
Acked-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 2/7] ARM64: rockchip: add support for rk3328 SoC
2017-02-17 8:07 [U-Boot] [PATCH 0/7] add support for rk3328 SoC Kever Yang
2017-02-17 8:07 ` [U-Boot] [PATCH 1/7] arm64: dts: add support for Rockchip rk3328 soc Kever Yang
@ 2017-02-17 8:07 ` Kever Yang
2017-02-21 18:06 ` Simon Glass
2017-02-17 8:07 ` [U-Boot] [PATCH 3/7] clk: rockchip: add support for rk3328 Kever Yang
` (5 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Kever Yang @ 2017-02-17 8:07 UTC (permalink / raw)
To: u-boot
RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU.
It supports two USB2.0 EHCI ports. Other interfaces are very
much like RK3288, the DRAM are 32bit width address and support
address from 0 to 4GB-16MB range.
Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm/mach-rockchip/Kconfig | 11 +++++
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rk3328/Kconfig | 23 ++++++++++
arch/arm/mach-rockchip/rk3328/Makefile | 8 ++++
arch/arm/mach-rockchip/rk3328/rk3328.c | 39 ++++++++++++++++
arch/arm/mach-rockchip/rk3328/syscon_rk3328.c | 20 +++++++++
include/configs/rk3328_common.h | 65 +++++++++++++++++++++++++++
7 files changed, 167 insertions(+)
create mode 100644 arch/arm/mach-rockchip/rk3328/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk3328/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3328/rk3328.c
create mode 100644 arch/arm/mach-rockchip/rk3328/syscon_rk3328.c
create mode 100644 include/configs/rk3328_common.h
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 5c4a4c2..9c01971 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -23,6 +23,16 @@ config ROCKCHIP_RK3288
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+config ROCKCHIP_RK3328
+ bool "Support Rockchip RK3328"
+ select ARM64
+ help
+ The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
+ including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
+ video interfaces supporting HDMI and eDP, several DDR3 options
+ and video codec support. Peripherals include Gigabit Ethernet,
+ USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+
config ROCKCHIP_RK3399
bool "Support Rockchip RK3399"
select ARM64
@@ -47,5 +57,6 @@ config SPL_MMC_SUPPORT
source "arch/arm/mach-rockchip/rk3036/Kconfig"
source "arch/arm/mach-rockchip/rk3288/Kconfig"
+source "arch/arm/mach-rockchip/rk3328/Kconfig"
source "arch/arm/mach-rockchip/rk3399/Kconfig"
endif
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 6e79fed..49d90b9 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -17,4 +17,5 @@ obj-y += rk_timer.o
endif
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
+obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig
new file mode 100644
index 0000000..43afba2
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3328/Kconfig
@@ -0,0 +1,23 @@
+if ROCKCHIP_RK3328
+
+choice
+ prompt "RK3328 board select"
+
+config TARGET_EVB_RK3328
+ bool "RK3328 evaluation board"
+ help
+ RK3328evb is a evaluation board for Rockchip rk3328,
+ with full function and phisical connectors support like
+ usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial...
+
+endchoice
+
+config SYS_SOC
+ default "rockchip"
+
+config SYS_MALLOC_F_LEN
+ default 0x0800
+
+source "board/rockchip/evb_rk3328/Kconfig"
+
+endif
diff --git a/arch/arm/mach-rockchip/rk3328/Makefile b/arch/arm/mach-rockchip/rk3328/Makefile
new file mode 100644
index 0000000..8ecf8ee
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3328/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += rk3328.o
+obj-y += syscon_rk3328.o
diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c
new file mode 100644
index 0000000..857f014
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3328/rk3328.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+
+static struct mm_region rk3328_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf0000000UL,
+ .phys = 0xf0000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = rk3328_mem_map;
+
+int arch_cpu_init(void)
+{
+ /* We do some SoC one time setting here. */
+
+ return 0;
+}
diff --git a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c
new file mode 100644
index 0000000..a1a368f
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c
@@ -0,0 +1,20 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <dm.h>
+#include <syscon.h>
+
+static const struct udevice_id rk3328_syscon_ids[] = {
+ { .compatible = "rockchip,rk3328-grf", .data = ROCKCHIP_SYSCON_GRF },
+};
+
+U_BOOT_DRIVER(syscon_rk3328) = {
+ .name = "rk3328_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3328_syscon_ids,
+};
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
new file mode 100644
index 0000000..eacf716
--- /dev/null
+++ b/include/configs/rk3328_common.h
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_RK3328_COMMON_H
+#define __CONFIG_RK3328_COMMON_H
+
+#include "rockchip-common.h"
+
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_BAUDRATE 1500000
+#define CONFIG_SYS_MALLOC_LEN (32 << 20)
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_SYS_TEXT_BASE 0x00200000
+#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
+#define CONFIG_SYS_LOAD_ADDR 0x00800800
+
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
+
+/* MMC/SD IP block */
+#define CONFIG_BOUNCE_BUFFER
+
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_FS_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_FS_EXT4
+
+/* RAW SD card / eMMC locations. */
+#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
+
+/* FAT sd card locations. */
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SYS_SDRAM_BASE 0
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI
+#define CONFIG_SF_DEFAULT_SPEED 20000000
+
+#ifndef CONFIG_SPL_BUILD
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x00500000\0" \
+ "pxefile_addr_r=0x00600000\0" \
+ "fdt_addr_r=0x01f00000\0" \
+ "kernel_addr_r=0x02000000\0" \
+ "ramdisk_addr_r=0x04000000\0"
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ ENV_MEM_LAYOUT_SETTINGS \
+ "partitions=" PARTS_DEFAULT \
+ BOOTENV
+
+#endif
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [U-Boot] [PATCH 2/7] ARM64: rockchip: add support for rk3328 SoC
2017-02-17 8:07 ` [U-Boot] [PATCH 2/7] ARM64: rockchip: add support for rk3328 SoC Kever Yang
@ 2017-02-21 18:06 ` Simon Glass
0 siblings, 0 replies; 18+ messages in thread
From: Simon Glass @ 2017-02-21 18:06 UTC (permalink / raw)
To: u-boot
On 17 February 2017 at 01:07, Kever Yang <kever.yang@rock-chips.com> wrote:
> RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU.
> It supports two USB2.0 EHCI ports. Other interfaces are very
> much like RK3288, the DRAM are 32bit width address and support
> address from 0 to 4GB-16MB range.
>
> Signed-off-by: William Zhang <william.zhang@rock-chips.com>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> arch/arm/mach-rockchip/Kconfig | 11 +++++
> arch/arm/mach-rockchip/Makefile | 1 +
> arch/arm/mach-rockchip/rk3328/Kconfig | 23 ++++++++++
> arch/arm/mach-rockchip/rk3328/Makefile | 8 ++++
> arch/arm/mach-rockchip/rk3328/rk3328.c | 39 ++++++++++++++++
> arch/arm/mach-rockchip/rk3328/syscon_rk3328.c | 20 +++++++++
> include/configs/rk3328_common.h | 65 +++++++++++++++++++++++++++
> 7 files changed, 167 insertions(+)
> create mode 100644 arch/arm/mach-rockchip/rk3328/Kconfig
> create mode 100644 arch/arm/mach-rockchip/rk3328/Makefile
> create mode 100644 arch/arm/mach-rockchip/rk3328/rk3328.c
> create mode 100644 arch/arm/mach-rockchip/rk3328/syscon_rk3328.c
> create mode 100644 include/configs/rk3328_common.h
Acked-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 3/7] clk: rockchip: add support for rk3328
2017-02-17 8:07 [U-Boot] [PATCH 0/7] add support for rk3328 SoC Kever Yang
2017-02-17 8:07 ` [U-Boot] [PATCH 1/7] arm64: dts: add support for Rockchip rk3328 soc Kever Yang
2017-02-17 8:07 ` [U-Boot] [PATCH 2/7] ARM64: rockchip: add support for rk3328 SoC Kever Yang
@ 2017-02-17 8:07 ` Kever Yang
2017-02-21 18:06 ` Simon Glass
2017-02-17 8:07 ` [U-Boot] [PATCH 4/7] pinctrl: " Kever Yang
` (4 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Kever Yang @ 2017-02-17 8:07 UTC (permalink / raw)
To: u-boot
Add rk3328 clock driver and cru structure definition.
Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/cru_rk3328.h | 65 +++
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk_rk3328.c | 607 ++++++++++++++++++++++++
3 files changed, 673 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3328.h
create mode 100644 drivers/clk/rockchip/clk_rk3328.c
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
new file mode 100644
index 0000000..089c4ca
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CRU_RK3328_H_
+#define __ASM_ARCH_CRU_RK3328_H_
+
+#include <common.h>
+
+struct rk3328_cru {
+ u32 apll_con[5];
+ u32 reserved1[3];
+ u32 dpll_con[5];
+ u32 reserved2[3];
+ u32 cpll_con[5];
+ u32 reserved3[3];
+ u32 gpll_con[5];
+ u32 reserved4[3];
+ u32 mode_con;
+ u32 misc;
+ u32 reserved5[2];
+ u32 glb_cnt_th;
+ u32 glb_rst_st;
+ u32 glb_srst_snd_value;
+ u32 glb_srst_fst_value;
+ u32 npll_con[5];
+ u32 reserved6[(0x100-0xb4)/4];
+ u32 clksel_con[53];
+ u32 reserved7[(0x200-0x1d4)/4];
+ u32 clkgate_con[29];
+ u32 reserved8[3];
+ u32 ssgtbl[32];
+ u32 softrst_con[12];
+ u32 reserved9[(0x380-0x330)/4];
+ u32 sdmmc_con[2];
+ u32 sdio_con[2];
+ u32 emmc_con[2];
+ u32 sdmmc_ext_con[2];
+};
+check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c);
+#define MHz 1000000
+#define KHz 1000
+#define OSC_HZ (24 * MHz)
+#define APLL_HZ (600 * MHz)
+#define GPLL_HZ (576 * MHz)
+#define CPLL_HZ (594 * MHz)
+
+#define CLK_CORE_HZ (600 * MHz)
+#define ACLKM_CORE_HZ (300 * MHz)
+#define PCLK_DBG_HZ (300 * MHz)
+
+#define PERIHP_ACLK_HZ (144000 * KHz)
+#define PERIHP_HCLK_HZ (72000 * KHz)
+#define PERIHP_PCLK_HZ (72000 * KHz)
+
+#define PWM_CLOCK_HZ (74 * MHz)
+
+enum apll_frequencies {
+ APLL_816_MHZ,
+ APLL_600_MHZ,
+};
+
+#endif /* __ASM_ARCH_CRU_RK3328_H_ */
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 1f8e417..c4e81e9 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -6,4 +6,5 @@
obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
new file mode 100644
index 0000000..e075414
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -0,0 +1,607 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3328.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/rk3328-cru.h>
+#include <errno.h>
+#include <syscon.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rk3328_clk_priv {
+ struct rk3328_cru *cru;
+ ulong rate;
+};
+
+struct pll_div {
+ u32 refdiv;
+ u32 fbdiv;
+ u32 postdiv1;
+ u32 postdiv2;
+ u32 frac;
+};
+
+#define RATE_TO_DIV(input_rate, output_rate) \
+ ((input_rate) / (output_rate) - 1);
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
+
+#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
+ .refdiv = _refdiv,\
+ .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
+ .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
+
+static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1);
+static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
+
+static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1);
+static const struct pll_div apll_600_cfg = PLL_DIVISORS(600 * MHz, 1, 3, 1);
+
+static const struct pll_div *apll_cfgs[] = {
+ [APLL_816_MHZ] = &apll_816_cfg,
+ [APLL_600_MHZ] = &apll_600_cfg,
+};
+
+enum {
+ /* PLL_CON0 */
+ PLL_POSTDIV1_SHIFT = 12,
+ PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
+ PLL_FBDIV_SHIFT = 0,
+ PLL_FBDIV_MASK = 0xfff,
+
+ /* PLL_CON1 */
+ PLL_DSMPD_SHIFT = 12,
+ PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
+ PLL_INTEGER_MODE = 1,
+ PLL_LOCK_STATUS_SHIFT = 10,
+ PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
+ PLL_POSTDIV2_SHIFT = 6,
+ PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,
+ PLL_REFDIV_SHIFT = 0,
+ PLL_REFDIV_MASK = 0x3f,
+
+ /* PLL_CON2 */
+ PLL_FRACDIV_SHIFT = 0,
+ PLL_FRACDIV_MASK = 0xffffff,
+
+ /* MODE_CON */
+ APLL_MODE_SHIFT = 0,
+ NPLL_MODE_SHIFT = 1,
+ DPLL_MODE_SHIFT = 4,
+ CPLL_MODE_SHIFT = 8,
+ GPLL_MODE_SHIFT = 12,
+ PLL_MODE_SLOW = 0,
+ PLL_MODE_NORM,
+
+ /* CLKSEL_CON0 */
+ CLK_CORE_PLL_SEL_APLL = 0,
+ CLK_CORE_PLL_SEL_GPLL,
+ CLK_CORE_PLL_SEL_DPLL,
+ CLK_CORE_PLL_SEL_NPLL,
+ CLK_CORE_PLL_SEL_SHIFT = 6,
+ CLK_CORE_PLL_SEL_MASK = 3 << CLK_CORE_PLL_SEL_SHIFT,
+ CLK_CORE_DIV_SHIFT = 0,
+ CLK_CORE_DIV_MASK = 0x1f,
+
+ /* CLKSEL_CON1 */
+ ACLKM_CORE_DIV_SHIFT = 4,
+ ACLKM_CORE_DIV_MASK = 0x7 << ACLKM_CORE_DIV_SHIFT,
+ PCLK_DBG_DIV_SHIFT = 0,
+ PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT,
+
+ /* CLKSEL_CON28 */
+ ACLK_PERIHP_PLL_SEL_CPLL = 0,
+ ACLK_PERIHP_PLL_SEL_GPLL,
+ ACLK_PERIHP_PLL_SEL_HDMIPHY,
+ ACLK_PERIHP_PLL_SEL_SHIFT = 6,
+ ACLK_PERIHP_PLL_SEL_MASK = 3 << ACLK_PERIHP_PLL_SEL_SHIFT,
+ ACLK_PERIHP_DIV_CON_SHIFT = 0,
+ ACLK_PERIHP_DIV_CON_MASK = 0x1f,
+
+ /* CLKSEL_CON29 */
+ PCLK_PERIHP_DIV_CON_SHIFT = 4,
+ PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
+ HCLK_PERIHP_DIV_CON_SHIFT = 0,
+ HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
+
+ /* CLKSEL_CON22 */
+ CLK_TSADC_DIV_CON_SHIFT = 0,
+ CLK_TSADC_DIV_CON_MASK = 0x3ff,
+
+ /* CLKSEL_CON23 */
+ CLK_SARADC_DIV_CON_SHIFT = 0,
+ CLK_SARADC_DIV_CON_MASK = 0x3ff << CLK_SARADC_DIV_CON_SHIFT,
+
+ /* CLKSEL_CON24 */
+ CLK_PWM_PLL_SEL_CPLL = 0,
+ CLK_PWM_PLL_SEL_GPLL,
+ CLK_PWM_PLL_SEL_SHIFT = 15,
+ CLK_PWM_PLL_SEL_MASK = 1 << CLK_PWM_PLL_SEL_SHIFT,
+ CLK_PWM_DIV_CON_SHIFT = 8,
+ CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT,
+
+ CLK_SPI_PLL_SEL_CPLL = 0,
+ CLK_SPI_PLL_SEL_GPLL,
+ CLK_SPI_PLL_SEL_SHIFT = 7,
+ CLK_SPI_PLL_SEL_MASK = 1 << CLK_SPI_PLL_SEL_SHIFT,
+ CLK_SPI_DIV_CON_SHIFT = 0,
+ CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT,
+
+ /* CLKSEL_CON30 */
+ CLK_SDMMC_PLL_SEL_CPLL = 0,
+ CLK_SDMMC_PLL_SEL_GPLL,
+ CLK_SDMMC_PLL_SEL_24M,
+ CLK_SDMMC_PLL_SEL_USBPHY,
+ CLK_SDMMC_PLL_SHIFT = 8,
+ CLK_SDMMC_PLL_MASK = 0x3 << CLK_SDMMC_PLL_SHIFT,
+ CLK_SDMMC_DIV_CON_SHIFT = 0,
+ CLK_SDMMC_DIV_CON_MASK = 0xff << CLK_SDMMC_DIV_CON_SHIFT,
+
+ /* CLKSEL_CON32 */
+ CLK_EMMC_PLL_SEL_CPLL = 0,
+ CLK_EMMC_PLL_SEL_GPLL,
+ CLK_EMMC_PLL_SEL_24M,
+ CLK_EMMC_PLL_SEL_USBPHY,
+ CLK_EMMC_PLL_SHIFT = 8,
+ CLK_EMMC_PLL_MASK = 0x3 << CLK_EMMC_PLL_SHIFT,
+ CLK_EMMC_DIV_CON_SHIFT = 0,
+ CLK_EMMC_DIV_CON_MASK = 0xff << CLK_EMMC_DIV_CON_SHIFT,
+
+ /* CLKSEL_CON34 */
+ CLK_I2C_PLL_SEL_CPLL = 0,
+ CLK_I2C_PLL_SEL_GPLL,
+ CLK_I2C_DIV_CON_MASK = 0x7f,
+ CLK_I2C_PLL_SEL_MASK = 1,
+ CLK_I2C1_PLL_SEL_SHIFT = 15,
+ CLK_I2C1_DIV_CON_SHIFT = 8,
+ CLK_I2C0_PLL_SEL_SHIFT = 7,
+ CLK_I2C0_DIV_CON_SHIFT = 0,
+
+ /* CLKSEL_CON35 */
+ CLK_I2C3_PLL_SEL_SHIFT = 15,
+ CLK_I2C3_DIV_CON_SHIFT = 8,
+ CLK_I2C2_PLL_SEL_SHIFT = 7,
+ CLK_I2C2_DIV_CON_SHIFT = 0,
+};
+
+#define I2C_CLK_REG_MASK(bus) \
+ (CLK_I2C_DIV_CON_MASK << \
+ CLK_I2C ##bus## _DIV_CON_SHIFT | \
+ CLK_I2C_PLL_SEL_MASK << \
+ CLK_I2C ##bus## _PLL_SEL_SHIFT)
+
+#define I2C_CLK_REG_VALUE(bus, clk_div) \
+ ((clk_div - 1) << \
+ CLK_I2C ##bus## _DIV_CON_SHIFT | \
+ CLK_I2C_PLL_SEL_GPLL << \
+ CLK_I2C ##bus## _PLL_SEL_SHIFT)
+
+#define I2C_CLK_DIV_VALUE(con, bus) \
+ (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \
+ CLK_I2C_DIV_CON_MASK;
+
+#define VCO_MAX_KHZ (3200 * (MHz / KHz))
+#define VCO_MIN_KHZ (800 * (MHz / KHz))
+#define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
+#define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
+
+/*
+ * the div restructions of pll in integer mode, these are defined in
+ * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
+ */
+#define PLL_DIV_MIN 16
+#define PLL_DIV_MAX 3200
+
+/*
+ * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
+ * Formulas also embedded within the Fractional PLL Verilog model:
+ * If DSMPD = 1 (DSM is disabled, "integer mode")
+ * FOUTVCO = FREF / REFDIV * FBDIV
+ * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
+ * Where:
+ * FOUTVCO = Fractional PLL non-divided output frequency
+ * FOUTPOSTDIV = Fractional PLL divided output frequency
+ * (output of second post divider)
+ * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
+ * REFDIV = Fractional PLL input reference clock divider
+ * FBDIV = Integer value programmed into feedback divide
+ *
+ */
+static void rkclk_set_pll(struct rk3328_cru *cru, enum rk_clk_id clk_id,
+ const struct pll_div *div)
+{
+ u32 *pll_con;
+ u32 mode_shift, mode_mask;
+
+ pll_con = NULL;
+ mode_shift = 0;
+ switch (clk_id) {
+ case CLK_ARM:
+ pll_con = cru->apll_con;
+ mode_shift = APLL_MODE_SHIFT;
+ break;
+ case CLK_DDR:
+ pll_con = cru->dpll_con;
+ mode_shift = DPLL_MODE_SHIFT;
+ break;
+ case CLK_CODEC:
+ pll_con = cru->cpll_con;
+ mode_shift = CPLL_MODE_SHIFT;
+ break;
+ case CLK_GENERAL:
+ pll_con = cru->gpll_con;
+ mode_shift = GPLL_MODE_SHIFT;
+ break;
+ case CLK_NEW:
+ pll_con = cru->npll_con;
+ mode_shift = NPLL_MODE_SHIFT;
+ break;
+ default:
+ break;
+ }
+ mode_mask = 1 << mode_shift;
+
+ /* All 8 PLLs have same VCO and output frequency range restrictions. */
+ u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
+ u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
+
+ debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, \
+ postdiv2=%d, vco=%u khz, output=%u khz\n",
+ pll_con, div->fbdiv, div->refdiv, div->postdiv1,
+ div->postdiv2, vco_khz, output_khz);
+ assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
+ output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
+ div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
+
+ /*
+ * When power on or changing PLL setting,
+ * we must force PLL into slow mode to ensure output stable clock.
+ */
+ rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_SLOW << mode_shift);
+
+ /* use integer mode */
+ rk_clrsetreg(&pll_con[1], PLL_DSMPD_MASK,
+ PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
+
+ rk_clrsetreg(&pll_con[0],
+ PLL_FBDIV_MASK | PLL_POSTDIV1_MASK,
+ (div->fbdiv << PLL_FBDIV_SHIFT) |
+ (div->postdiv1 << PLL_POSTDIV1_SHIFT));
+ rk_clrsetreg(&pll_con[1],
+ PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
+ (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
+ (div->refdiv << PLL_REFDIV_SHIFT));
+
+ /* waiting for pll lock */
+ while (!(readl(&pll_con[1]) & (1 << PLL_LOCK_STATUS_SHIFT)))
+ udelay(1);
+
+ /* pll enter normal mode */
+ rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift);
+}
+
+static void rkclk_init(struct rk3328_cru *cru)
+{
+ u32 aclk_div;
+ u32 hclk_div;
+ u32 pclk_div;
+
+ /* configure gpll cpll */
+ rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
+ rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
+
+ /* configure perihp aclk, hclk, pclk */
+ aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
+ hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
+ pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
+
+ rk_clrsetreg(&cru->clksel_con[28],
+ ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
+ ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
+ aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
+ rk_clrsetreg(&cru->clksel_con[29],
+ PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK,
+ pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
+ hclk_div << HCLK_PERIHP_DIV_CON_SHIFT);
+}
+
+void rk3328_configure_cpu(struct rk3328_cru *cru,
+ enum apll_frequencies apll_freq)
+{
+ u32 clk_core_div;
+ u32 aclkm_div;
+ u32 pclk_dbg_div;
+
+ rkclk_set_pll(cru, CLK_ARM, apll_cfgs[apll_freq]);
+
+ clk_core_div = APLL_HZ / CLK_CORE_HZ - 1;
+ aclkm_div = APLL_HZ / ACLKM_CORE_HZ / (clk_core_div + 1) - 1;
+ pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ / (clk_core_div + 1) - 1;
+
+ rk_clrsetreg(&cru->clksel_con[0],
+ CLK_CORE_PLL_SEL_MASK | CLK_CORE_DIV_MASK,
+ CLK_CORE_PLL_SEL_APLL << CLK_CORE_PLL_SEL_SHIFT |
+ clk_core_div << CLK_CORE_DIV_SHIFT);
+
+ rk_clrsetreg(&cru->clksel_con[1],
+ PCLK_DBG_DIV_MASK | ACLKM_CORE_DIV_MASK,
+ pclk_dbg_div << PCLK_DBG_DIV_SHIFT |
+ aclkm_div << ACLKM_CORE_DIV_SHIFT);
+}
+
+
+static ulong rk3328_i2c_get_clk(struct rk3328_cru *cru, ulong clk_id)
+{
+ u32 div, con;
+
+ switch (clk_id) {
+ case SCLK_I2C0:
+ con = readl(&cru->clksel_con[34]);
+ div = I2C_CLK_DIV_VALUE(con, 0);
+ break;
+ case SCLK_I2C1:
+ con = readl(&cru->clksel_con[34]);
+ div = I2C_CLK_DIV_VALUE(con, 1);
+ break;
+ case SCLK_I2C2:
+ con = readl(&cru->clksel_con[35]);
+ div = I2C_CLK_DIV_VALUE(con, 2);
+ break;
+ case SCLK_I2C3:
+ con = readl(&cru->clksel_con[35]);
+ div = I2C_CLK_DIV_VALUE(con, 3);
+ break;
+ default:
+ printf("do not support this i2c bus\n");
+ return -EINVAL;
+ }
+
+ return DIV_TO_RATE(GPLL_HZ, div);
+}
+
+static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz)
+{
+ int src_clk_div;
+
+ src_clk_div = GPLL_HZ / hz;
+ assert(src_clk_div - 1 < 127);
+
+ switch (clk_id) {
+ case SCLK_I2C0:
+ rk_clrsetreg(&cru->clksel_con[34], I2C_CLK_REG_MASK(0),
+ I2C_CLK_REG_VALUE(0, src_clk_div));
+ break;
+ case SCLK_I2C1:
+ rk_clrsetreg(&cru->clksel_con[34], I2C_CLK_REG_MASK(1),
+ I2C_CLK_REG_VALUE(1, src_clk_div));
+ break;
+ case SCLK_I2C2:
+ rk_clrsetreg(&cru->clksel_con[35], I2C_CLK_REG_MASK(2),
+ I2C_CLK_REG_VALUE(2, src_clk_div));
+ break;
+ case SCLK_I2C3:
+ rk_clrsetreg(&cru->clksel_con[35], I2C_CLK_REG_MASK(3),
+ I2C_CLK_REG_VALUE(3, src_clk_div));
+ break;
+ default:
+ printf("do not support this i2c bus\n");
+ return -EINVAL;
+ }
+
+ return DIV_TO_RATE(GPLL_HZ, src_clk_div);
+}
+
+static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
+{
+ u32 div, con, con_id;
+
+ switch (clk_id) {
+ case HCLK_SDMMC:
+ con_id = 30;
+ break;
+ case HCLK_EMMC:
+ con_id = 32;
+ break;
+ default:
+ return -EINVAL;
+ }
+ con = readl(&cru->clksel_con[con_id]);
+ div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
+
+ if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
+ == CLK_EMMC_PLL_SEL_24M)
+ return DIV_TO_RATE(24*1024*1024, div);
+ else
+ return DIV_TO_RATE(GPLL_HZ, div);
+}
+
+static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
+ ulong clk_id, ulong set_rate)
+{
+ int src_clk_div;
+ u32 con_id;
+
+ switch (clk_id) {
+ case HCLK_SDMMC:
+ con_id = 30;
+ break;
+ case HCLK_EMMC:
+ con_id = 32;
+ break;
+ default:
+ return -EINVAL;
+ }
+ /* Select clk_sdmmc/emmc source from GPLL by default */
+ src_clk_div = GPLL_HZ / set_rate;
+
+ if (src_clk_div > 127) {
+ /* use 24MHz source for 400KHz clock */
+ src_clk_div = 24*1024*1024 / set_rate;
+ rk_clrsetreg(&cru->clksel_con[con_id],
+ CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
+ CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
+ (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
+ } else {
+ rk_clrsetreg(&cru->clksel_con[con_id],
+ CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
+ CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
+ (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
+ }
+
+ return rk3328_mmc_get_clk(cru, clk_id);
+}
+
+static ulong rk3328_pwm_get_clk(struct rk3328_cru *cru)
+{
+ u32 div, con;
+
+ con = readl(&cru->clksel_con[24]);
+ div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT;
+
+ return DIV_TO_RATE(GPLL_HZ, div);
+}
+
+static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz)
+{
+ u32 div = GPLL_HZ / hz;
+
+ rk_clrsetreg(&cru->clksel_con[24],
+ CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
+ CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
+ (div - 1) << CLK_PWM_DIV_CON_SHIFT);
+
+ return DIV_TO_RATE(GPLL_HZ, div);
+}
+
+static ulong rk3328_clk_get_rate(struct clk *clk)
+{
+ struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong rate = 0;
+
+ switch (clk->id) {
+ case 0 ... 29:
+ return 0;
+ case HCLK_SDMMC:
+ case HCLK_EMMC:
+ rate = rk3328_mmc_get_clk(priv->cru, clk->id);
+ break;
+ case SCLK_I2C0:
+ case SCLK_I2C1:
+ case SCLK_I2C2:
+ case SCLK_I2C3:
+ rate = rk3328_i2c_get_clk(priv->cru, clk->id);
+ break;
+ case SCLK_PWM:
+ rate = rk3328_pwm_get_clk(priv->cru);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+}
+
+static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong ret = 0;
+
+ switch (clk->id) {
+ case 0 ... 29:
+ return 0;
+ case HCLK_SDMMC:
+ case HCLK_EMMC:
+ ret = rk3328_mmc_set_clk(priv->cru, clk->id, rate);
+ break;
+ case SCLK_I2C0:
+ case SCLK_I2C1:
+ case SCLK_I2C2:
+ case SCLK_I2C3:
+ ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate);
+ break;
+ case SCLK_PWM:
+ ret = rk3328_pwm_set_clk(priv->cru, rate);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return ret;
+}
+
+static struct clk_ops rk3328_clk_ops = {
+ .get_rate = rk3328_clk_get_rate,
+ .set_rate = rk3328_clk_set_rate,
+};
+
+void *rockchip_get_cru(void)
+{
+ struct udevice *dev;
+ fdt_addr_t *addr;
+ int ret;
+
+ ret = uclass_get_device_by_name(UCLASS_CLK, "clk_rk3328", &dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ addr = dev_get_addr_ptr(dev);
+ if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
+ return ERR_PTR(-EINVAL);
+
+ return addr;
+}
+
+static int rk3328_clk_probe(struct udevice *dev)
+{
+ struct rk3328_clk_priv *priv = dev_get_priv(dev);
+
+ rkclk_init(priv->cru);
+
+ return 0;
+}
+
+static int rk3328_clk_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rk3328_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = (struct rk3328_cru *)dev_get_addr(dev);
+
+ return 0;
+}
+
+static int rk3328_clk_bind(struct udevice *dev)
+{
+ int ret;
+
+ /* The reset driver does not have a device node, so bind it here */
+ ret = device_bind_driver(gd->dm_root, "rk3328_sysreset", "reset", &dev);
+ if (ret)
+ printf("Warning: No RK3328 reset driver: ret=%d\n", ret);
+
+ return ret;
+}
+
+static const struct udevice_id rk3328_clk_ids[] = {
+ { .compatible = "rockchip,rk3328-cru" },
+ { }
+};
+
+U_BOOT_DRIVER(clk_rk3328) = {
+ .name = "clk_rk3328",
+ .id = UCLASS_CLK,
+ .of_match = rk3328_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct rk3328_clk_priv),
+ .ofdata_to_platdata = rk3328_clk_ofdata_to_platdata,
+ .ops = &rk3328_clk_ops,
+ .bind = rk3328_clk_bind,
+ .probe = rk3328_clk_probe,
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [U-Boot] [PATCH 3/7] clk: rockchip: add support for rk3328
2017-02-17 8:07 ` [U-Boot] [PATCH 3/7] clk: rockchip: add support for rk3328 Kever Yang
@ 2017-02-21 18:06 ` Simon Glass
2017-02-22 9:45 ` Kever Yang
0 siblings, 1 reply; 18+ messages in thread
From: Simon Glass @ 2017-02-21 18:06 UTC (permalink / raw)
To: u-boot
Hi Kever,
On 17 February 2017 at 01:07, Kever Yang <kever.yang@rock-chips.com> wrote:
> Add rk3328 clock driver and cru structure definition.
>
> Signed-off-by: William Zhang <william.zhang@rock-chips.com>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> arch/arm/include/asm/arch-rockchip/cru_rk3328.h | 65 +++
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk_rk3328.c | 607 ++++++++++++++++++++++++
> 3 files changed, 673 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3328.h
> create mode 100644 drivers/clk/rockchip/clk_rk3328.c
>
> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
> new file mode 100644
> index 0000000..089c4ca
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
> @@ -0,0 +1,65 @@
> +/*
> + * (C) Copyright 2016 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __ASM_ARCH_CRU_RK3328_H_
> +#define __ASM_ARCH_CRU_RK3328_H_
> +
> +#include <common.h>
> +
> +struct rk3328_cru {
> + u32 apll_con[5];
> + u32 reserved1[3];
> + u32 dpll_con[5];
> + u32 reserved2[3];
> + u32 cpll_con[5];
> + u32 reserved3[3];
> + u32 gpll_con[5];
> + u32 reserved4[3];
> + u32 mode_con;
> + u32 misc;
> + u32 reserved5[2];
> + u32 glb_cnt_th;
> + u32 glb_rst_st;
> + u32 glb_srst_snd_value;
> + u32 glb_srst_fst_value;
> + u32 npll_con[5];
> + u32 reserved6[(0x100-0xb4)/4];
> + u32 clksel_con[53];
> + u32 reserved7[(0x200-0x1d4)/4];
> + u32 clkgate_con[29];
> + u32 reserved8[3];
> + u32 ssgtbl[32];
> + u32 softrst_con[12];
> + u32 reserved9[(0x380-0x330)/4];
> + u32 sdmmc_con[2];
> + u32 sdio_con[2];
> + u32 emmc_con[2];
> + u32 sdmmc_ext_con[2];
> +};
> +check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c);
> +#define MHz 1000000
> +#define KHz 1000
> +#define OSC_HZ (24 * MHz)
> +#define APLL_HZ (600 * MHz)
> +#define GPLL_HZ (576 * MHz)
> +#define CPLL_HZ (594 * MHz)
> +
> +#define CLK_CORE_HZ (600 * MHz)
> +#define ACLKM_CORE_HZ (300 * MHz)
> +#define PCLK_DBG_HZ (300 * MHz)
> +
> +#define PERIHP_ACLK_HZ (144000 * KHz)
> +#define PERIHP_HCLK_HZ (72000 * KHz)
> +#define PERIHP_PCLK_HZ (72000 * KHz)
> +
> +#define PWM_CLOCK_HZ (74 * MHz)
> +
> +enum apll_frequencies {
> + APLL_816_MHZ,
> + APLL_600_MHZ,
> +};
> +
> +#endif /* __ASM_ARCH_CRU_RK3328_H_ */
> diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
> index 1f8e417..c4e81e9 100644
> --- a/drivers/clk/rockchip/Makefile
> +++ b/drivers/clk/rockchip/Makefile
> @@ -6,4 +6,5 @@
>
> obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
> obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
> +obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
> diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
> new file mode 100644
> index 0000000..e075414
> --- /dev/null
> +++ b/drivers/clk/rockchip/clk_rk3328.c
> @@ -0,0 +1,607 @@
> +/*
> + * (C) Copyright 2016 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk3328.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/io.h>
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <dm/lists.h>
> +#include <dt-bindings/clock/rk3328-cru.h>
> +#include <errno.h>
> +#include <syscon.h>
Can you please tidy up the order here? asm/ should go after the normal
headers, and dm/lists and dt-bindings/ afer that
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct rk3328_clk_priv {
> + struct rk3328_cru *cru;
> + ulong rate;
> +};
> +
[..]
> +
> +#define I2C_CLK_REG_MASK(bus) \
> + (CLK_I2C_DIV_CON_MASK << \
> + CLK_I2C ##bus## _DIV_CON_SHIFT | \
> + CLK_I2C_PLL_SEL_MASK << \
> + CLK_I2C ##bus## _PLL_SEL_SHIFT)
> +
> +#define (bus, clk_div) \
> + ((clk_div - 1) << \
> + CLK_I2C ##bus## _DIV_CON_SHIFT | \
> + CLK_I2C_PLL_SEL_GPLL << \
> + CLK_I2C ##bus## _PLL_SEL_SHIFT)
> +
> +#define I2C_CLK_DIV_VALUE(con, bus) \
> + (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \
> + CLK_I2C_DIV_CON_MASK;
Can we drop these three and instead write them out below?
> +
> +#define VCO_MAX_KHZ (3200 * (MHz / KHz))
> +#define VCO_MIN_KHZ (800 * (MHz / KHz))
> +#define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
> +#define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
> +
> +/*
> + * the div restructions of pll in integer mode, these are defined in
> + * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
> + */
> +#define PLL_DIV_MIN 16
> +#define PLL_DIV_MAX 3200
> +
[...]
> +static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
> +{
> + u32 div, con, con_id;
> +
> + switch (clk_id) {
> + case HCLK_SDMMC:
> + con_id = 30;
> + break;
> + case HCLK_EMMC:
> + con_id = 32;
> + break;
> + default:
> + return -EINVAL;
> + }
> + con = readl(&cru->clksel_con[con_id]);
> + div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
> +
> + if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
> + == CLK_EMMC_PLL_SEL_24M)
> + return DIV_TO_RATE(24*1024*1024, div);
Perhaps should have a #define for the 24MHz oscillator?
> + else
> + return DIV_TO_RATE(GPLL_HZ, div);
> +}
> +
> +static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
> + ulong clk_id, ulong set_rate)
> +{
> + int src_clk_div;
> + u32 con_id;
> +
> + switch (clk_id) {
> + case HCLK_SDMMC:
> + con_id = 30;
> + break;
> + case HCLK_EMMC:
> + con_id = 32;
> + break;
> + default:
> + return -EINVAL;
> + }
> + /* Select clk_sdmmc/emmc source from GPLL by default */
> + src_clk_div = GPLL_HZ / set_rate;
> +
> + if (src_clk_div > 127) {
> + /* use 24MHz source for 400KHz clock */
> + src_clk_div = 24*1024*1024 / set_rate;
> + rk_clrsetreg(&cru->clksel_con[con_id],
> + CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
> + CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
> + (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
> + } else {
> + rk_clrsetreg(&cru->clksel_con[con_id],
> + CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
> + CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
> + (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
> + }
> +
> + return rk3328_mmc_get_clk(cru, clk_id);
> +}
> +
> +static ulong rk3328_pwm_get_clk(struct rk3328_cru *cru)
> +{
> + u32 div, con;
> +
> + con = readl(&cru->clksel_con[24]);
> + div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT;
> +
> + return DIV_TO_RATE(GPLL_HZ, div);
> +}
> +
> +static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz)
> +{
> + u32 div = GPLL_HZ / hz;
> +
> + rk_clrsetreg(&cru->clksel_con[24],
> + CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
> + CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
> + (div - 1) << CLK_PWM_DIV_CON_SHIFT);
> +
> + return DIV_TO_RATE(GPLL_HZ, div);
> +}
> +
> +static ulong rk3328_clk_get_rate(struct clk *clk)
> +{
> + struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
> + ulong rate = 0;
> +
> + switch (clk->id) {
> + case 0 ... 29:
> + return 0;
> + case HCLK_SDMMC:
> + case HCLK_EMMC:
> + rate = rk3328_mmc_get_clk(priv->cru, clk->id);
> + break;
> + case SCLK_I2C0:
> + case SCLK_I2C1:
> + case SCLK_I2C2:
> + case SCLK_I2C3:
> + rate = rk3328_i2c_get_clk(priv->cru, clk->id);
> + break;
> + case SCLK_PWM:
> + rate = rk3328_pwm_get_clk(priv->cru);
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return rate;
> +}
> +
> +static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
> +{
> + struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
> + ulong ret = 0;
> +
> + switch (clk->id) {
> + case 0 ... 29:
> + return 0;
> + case HCLK_SDMMC:
> + case HCLK_EMMC:
> + ret = rk3328_mmc_set_clk(priv->cru, clk->id, rate);
> + break;
> + case SCLK_I2C0:
> + case SCLK_I2C1:
> + case SCLK_I2C2:
> + case SCLK_I2C3:
> + ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate);
> + break;
> + case SCLK_PWM:
> + ret = rk3328_pwm_set_clk(priv->cru, rate);
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return ret;
> +}
> +
> +static struct clk_ops rk3328_clk_ops = {
> + .get_rate = rk3328_clk_get_rate,
> + .set_rate = rk3328_clk_set_rate,
> +};
> +
> +void *rockchip_get_cru(void)
> +{
> + struct udevice *dev;
> + fdt_addr_t *addr;
> + int ret;
> +
> + ret = uclass_get_device_by_name(UCLASS_CLK, "clk_rk3328", &dev);
Would it be possible to use uclass_get_device_by_driver()? Also, if
this function is to be exported, it really should be in
arch/arm/mach-rockchip somewhere.
> + if (ret)
> + return ERR_PTR(ret);
> +
> + addr = dev_get_addr_ptr(dev);
> + if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
> + return ERR_PTR(-EINVAL);
> +
> + return addr;
> +}
> +
> +static int rk3328_clk_probe(struct udevice *dev)
> +{
> + struct rk3328_clk_priv *priv = dev_get_priv(dev);
> +
> + rkclk_init(priv->cru);
> +
> + return 0;
> +}
> +
> +static int rk3328_clk_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct rk3328_clk_priv *priv = dev_get_priv(dev);
> +
> + priv->cru = (struct rk3328_cru *)dev_get_addr(dev);
> +
> + return 0;
> +}
> +
> +static int rk3328_clk_bind(struct udevice *dev)
> +{
> + int ret;
> +
> + /* The reset driver does not have a device node, so bind it here */
> + ret = device_bind_driver(gd->dm_root, "rk3328_sysreset", "reset", &dev);
> + if (ret)
> + printf("Warning: No RK3328 reset driver: ret=%d\n", ret);
> +
> + return ret;
> +}
> +
> +static const struct udevice_id rk3328_clk_ids[] = {
> + { .compatible = "rockchip,rk3328-cru" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(clk_rk3328) = {
> + .name = "clk_rk3328",
> + .id = UCLASS_CLK,
> + .of_match = rk3328_clk_ids,
> + .priv_auto_alloc_size = sizeof(struct rk3328_clk_priv),
> + .ofdata_to_platdata = rk3328_clk_ofdata_to_platdata,
> + .ops = &rk3328_clk_ops,
> + .bind = rk3328_clk_bind,
> + .probe = rk3328_clk_probe,
> +};
> --
> 1.9.1
>
Regards,
Simon
^ permalink raw reply [flat|nested] 18+ messages in thread* [U-Boot] [PATCH 3/7] clk: rockchip: add support for rk3328
2017-02-21 18:06 ` Simon Glass
@ 2017-02-22 9:45 ` Kever Yang
2017-02-23 2:23 ` Simon Glass
0 siblings, 1 reply; 18+ messages in thread
From: Kever Yang @ 2017-02-22 9:45 UTC (permalink / raw)
To: u-boot
Hi Simon,
On 02/22/2017 02:06 AM, Simon Glass wrote:
> Hi Kever,
>
> On 17 February 2017 at 01:07, Kever Yang <kever.yang@rock-chips.com> wrote:
>> Add rk3328 clock driver and cru structure definition.
>>
>> Signed-off-by: William Zhang <william.zhang@rock-chips.com>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>> arch/arm/include/asm/arch-rockchip/cru_rk3328.h | 65 +++
>> drivers/clk/rockchip/Makefile | 1 +
>> drivers/clk/rockchip/clk_rk3328.c | 607 ++++++++++++++++++++++++
>> 3 files changed, 673 insertions(+)
>> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3328.h
>> create mode 100644 drivers/clk/rockchip/clk_rk3328.c
>>
>> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
>> new file mode 100644
>> index 0000000..089c4ca
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
>> @@ -0,0 +1,65 @@
>> +/*
>> + * (C) Copyright 2016 Rockchip Electronics Co., Ltd
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#ifndef __ASM_ARCH_CRU_RK3328_H_
>> +#define __ASM_ARCH_CRU_RK3328_H_
>> +
>> +#include <common.h>
>> +
>> +struct rk3328_cru {
>> + u32 apll_con[5];
>> + u32 reserved1[3];
>> + u32 dpll_con[5];
>> + u32 reserved2[3];
>> + u32 cpll_con[5];
>> + u32 reserved3[3];
>> + u32 gpll_con[5];
>> + u32 reserved4[3];
>> + u32 mode_con;
>> + u32 misc;
>> + u32 reserved5[2];
>> + u32 glb_cnt_th;
>> + u32 glb_rst_st;
>> + u32 glb_srst_snd_value;
>> + u32 glb_srst_fst_value;
>> + u32 npll_con[5];
>> + u32 reserved6[(0x100-0xb4)/4];
>> + u32 clksel_con[53];
>> + u32 reserved7[(0x200-0x1d4)/4];
>> + u32 clkgate_con[29];
>> + u32 reserved8[3];
>> + u32 ssgtbl[32];
>> + u32 softrst_con[12];
>> + u32 reserved9[(0x380-0x330)/4];
>> + u32 sdmmc_con[2];
>> + u32 sdio_con[2];
>> + u32 emmc_con[2];
>> + u32 sdmmc_ext_con[2];
>> +};
>> +check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c);
>> +#define MHz 1000000
>> +#define KHz 1000
>> +#define OSC_HZ (24 * MHz)
>> +#define APLL_HZ (600 * MHz)
>> +#define GPLL_HZ (576 * MHz)
>> +#define CPLL_HZ (594 * MHz)
>> +
>> +#define CLK_CORE_HZ (600 * MHz)
>> +#define ACLKM_CORE_HZ (300 * MHz)
>> +#define PCLK_DBG_HZ (300 * MHz)
>> +
>> +#define PERIHP_ACLK_HZ (144000 * KHz)
>> +#define PERIHP_HCLK_HZ (72000 * KHz)
>> +#define PERIHP_PCLK_HZ (72000 * KHz)
>> +
>> +#define PWM_CLOCK_HZ (74 * MHz)
>> +
>> +enum apll_frequencies {
>> + APLL_816_MHZ,
>> + APLL_600_MHZ,
>> +};
>> +
>> +#endif /* __ASM_ARCH_CRU_RK3328_H_ */
>> diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
>> index 1f8e417..c4e81e9 100644
>> --- a/drivers/clk/rockchip/Makefile
>> +++ b/drivers/clk/rockchip/Makefile
>> @@ -6,4 +6,5 @@
>>
>> obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
>> obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
>> +obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
>> obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
>> diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
>> new file mode 100644
>> index 0000000..e075414
>> --- /dev/null
>> +++ b/drivers/clk/rockchip/clk_rk3328.c
>> @@ -0,0 +1,607 @@
>> +/*
>> + * (C) Copyright 2016 Rockchip Electronics Co., Ltd
>> + *
>> + * SPDX-License-Identifier: GPL-2.0
>> + */
>> +
>> +#include <common.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/cru_rk3328.h>
>> +#include <asm/arch/hardware.h>
>> +#include <asm/io.h>
>> +#include <clk-uclass.h>
>> +#include <dm.h>
>> +#include <dm/lists.h>
>> +#include <dt-bindings/clock/rk3328-cru.h>
>> +#include <errno.h>
>> +#include <syscon.h>
> Can you please tidy up the order here? asm/ should go after the normal
> headers, and dm/lists and dt-bindings/ afer that
OK, will fix.
>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +struct rk3328_clk_priv {
>> + struct rk3328_cru *cru;
>> + ulong rate;
>> +};
>> +
> [..]
>
>> +
>> +#define I2C_CLK_REG_MASK(bus) \
>> + (CLK_I2C_DIV_CON_MASK << \
>> + CLK_I2C ##bus## _DIV_CON_SHIFT | \
>> + CLK_I2C_PLL_SEL_MASK << \
>> + CLK_I2C ##bus## _PLL_SEL_SHIFT)
>> +
>> +#define (bus, clk_div) \
>> + ((clk_div - 1) << \
>> + CLK_I2C ##bus## _DIV_CON_SHIFT | \
>> + CLK_I2C_PLL_SEL_GPLL << \
>> + CLK_I2C ##bus## _PLL_SEL_SHIFT)
>> +
>> +#define I2C_CLK_DIV_VALUE(con, bus) \
>> + (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \
>> + CLK_I2C_DIV_CON_MASK;
> Can we drop these three and instead write them out below?
I don't know why you don't like this kind of MACRO, like the size_mb in
sdram driver,
we though this help people understand the C source and make the C source
cold looks much clean,
in some platform, maintainer may ask for this when there are multi
controller and can reuse
the same MACRO.
Anyway, I will make this fallback to normal shift/mask style in next
version.
>
>> +
>> +#define VCO_MAX_KHZ (3200 * (MHz / KHz))
>> +#define VCO_MIN_KHZ (800 * (MHz / KHz))
>> +#define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
>> +#define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
>> +
>> +/*
>> + * the div restructions of pll in integer mode, these are defined in
>> + * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
>> + */
>> +#define PLL_DIV_MIN 16
>> +#define PLL_DIV_MAX 3200
>> +
> [...]
>
>> +static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
>> +{
>> + u32 div, con, con_id;
>> +
>> + switch (clk_id) {
>> + case HCLK_SDMMC:
>> + con_id = 30;
>> + break;
>> + case HCLK_EMMC:
>> + con_id = 32;
>> + break;
>> + default:
>> + return -EINVAL;
>> + }
>> + con = readl(&cru->clksel_con[con_id]);
>> + div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
>> +
>> + if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
>> + == CLK_EMMC_PLL_SEL_24M)
>> + return DIV_TO_RATE(24*1024*1024, div);
> Perhaps should have a #define for the 24MHz oscillator?
Already have one, will fix.
>
>> + else
>> + return DIV_TO_RATE(GPLL_HZ, div);
>> +}
>> +
>> +static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
>> + ulong clk_id, ulong set_rate)
>> +{
>> + int src_clk_div;
>> + u32 con_id;
>> +
>> + switch (clk_id) {
>> + case HCLK_SDMMC:
>> + con_id = 30;
>> + break;
>> + case HCLK_EMMC:
>> + con_id = 32;
>> + break;
>> + default:
>> + return -EINVAL;
>> + }
>> + /* Select clk_sdmmc/emmc source from GPLL by default */
>> + src_clk_div = GPLL_HZ / set_rate;
>> +
>> + if (src_clk_div > 127) {
>> + /* use 24MHz source for 400KHz clock */
>> + src_clk_div = 24*1024*1024 / set_rate;
>> + rk_clrsetreg(&cru->clksel_con[con_id],
>> + CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
>> + CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
>> + (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
>> + } else {
>> + rk_clrsetreg(&cru->clksel_con[con_id],
>> + CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
>> + CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
>> + (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
>> + }
>> +
>> + return rk3328_mmc_get_clk(cru, clk_id);
>> +}
>> +
>> +static ulong rk3328_pwm_get_clk(struct rk3328_cru *cru)
>> +{
>> + u32 div, con;
>> +
>> + con = readl(&cru->clksel_con[24]);
>> + div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT;
>> +
>> + return DIV_TO_RATE(GPLL_HZ, div);
>> +}
>> +
>> +static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz)
>> +{
>> + u32 div = GPLL_HZ / hz;
>> +
>> + rk_clrsetreg(&cru->clksel_con[24],
>> + CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
>> + CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
>> + (div - 1) << CLK_PWM_DIV_CON_SHIFT);
>> +
>> + return DIV_TO_RATE(GPLL_HZ, div);
>> +}
>> +
>> +static ulong rk3328_clk_get_rate(struct clk *clk)
>> +{
>> + struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
>> + ulong rate = 0;
>> +
>> + switch (clk->id) {
>> + case 0 ... 29:
>> + return 0;
>> + case HCLK_SDMMC:
>> + case HCLK_EMMC:
>> + rate = rk3328_mmc_get_clk(priv->cru, clk->id);
>> + break;
>> + case SCLK_I2C0:
>> + case SCLK_I2C1:
>> + case SCLK_I2C2:
>> + case SCLK_I2C3:
>> + rate = rk3328_i2c_get_clk(priv->cru, clk->id);
>> + break;
>> + case SCLK_PWM:
>> + rate = rk3328_pwm_get_clk(priv->cru);
>> + break;
>> + default:
>> + return -ENOENT;
>> + }
>> +
>> + return rate;
>> +}
>> +
>> +static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
>> +{
>> + struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
>> + ulong ret = 0;
>> +
>> + switch (clk->id) {
>> + case 0 ... 29:
>> + return 0;
>> + case HCLK_SDMMC:
>> + case HCLK_EMMC:
>> + ret = rk3328_mmc_set_clk(priv->cru, clk->id, rate);
>> + break;
>> + case SCLK_I2C0:
>> + case SCLK_I2C1:
>> + case SCLK_I2C2:
>> + case SCLK_I2C3:
>> + ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate);
>> + break;
>> + case SCLK_PWM:
>> + ret = rk3328_pwm_set_clk(priv->cru, rate);
>> + break;
>> + default:
>> + return -ENOENT;
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static struct clk_ops rk3328_clk_ops = {
>> + .get_rate = rk3328_clk_get_rate,
>> + .set_rate = rk3328_clk_set_rate,
>> +};
>> +
>> +void *rockchip_get_cru(void)
>> +{
>> + struct udevice *dev;
>> + fdt_addr_t *addr;
>> + int ret;
>> +
>> + ret = uclass_get_device_by_name(UCLASS_CLK, "clk_rk3328", &dev);
> Would it be possible to use uclass_get_device_by_driver()? Also, if
> this function is to be exported, it really should be in
> arch/arm/mach-rockchip somewhere.
Will move to arch/arm/mach-rockchip.
Thanks,
- Kever
>
>> + if (ret)
>> + return ERR_PTR(ret);
>> +
>> + addr = dev_get_addr_ptr(dev);
>> + if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
>> + return ERR_PTR(-EINVAL);
>> +
>> + return addr;
>> +}
>> +
>> +static int rk3328_clk_probe(struct udevice *dev)
>> +{
>> + struct rk3328_clk_priv *priv = dev_get_priv(dev);
>> +
>> + rkclk_init(priv->cru);
>> +
>> + return 0;
>> +}
>> +
>> +static int rk3328_clk_ofdata_to_platdata(struct udevice *dev)
>> +{
>> + struct rk3328_clk_priv *priv = dev_get_priv(dev);
>> +
>> + priv->cru = (struct rk3328_cru *)dev_get_addr(dev);
>> +
>> + return 0;
>> +}
>> +
>> +static int rk3328_clk_bind(struct udevice *dev)
>> +{
>> + int ret;
>> +
>> + /* The reset driver does not have a device node, so bind it here */
>> + ret = device_bind_driver(gd->dm_root, "rk3328_sysreset", "reset", &dev);
>> + if (ret)
>> + printf("Warning: No RK3328 reset driver: ret=%d\n", ret);
>> +
>> + return ret;
>> +}
>> +
>> +static const struct udevice_id rk3328_clk_ids[] = {
>> + { .compatible = "rockchip,rk3328-cru" },
>> + { }
>> +};
>> +
>> +U_BOOT_DRIVER(clk_rk3328) = {
>> + .name = "clk_rk3328",
>> + .id = UCLASS_CLK,
>> + .of_match = rk3328_clk_ids,
>> + .priv_auto_alloc_size = sizeof(struct rk3328_clk_priv),
>> + .ofdata_to_platdata = rk3328_clk_ofdata_to_platdata,
>> + .ops = &rk3328_clk_ops,
>> + .bind = rk3328_clk_bind,
>> + .probe = rk3328_clk_probe,
>> +};
>> --
>> 1.9.1
>>
> Regards,
> Simon
>
>
>
^ permalink raw reply [flat|nested] 18+ messages in thread* [U-Boot] [PATCH 3/7] clk: rockchip: add support for rk3328
2017-02-22 9:45 ` Kever Yang
@ 2017-02-23 2:23 ` Simon Glass
0 siblings, 0 replies; 18+ messages in thread
From: Simon Glass @ 2017-02-23 2:23 UTC (permalink / raw)
To: u-boot
+Tom
Hi Kever,
On 22 February 2017 at 02:45, Kever Yang <kever.yang@rock-chips.com> wrote:
>
> Hi Simon,
>
>
> On 02/22/2017 02:06 AM, Simon Glass wrote:
>>
>> Hi Kever,
>>
>> On 17 February 2017 at 01:07, Kever Yang <kever.yang@rock-chips.com> wrote:
>>>
>>> Add rk3328 clock driver and cru structure definition.
>>>
>>> Signed-off-by: William Zhang <william.zhang@rock-chips.com>
>>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>>> ---
>>>
>>> arch/arm/include/asm/arch-rockchip/cru_rk3328.h | 65 +++
>>> drivers/clk/rockchip/Makefile | 1 +
>>> drivers/clk/rockchip/clk_rk3328.c | 607 ++++++++++++++++++++++++
>>> 3 files changed, 673 insertions(+)
>>> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3328.h
>>> create mode 100644 drivers/clk/rockchip/clk_rk3328.c
>>>
>> [..]
>>
>>> +
>>> +#define I2C_CLK_REG_MASK(bus) \
>>> + (CLK_I2C_DIV_CON_MASK << \
>>> + CLK_I2C ##bus## _DIV_CON_SHIFT | \
>>> + CLK_I2C_PLL_SEL_MASK << \
>>> + CLK_I2C ##bus## _PLL_SEL_SHIFT)
>>> +
>>> +#define (bus, clk_div) \
>>> + ((clk_div - 1) << \
>>> + CLK_I2C ##bus## _DIV_CON_SHIFT | \
>>> + CLK_I2C_PLL_SEL_GPLL << \
>>> + CLK_I2C ##bus## _PLL_SEL_SHIFT)
>>> +
>>> +#define I2C_CLK_DIV_VALUE(con, bus) \
>>> + (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \
>>> + CLK_I2C_DIV_CON_MASK;
>>
>> Can we drop these three and instead write them out below?
>
>
> I don't know why you don't like this kind of MACRO, like the size_mb in sdram driver,
> we though this help people understand the C source and make the C source cold looks much clean,
> in some platform, maintainer may ask for this when there are multi controller and can reuse
> the same MACRO.
> Anyway, I will make this fallback to normal shift/mask style in next version.
>
Let me try to explain this.
In this code macros are created by pasting symbols together which
means (for example) that it is not possible to find the definition of
CLK_I2C 0_DIV_CON_SHIFT by searching the code. This can be very
confusing for people trying to figure out what is going on. It is bad
enough in a single file but gets worse when things migrate to header
files.
If you want to have a macro here, how about
#define CLK_I2C DIV_CON_SHIFT(bus)
instead? This can return the appropriate shift for the bus. The
'I2C_CLK_DIV_VALUE' macro is only used in rk3328_i2c_get_clk() and
ends up creating repetitive code (all the macro logic happens in each
case of the switch() , which the compiler hopefully can optimize, but
who knows? In any case conceptually I do not think it simplifies the
code. You end up unpicking the macros and printing out intermediate
values, etc. I have definitely done my share of that.
The rule of using shifts and masks in the code rather than hiding them
originally came from Wolfgang and I have got used to it. One thing I
have noticed is that with macros you can build up a tree of
interdependent macros such that it is very hard to figure out what is
actually going on, e.g. if you are looking for a bug. I am aware that
the code style in coreboot and UEFI are different, although I am not
an expert in either.
Does that make sense?
Regards,
Simon
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 4/7] pinctrl: rockchip: add support for rk3328
2017-02-17 8:07 [U-Boot] [PATCH 0/7] add support for rk3328 SoC Kever Yang
` (2 preceding siblings ...)
2017-02-17 8:07 ` [U-Boot] [PATCH 3/7] clk: rockchip: add support for rk3328 Kever Yang
@ 2017-02-17 8:07 ` Kever Yang
2017-02-21 18:06 ` Simon Glass
2017-02-17 8:07 ` [U-Boot] [PATCH 5/7] sysreset: add support for rockchip rk3328 soc Kever Yang
` (3 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Kever Yang @ 2017-02-17 8:07 UTC (permalink / raw)
To: u-boot
Add rk3328 pinctrl driver and grf/iomux structure definition.
Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 134 ++++++++
drivers/pinctrl/Kconfig | 9 +
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl_rk3328.c | 418 ++++++++++++++++++++++++
include/dt-bindings/pinctrl/rockchip.h | 2 +
5 files changed, 564 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3328.h
create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3328.c
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
new file mode 100644
index 0000000..4a3eda8
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3328_GRF_H__
+#define __SOC_ROCKCHIP_RK3328_GRF_H__
+
+struct rk3328_grf_regs {
+ u32 gpio0a_iomux;
+ u32 gpio0b_iomux;
+ u32 gpio0c_iomux;
+ u32 gpio0d_iomux;
+ u32 gpio1a_iomux;
+ u32 gpio1b_iomux;
+ u32 gpio1c_iomux;
+ u32 gpio1d_iomux;
+ u32 gpio2a_iomux;
+ u32 gpio2bl_iomux;
+ u32 gpio2bh_iomux;
+ u32 gpio2cl_iomux;
+ u32 gpio2ch_iomux;
+ u32 gpio2d_iomux;
+ u32 gpio3al_iomux;
+ u32 gpio3ah_iomux;
+ u32 gpio3bl_iomux;
+ u32 gpio3bh_iomux;
+ u32 gpio3c_iomux;
+ u32 gpio3d_iomux;
+ u32 com_iomux;
+ u32 reserved1[(0x100-0x54)/4];
+
+ u32 gpio0a_p;
+ u32 gpio0b_p;
+ u32 gpio0c_p;
+ u32 gpio0d_p;
+ u32 gpio1a_p;
+ u32 gpio1b_p;
+ u32 gpio1c_p;
+ u32 gpio1d_p;
+ u32 gpio2a_p;
+ u32 gpio2b_p;
+ u32 gpio2c_p;
+ u32 gpio2d_p;
+ u32 gpio3a_p;
+ u32 gpio3b_p;
+ u32 gpio3c_p;
+ u32 gpio3d_p;
+ u32 reserved2[(0x200-0x140)/4];
+ u32 gpio0a_e;
+ u32 gpio0b_e;
+ u32 gpio0c_e;
+ u32 gpio0d_e;
+ u32 gpio1a_e;
+ u32 gpio1b_e;
+ u32 gpio1c_e;
+ u32 gpio1d_e;
+ u32 gpio2a_e;
+ u32 gpio2b_e;
+ u32 gpio2c_e;
+ u32 gpio2d_e;
+ u32 gpio3a_e;
+ u32 gpio3b_e;
+ u32 gpio3c_e;
+ u32 gpio3d_e;
+ u32 reserved3[(0x300-0x240)/4];
+ u32 gpio0l_sr;
+ u32 gpio0h_sr;
+ u32 gpio1l_sr;
+ u32 gpio1h_sr;
+ u32 gpio2l_sr;
+ u32 gpio2h_sr;
+ u32 gpio3l_sr;
+ u32 gpio3h_sr;
+ u32 reserved4[(0x380-0x320)/4];
+ u32 gpio0l_smt;
+ u32 gpio0h_smt;
+ u32 gpio1l_smt;
+ u32 gpio1h_smt;
+ u32 gpio2l_smt;
+ u32 gpio2h_smt;
+ u32 gpio3l_smt;
+ u32 gpio3h_smt;
+ u32 reserved5[(0x400-0x3a0)/4];
+ u32 soc_con[11];
+ u32 reserved6[(0x480-0x42c)/4];
+ u32 soc_status[5];
+ u32 reserved7[(0x4c0-0x494)/4];
+ u32 otg3_con[2];
+ u32 reserved8[(0x500-0x4c8)/4];
+ u32 cpu_con[2];
+ u32 reserved9[(0x520-0x508)/4];
+ u32 cpu_status[2];
+ u32 reserved10[(0x5c8-0x528)/4];
+ u32 os_reg[8];
+ u32 reserved11[(0x680-0x5e8)/4];
+ u32 sig_detect_con;
+ u32 reserved12[3];
+ u32 sig_detect_status;
+ u32 reserved13[3];
+ u32 sig_detect_status_clr;
+ u32 reserved14[3];
+
+ u32 sdmmc_det_counter;
+ u32 reserved15[(0x700-0x6b4)/4];
+ u32 host0_con[3];
+ u32 reserved16[(0x880-0x70c)/4];
+ u32 otg_con0;
+ u32 reserved17[3];
+ u32 host0_status;
+ u32 reserved18[(0x900-0x894)/4];
+ u32 mac_con[3];
+ u32 reserved19[(0xb00-0x90c)/4];
+ u32 macphy_con[4];
+ u32 macphy_status;
+};
+check_member(rk3328_grf_regs, macphy_status, 0xb10);
+
+struct rk3328_sgrf_regs {
+ u32 soc_con[6];
+ u32 reserved0[(0x100-0x18)/4];
+ u32 dmac_con[6];
+ u32 reserved1[(0x180-0x118)/4];
+ u32 fast_boot_addr;
+ u32 reserved2[(0x200-0x184)/4];
+ u32 chip_fuse_con;
+ u32 reserved3[(0x280-0x204)/4];
+ u32 hdcp_key_reg[8];
+ u32 hdcp_key_access_mask;
+};
+check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0);
+
+#endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index efcb4c0..16e2a17 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -148,6 +148,15 @@ config PINCTRL_AT91PIO4
This option is to enable the AT91 pinctrl driver for AT91 PIO4
controller which is available on SAMA5D2 SoC.
+config ROCKCHIP_RK3328_PINCTRL
+ bool "Rockchip pin control driver"
+ depends on DM
+ help
+ Support pin multiplexing control on Rockchip rk3328 SoCs. The driver
+ is controlled by a device tree node which contains both the GPIO
+ definitions and pin control functions for each available multiplex
+ function.
+
config ROCKCHIP_RK3399_PINCTRL
bool "Rockchip pin control driver"
depends on DM
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index 805c833..6bf770b 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -7,4 +7,5 @@
obj-$(CONFIG_ROCKCHIP_RK3036_PINCTRL) += pinctrl_rk3036.o
obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3328_PINCTRL) += pinctrl_rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3399_PINCTRL) += pinctrl_rk3399.o
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
new file mode 100644
index 0000000..3fa334f
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
@@ -0,0 +1,418 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3328.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <errno.h>
+#include <syscon.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rk3328_pinctrl_priv {
+ struct rk3328_grf_regs *grf;
+};
+
+enum {
+ /* GRF_GPIO0A_IOMUX */
+ GRF_GPIO0A5_SEL_SHIFT = 10,
+ GRF_GPIO0A5_SEL_MASK = 3 << GRF_GPIO0A5_SEL_SHIFT,
+ GRF_I2C3_SCL = 2,
+
+ GRF_GPIO0A6_SEL_SHIFT = 12,
+ GRF_GPIO0A6_SEL_MASK = 3 << GRF_GPIO0A6_SEL_SHIFT,
+ GRF_I2C3_SDA = 2,
+
+ GRF_GPIO0A7_SEL_SHIFT = 14,
+ GRF_GPIO0A7_SEL_MASK = 3 << GRF_GPIO0A7_SEL_SHIFT,
+ GRF_EMMC_DATA0 = 2,
+
+ /* GRF_GPIO1A_IOMUX */
+ GRF_GPIO1A0_SEL_SHIFT = 0,
+ GRF_GPIO1A0_SEL_MASK = 0x3fff << GRF_GPIO1A0_SEL_SHIFT,
+ GRF_CARD_DATA_CLK_CMD_DETN = 0x1555,
+
+ /* GRF_GPIO2A_IOMUX */
+ GRF_GPIO2A0_SEL_SHIFT = 0,
+ GRF_GPIO2A0_SEL_MASK = 3 << GRF_GPIO2A0_SEL_SHIFT,
+ GRF_UART2_TX_M1 = 1,
+
+ GRF_GPIO2A1_SEL_SHIFT = 2,
+ GRF_GPIO2A1_SEL_MASK = 3 << GRF_GPIO2A1_SEL_SHIFT,
+ GRF_UART2_RX_M1 = 1,
+
+ GRF_GPIO2A2_SEL_SHIFT = 4,
+ GRF_GPIO2A2_SEL_MASK = 3 << GRF_GPIO2A2_SEL_SHIFT,
+ GRF_PWM_IR = 1,
+
+ GRF_GPIO2A4_SEL_SHIFT = 8,
+ GRF_GPIO2A4_SEL_MASK = 3 << GRF_GPIO2A4_SEL_SHIFT,
+ GRF_PWM_0 = 1,
+ GRF_I2C1_SDA,
+
+ GRF_GPIO2A5_SEL_SHIFT = 10,
+ GRF_GPIO2A5_SEL_MASK = 3 << GRF_GPIO2A5_SEL_SHIFT,
+ GRF_PWM_1 = 1,
+ GRF_I2C1_SCL,
+
+ GRF_GPIO2A6_SEL_SHIFT = 12,
+ GRF_GPIO2A6_SEL_MASK = 3 << GRF_GPIO2A6_SEL_SHIFT,
+ GRF_PWM_2 = 1,
+
+ GRF_GPIO2A7_SEL_SHIFT = 14,
+ GRF_GPIO2A7_SEL_MASK = 3 << GRF_GPIO2A7_SEL_SHIFT,
+ GRF_CARD_PWR_EN_M0 = 1,
+
+ /* GRF_GPIO2BL_IOMUX */
+ GRF_GPIO2BL0_SEL_SHIFT = 0,
+ GRF_GPIO2BL0_SEL_MASK = 0x3f << GRF_GPIO2BL0_SEL_SHIFT,
+ GRF_SPI_CLK_TX_RX_M0 = 0x15,
+
+ GRF_GPIO2BL3_SEL_SHIFT = 6,
+ GRF_GPIO2BL3_SEL_MASK = 3 << GRF_GPIO2BL3_SEL_SHIFT,
+ GRF_SPI_CSN0_M0 = 1,
+
+ GRF_GPIO2BL4_SEL_SHIFT = 8,
+ GRF_GPIO2BL4_SEL_MASK = 3 << GRF_GPIO2BL4_SEL_SHIFT,
+ GRF_SPI_CSN1_M0 = 1,
+
+ GRF_GPIO2BL5_SEL_SHIFT = 10,
+ GRF_GPIO2BL5_SEL_MASK = 3 << GRF_GPIO2BL5_SEL_SHIFT,
+ GRF_I2C2_SDA = 1,
+
+ GRF_GPIO2BL6_SEL_SHIFT = 12,
+ GRF_GPIO2BL6_SEL_MASK = 3 << GRF_GPIO2BL6_SEL_SHIFT,
+ GRF_I2C2_SCL = 1,
+
+ /* GRF_GPIO2D_IOMUX */
+ GRF_GPIO2D0_SEL_SHIFT = 0,
+ GRF_GPIO2D0_SEL_MASK = 3 << GRF_GPIO2D0_SEL_SHIFT,
+ GRF_I2C0_SCL = 1,
+
+ GRF_GPIO2D1_SEL_SHIFT = 2,
+ GRF_GPIO2D1_SEL_MASK = 3 << GRF_GPIO2D1_SEL_SHIFT,
+ GRF_I2C0_SDA = 1,
+
+ GRF_GPIO2D4_SEL_SHIFT = 8,
+ GRF_GPIO2D4_SEL_MASK = 0xff << GRF_GPIO2D4_SEL_SHIFT,
+ GRF_EMMC_DATA123 = 0xaa,
+
+ /* GRF_GPIO3C_IOMUX */
+ GRF_GPIO3C0_SEL_SHIFT = 0,
+ GRF_GPIO3C0_SEL_MASK = 0x3fff << GRF_GPIO3C0_SEL_SHIFT,
+ GRF_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa,
+
+ /* GRF_COM_IOMUX */
+ GRF_UART2_IOMUX_SEL_SHIFT = 0,
+ GRF_UART2_IOMUX_SEL_MASK = 3 << GRF_UART2_IOMUX_SEL_SHIFT,
+ GRF_UART2_IOMUX_SEL_M0 = 0,
+ GRF_UART2_IOMUX_SEL_M1,
+
+ GRF_SPI_IOMUX_SEL_SHIFT = 4,
+ GRF_SPI_IOMUX_SEL_MASK = 3 << GRF_SPI_IOMUX_SEL_SHIFT,
+ GRF_SPI_IOMUX_SEL_M0 = 0,
+ GRF_SPI_IOMUX_SEL_M1,
+ GRF_SPI_IOMUX_SEL_M2,
+
+ GRF_CARD_IOMUX_SEL_SHIFT = 7,
+ GRF_CARD_IOMUX_SEL_MASK = 1 << GRF_CARD_IOMUX_SEL_SHIFT,
+ GRF_CARD_IOMUX_SEL_M0 = 0,
+ GRF_CARD_IOMUX_SEL_M1,
+};
+static void pinctrl_rk3328_pwm_config(struct rk3328_grf_regs *grf, int pwm_id)
+{
+ switch (pwm_id) {
+ case PERIPH_ID_PWM0:
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GRF_GPIO2A4_SEL_MASK,
+ GRF_PWM_0 << GRF_GPIO2A4_SEL_SHIFT);
+ break;
+ case PERIPH_ID_PWM1:
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GRF_GPIO2A5_SEL_MASK,
+ GRF_PWM_1 << GRF_GPIO2A5_SEL_SHIFT);
+ break;
+ case PERIPH_ID_PWM2:
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GRF_GPIO2A6_SEL_MASK,
+ GRF_PWM_2 << GRF_GPIO2A6_SEL_SHIFT);
+ break;
+ case PERIPH_ID_PWM3:
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GRF_GPIO2A2_SEL_MASK,
+ GRF_PWM_IR << GRF_GPIO2A2_SEL_SHIFT);
+ break;
+ default:
+ debug("pwm id = %d iomux error!\n", pwm_id);
+ break;
+ }
+}
+
+static void pinctrl_rk3328_i2c_config(struct rk3328_grf_regs *grf, int i2c_id)
+{
+ switch (i2c_id) {
+ case PERIPH_ID_I2C0:
+ rk_clrsetreg(&grf->gpio2d_iomux,
+ GRF_GPIO2D0_SEL_MASK | GRF_GPIO2D1_SEL_MASK,
+ GRF_I2C0_SCL << GRF_GPIO2D0_SEL_SHIFT
+ | GRF_I2C0_SDA << GRF_GPIO2D1_SEL_SHIFT);
+ break;
+ case PERIPH_ID_I2C1:
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GRF_GPIO2A4_SEL_MASK | GRF_GPIO2A5_SEL_MASK,
+ GRF_I2C1_SCL << GRF_GPIO2A5_SEL_SHIFT
+ | GRF_I2C1_SDA << GRF_GPIO2A4_SEL_SHIFT);
+ break;
+ case PERIPH_ID_I2C2:
+ rk_clrsetreg(&grf->gpio2bl_iomux,
+ GRF_GPIO2BL5_SEL_MASK | GRF_GPIO2BL6_SEL_MASK,
+ GRF_I2C2_SCL << GRF_GPIO2BL6_SEL_SHIFT
+ | GRF_I2C2_SDA << GRF_GPIO2BL6_SEL_SHIFT);
+ break;
+ case PERIPH_ID_I2C3:
+ rk_clrsetreg(&grf->gpio0a_iomux,
+ GRF_GPIO0A5_SEL_MASK | GRF_GPIO0A6_SEL_MASK,
+ GRF_I2C3_SCL << GRF_GPIO0A5_SEL_SHIFT
+ | GRF_I2C3_SDA << GRF_GPIO0A6_SEL_SHIFT);
+ break;
+ default:
+ debug("i2c id = %d iomux error!\n", i2c_id);
+ break;
+ }
+}
+
+static void pinctrl_rk3328_lcdc_config(struct rk3328_grf_regs *grf, int lcd_id)
+{
+ switch (lcd_id) {
+ case PERIPH_ID_LCDC0:
+ break;
+ default:
+ debug("lcdc id = %d iomux error!\n", lcd_id);
+ break;
+ }
+}
+
+static int pinctrl_rk3328_spi_config(struct rk3328_grf_regs *grf,
+ enum periph_id spi_id, int cs)
+{
+ rk_clrsetreg(&grf->com_iomux,
+ GRF_SPI_IOMUX_SEL_MASK,
+ GRF_SPI_IOMUX_SEL_M0 << GRF_SPI_IOMUX_SEL_SHIFT);
+
+ switch (spi_id) {
+ case PERIPH_ID_SPI0:
+ switch (cs) {
+ case 0:
+ rk_clrsetreg(&grf->gpio2bl_iomux,
+ GRF_GPIO2BL3_SEL_MASK,
+ GRF_SPI_CSN0_M0 << GRF_GPIO2BL3_SEL_SHIFT);
+ break;
+ case 1:
+ rk_clrsetreg(&grf->gpio2bl_iomux,
+ GRF_GPIO2BL4_SEL_MASK,
+ GRF_SPI_CSN1_M0 << GRF_GPIO2BL4_SEL_SHIFT);
+ break;
+ default:
+ goto err;
+ }
+ rk_clrsetreg(&grf->gpio2bl_iomux,
+ GRF_GPIO2BL0_SEL_MASK,
+ GRF_SPI_CLK_TX_RX_M0 << GRF_GPIO2BL0_SEL_SHIFT);
+ break;
+ default:
+ goto err;
+ }
+
+ return 0;
+err:
+ debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
+ return -ENOENT;
+}
+
+static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id)
+{
+ switch (uart_id) {
+ case PERIPH_ID_UART2:
+ break;
+ /* uart2 iomux select m1 */
+ rk_clrsetreg(&grf->com_iomux,
+ GRF_UART2_IOMUX_SEL_MASK,
+ GRF_UART2_IOMUX_SEL_M1
+ << GRF_UART2_IOMUX_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GRF_GPIO2A0_SEL_MASK | GRF_GPIO2A1_SEL_MASK,
+ GRF_UART2_TX_M1 << GRF_GPIO2A0_SEL_SHIFT |
+ GRF_UART2_RX_M1 << GRF_GPIO2A1_SEL_SHIFT);
+ break;
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART3:
+ case PERIPH_ID_UART4:
+ default:
+ debug("uart id = %d iomux error!\n", uart_id);
+ break;
+ }
+}
+
+static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf,
+ int mmc_id)
+{
+ switch (mmc_id) {
+ case PERIPH_ID_EMMC:
+ rk_clrsetreg(&grf->gpio0a_iomux,
+ GRF_GPIO0A7_SEL_MASK,
+ GRF_EMMC_DATA0 << GRF_GPIO0A7_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio2d_iomux,
+ GRF_GPIO2D4_SEL_MASK,
+ GRF_EMMC_DATA123 << GRF_GPIO2D4_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio3c_iomux,
+ GRF_GPIO3C0_SEL_MASK,
+ GRF_EMMC_DATA567_PWR_CLK_RSTN_CMD
+ << GRF_GPIO3C0_SEL_SHIFT);
+ break;
+ case PERIPH_ID_SDCARD:
+ /* sdcard iomux select m0 */
+ rk_clrsetreg(&grf->com_iomux,
+ GRF_CARD_IOMUX_SEL_MASK,
+ GRF_CARD_IOMUX_SEL_M0 << GRF_CARD_IOMUX_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GRF_GPIO2A7_SEL_MASK,
+ GRF_CARD_PWR_EN_M0 << GRF_GPIO2A7_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio1a_iomux,
+ GRF_GPIO1A0_SEL_MASK,
+ GRF_CARD_DATA_CLK_CMD_DETN
+ << GRF_GPIO1A0_SEL_SHIFT);
+ break;
+ default:
+ debug("mmc id = %d iomux error!\n", mmc_id);
+ break;
+ }
+}
+
+static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+ struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
+
+ debug("%s: func=%x, flags=%x\n", __func__, func, flags);
+ switch (func) {
+ case PERIPH_ID_PWM0:
+ case PERIPH_ID_PWM1:
+ case PERIPH_ID_PWM2:
+ case PERIPH_ID_PWM3:
+ pinctrl_rk3328_pwm_config(priv->grf, func);
+ break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ pinctrl_rk3328_i2c_config(priv->grf, func);
+ break;
+ case PERIPH_ID_SPI0:
+ pinctrl_rk3328_spi_config(priv->grf, func, flags);
+ break;
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ case PERIPH_ID_UART4:
+ pinctrl_rk3328_uart_config(priv->grf, func);
+ break;
+ case PERIPH_ID_LCDC0:
+ case PERIPH_ID_LCDC1:
+ pinctrl_rk3328_lcdc_config(priv->grf, func);
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ pinctrl_rk3328_sdmmc_config(priv->grf, func);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int rk3328_pinctrl_get_periph_id(struct udevice *dev,
+ struct udevice *periph)
+{
+ u32 cell[3];
+ int ret;
+
+ ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+ "interrupts", cell, ARRAY_SIZE(cell));
+ if (ret < 0)
+ return -EINVAL;
+
+ switch (cell[1]) {
+ case 49:
+ return PERIPH_ID_SPI0;
+ case 50:
+ return PERIPH_ID_PWM0;
+ case 36:
+ return PERIPH_ID_I2C0;
+ case 37: /* Note strange order */
+ return PERIPH_ID_I2C1;
+ case 38:
+ return PERIPH_ID_I2C2;
+ case 39:
+ return PERIPH_ID_I2C3;
+ case 12:
+ return PERIPH_ID_SDCARD;
+ case 14:
+ return PERIPH_ID_EMMC;
+ }
+
+ return -ENOENT;
+}
+
+static int rk3328_pinctrl_set_state_simple(struct udevice *dev,
+ struct udevice *periph)
+{
+ int func;
+
+ func = rk3328_pinctrl_get_periph_id(dev, periph);
+ if (func < 0)
+ return func;
+
+ return rk3328_pinctrl_request(dev, func, 0);
+}
+
+static struct pinctrl_ops rk3328_pinctrl_ops = {
+ .set_state_simple = rk3328_pinctrl_set_state_simple,
+ .request = rk3328_pinctrl_request,
+ .get_periph_id = rk3328_pinctrl_get_periph_id,
+};
+
+static int rk3328_pinctrl_probe(struct udevice *dev)
+{
+ struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
+ int ret = 0;
+
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ debug("%s: grf=%p\n", __func__, priv->grf);
+
+ return ret;
+}
+
+static const struct udevice_id rk3328_pinctrl_ids[] = {
+ { .compatible = "rockchip,rk3328-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_rk3328) = {
+ .name = "rockchip_rk3328_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = rk3328_pinctrl_ids,
+ .priv_auto_alloc_size = sizeof(struct rk3328_pinctrl_priv),
+ .ops = &rk3328_pinctrl_ops,
+ .bind = dm_scan_fdt_dev,
+ .probe = rk3328_pinctrl_probe,
+};
diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h
index 56887e1..ecb76c7 100644
--- a/include/dt-bindings/pinctrl/rockchip.h
+++ b/include/dt-bindings/pinctrl/rockchip.h
@@ -22,5 +22,7 @@
#define RK_FUNC_2 2
#define RK_FUNC_3 3
#define RK_FUNC_4 4
+#define RK_FUNC_5 5
+#define RK_FUNC_6 6
#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [U-Boot] [PATCH 4/7] pinctrl: rockchip: add support for rk3328
2017-02-17 8:07 ` [U-Boot] [PATCH 4/7] pinctrl: " Kever Yang
@ 2017-02-21 18:06 ` Simon Glass
0 siblings, 0 replies; 18+ messages in thread
From: Simon Glass @ 2017-02-21 18:06 UTC (permalink / raw)
To: u-boot
Hi Kever,
On 17 February 2017 at 01:07, Kever Yang <kever.yang@rock-chips.com> wrote:
> Add rk3328 pinctrl driver and grf/iomux structure definition.
>
> Signed-off-by: William Zhang <william.zhang@rock-chips.com>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 134 ++++++++
> drivers/pinctrl/Kconfig | 9 +
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl_rk3328.c | 418 ++++++++++++++++++++++++
> include/dt-bindings/pinctrl/rockchip.h | 2 +
> 5 files changed, 564 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3328.h
> create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3328.c
Acked-by: Simon Glass <sjg@chromium.org>
Nits below.
[...]
In your clock structures, please add space around operators:
+ u32 reserved1[(0x100-0x54)/4];
[(0x100 - 0x54) / 4]
> diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
> new file mode 100644
> index 0000000..3fa334f
> --- /dev/null
> +++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
> @@ -0,0 +1,418 @@
> +/*
> + * (C) Copyright 2016 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/grf_rk3328.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/arch/periph.h>
> +#include <asm/io.h>
> +#include <dm.h>
> +#include <dm/pinctrl.h>
> +#include <errno.h>
> +#include <syscon.h>
Please fix header order.
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct rk3328_pinctrl_priv {
> + struct rk3328_grf_regs *grf;
> +};
> +
> +enum {
> + /* GRF_GPIO0A_IOMUX */
> + GRF_GPIO0A5_SEL_SHIFT = 10,
> + GRF_GPIO0A5_SEL_MASK = 3 << GRF_GPIO0A5_SEL_SHIFT,
> + GRF_I2C3_SCL = 2,
> +
> + GRF_GPIO0A6_SEL_SHIFT = 12,
> + GRF_GPIO0A6_SEL_MASK = 3 << GRF_GPIO0A6_SEL_SHIFT,
> + GRF_I2C3_SDA = 2,
> +
> + GRF_GPIO0A7_SEL_SHIFT = 14,
> + GRF_GPIO0A7_SEL_MASK = 3 << GRF_GPIO0A7_SEL_SHIFT,
> + GRF_EMMC_DATA0 = 2,
> +
> + /* GRF_GPIO1A_IOMUX */
> + GRF_GPIO1A0_SEL_SHIFT = 0,
> + GRF_GPIO1A0_SEL_MASK = 0x3fff << GRF_GPIO1A0_SEL_SHIFT,
> + GRF_CARD_DATA_CLK_CMD_DETN = 0x1555,
> +
> + /* GRF_GPIO2A_IOMUX */
> + GRF_GPIO2A0_SEL_SHIFT = 0,
> + GRF_GPIO2A0_SEL_MASK = 3 << GRF_GPIO2A0_SEL_SHIFT,
> + GRF_UART2_TX_M1 = 1,
> +
> + GRF_GPIO2A1_SEL_SHIFT = 2,
> + GRF_GPIO2A1_SEL_MASK = 3 << GRF_GPIO2A1_SEL_SHIFT,
> + GRF_UART2_RX_M1 = 1,
> +
> + GRF_GPIO2A2_SEL_SHIFT = 4,
> + GRF_GPIO2A2_SEL_MASK = 3 << GRF_GPIO2A2_SEL_SHIFT,
> + GRF_PWM_IR = 1,
> +
> + GRF_GPIO2A4_SEL_SHIFT = 8,
> + GRF_GPIO2A4_SEL_MASK = 3 << GRF_GPIO2A4_SEL_SHIFT,
> + GRF_PWM_0 = 1,
> + GRF_I2C1_SDA,
> +
> + GRF_GPIO2A5_SEL_SHIFT = 10,
> + GRF_GPIO2A5_SEL_MASK = 3 << GRF_GPIO2A5_SEL_SHIFT,
> + GRF_PWM_1 = 1,
> + GRF_I2C1_SCL,
> +
> + GRF_GPIO2A6_SEL_SHIFT = 12,
> + GRF_GPIO2A6_SEL_MASK = 3 << GRF_GPIO2A6_SEL_SHIFT,
> + GRF_PWM_2 = 1,
> +
> + GRF_GPIO2A7_SEL_SHIFT = 14,
> + GRF_GPIO2A7_SEL_MASK = 3 << GRF_GPIO2A7_SEL_SHIFT,
> + GRF_CARD_PWR_EN_M0 = 1,
> +
> + /* GRF_GPIO2BL_IOMUX */
> + GRF_GPIO2BL0_SEL_SHIFT = 0,
> + GRF_GPIO2BL0_SEL_MASK = 0x3f << GRF_GPIO2BL0_SEL_SHIFT,
> + GRF_SPI_CLK_TX_RX_M0 = 0x15,
> +
> + GRF_GPIO2BL3_SEL_SHIFT = 6,
> + GRF_GPIO2BL3_SEL_MASK = 3 << GRF_GPIO2BL3_SEL_SHIFT,
> + GRF_SPI_CSN0_M0 = 1,
> +
> + GRF_GPIO2BL4_SEL_SHIFT = 8,
> + GRF_GPIO2BL4_SEL_MASK = 3 << GRF_GPIO2BL4_SEL_SHIFT,
> + GRF_SPI_CSN1_M0 = 1,
> +
> + GRF_GPIO2BL5_SEL_SHIFT = 10,
> + GRF_GPIO2BL5_SEL_MASK = 3 << GRF_GPIO2BL5_SEL_SHIFT,
> + GRF_I2C2_SDA = 1,
> +
> + GRF_GPIO2BL6_SEL_SHIFT = 12,
> + GRF_GPIO2BL6_SEL_MASK = 3 << GRF_GPIO2BL6_SEL_SHIFT,
> + GRF_I2C2_SCL = 1,
> +
> + /* GRF_GPIO2D_IOMUX */
> + GRF_GPIO2D0_SEL_SHIFT = 0,
> + GRF_GPIO2D0_SEL_MASK = 3 << GRF_GPIO2D0_SEL_SHIFT,
> + GRF_I2C0_SCL = 1,
> +
> + GRF_GPIO2D1_SEL_SHIFT = 2,
> + GRF_GPIO2D1_SEL_MASK = 3 << GRF_GPIO2D1_SEL_SHIFT,
> + GRF_I2C0_SDA = 1,
> +
> + GRF_GPIO2D4_SEL_SHIFT = 8,
> + GRF_GPIO2D4_SEL_MASK = 0xff << GRF_GPIO2D4_SEL_SHIFT,
> + GRF_EMMC_DATA123 = 0xaa,
> +
> + /* GRF_GPIO3C_IOMUX */
> + GRF_GPIO3C0_SEL_SHIFT = 0,
> + GRF_GPIO3C0_SEL_MASK = 0x3fff << GRF_GPIO3C0_SEL_SHIFT,
> + GRF_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa,
> +
> + /* GRF_COM_IOMUX */
> + GRF_UART2_IOMUX_SEL_SHIFT = 0,
> + GRF_UART2_IOMUX_SEL_MASK = 3 << GRF_UART2_IOMUX_SEL_SHIFT,
> + GRF_UART2_IOMUX_SEL_M0 = 0,
> + GRF_UART2_IOMUX_SEL_M1,
> +
> + GRF_SPI_IOMUX_SEL_SHIFT = 4,
> + GRF_SPI_IOMUX_SEL_MASK = 3 << GRF_SPI_IOMUX_SEL_SHIFT,
> + GRF_SPI_IOMUX_SEL_M0 = 0,
> + GRF_SPI_IOMUX_SEL_M1,
> + GRF_SPI_IOMUX_SEL_M2,
> +
> + GRF_CARD_IOMUX_SEL_SHIFT = 7,
> + GRF_CARD_IOMUX_SEL_MASK = 1 << GRF_CARD_IOMUX_SEL_SHIFT,
> + GRF_CARD_IOMUX_SEL_M0 = 0,
> + GRF_CARD_IOMUX_SEL_M1,
> +};
blank line here
> +static void pinctrl_rk3328_pwm_config(struct rk3328_grf_regs *grf, int pwm_id)
> +{
> + switch (pwm_id) {
> + case PERIPH_ID_PWM0:
> + rk_clrsetreg(&grf->gpio2a_iomux,
> + GRF_GPIO2A4_SEL_MASK,
> + GRF_PWM_0 << GRF_GPIO2A4_SEL_SHIFT);
> + break;
> + case PERIPH_ID_PWM1:
> + rk_clrsetreg(&grf->gpio2a_iomux,
> + GRF_GPIO2A5_SEL_MASK,
> + GRF_PWM_1 << GRF_GPIO2A5_SEL_SHIFT);
> + break;
> + case PERIPH_ID_PWM2:
> + rk_clrsetreg(&grf->gpio2a_iomux,
> + GRF_GPIO2A6_SEL_MASK,
> + GRF_PWM_2 << GRF_GPIO2A6_SEL_SHIFT);
> + break;
> + case PERIPH_ID_PWM3:
> + rk_clrsetreg(&grf->gpio2a_iomux,
> + GRF_GPIO2A2_SEL_MASK,
> + GRF_PWM_IR << GRF_GPIO2A2_SEL_SHIFT);
> + break;
> + default:
> + debug("pwm id = %d iomux error!\n", pwm_id);
> + break;
> + }
> +}
> +
Regards,
Simon
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 5/7] sysreset: add support for rockchip rk3328 soc
2017-02-17 8:07 [U-Boot] [PATCH 0/7] add support for rk3328 SoC Kever Yang
` (3 preceding siblings ...)
2017-02-17 8:07 ` [U-Boot] [PATCH 4/7] pinctrl: " Kever Yang
@ 2017-02-17 8:07 ` Kever Yang
2017-02-21 18:06 ` Simon Glass
2017-02-17 8:07 ` [U-Boot] [PATCH 6/7] board: rockchip: add support for rk3328 evb Kever Yang
` (2 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Kever Yang @ 2017-02-17 8:07 UTC (permalink / raw)
To: u-boot
Add rk3328 sysreset driver.
Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_rk3328.c | 45 ++++++++++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+)
create mode 100644 drivers/sysreset/sysreset_rk3328.c
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index 37638a8..12cfa79 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -10,6 +10,7 @@ ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o
endif
obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3328) += sysreset_rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o
obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
diff --git a/drivers/sysreset/sysreset_rk3328.c b/drivers/sysreset/sysreset_rk3328.c
new file mode 100644
index 0000000..7b22342
--- /dev/null
+++ b/drivers/sysreset/sysreset_rk3328.c
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3328.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <errno.h>
+#include <linux/err.h>
+#include <sysreset.h>
+
+int rk3328_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct rk3328_cru *cru = rockchip_get_cru();
+
+ if (IS_ERR(cru))
+ return PTR_ERR(cru);
+ switch (type) {
+ case SYSRESET_WARM:
+ writel(0xeca8, &cru->glb_srst_snd_value);
+ break;
+ case SYSRESET_COLD:
+ writel(0xfdb9, &cru->glb_srst_fst_value);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops rk3328_sysreset = {
+ .request = rk3328_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_rk3328) = {
+ .name = "rk3328_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &rk3328_sysreset,
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [U-Boot] [PATCH 5/7] sysreset: add support for rockchip rk3328 soc
2017-02-17 8:07 ` [U-Boot] [PATCH 5/7] sysreset: add support for rockchip rk3328 soc Kever Yang
@ 2017-02-21 18:06 ` Simon Glass
0 siblings, 0 replies; 18+ messages in thread
From: Simon Glass @ 2017-02-21 18:06 UTC (permalink / raw)
To: u-boot
On 17 February 2017 at 01:07, Kever Yang <kever.yang@rock-chips.com> wrote:
> Add rk3328 sysreset driver.
>
> Signed-off-by: William Zhang <william.zhang@rock-chips.com>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> drivers/sysreset/Makefile | 1 +
> drivers/sysreset/sysreset_rk3328.c | 45 ++++++++++++++++++++++++++++++++++++++
> 2 files changed, 46 insertions(+)
> create mode 100644 drivers/sysreset/sysreset_rk3328.c
Acked-by: Simon Glass <sjg@chromium.org>
Nit below.
>
> diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
> index 37638a8..12cfa79 100644
> --- a/drivers/sysreset/Makefile
> +++ b/drivers/sysreset/Makefile
> @@ -10,6 +10,7 @@ ifndef CONFIG_SPL_BUILD
> obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o
> endif
> obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o
> +obj-$(CONFIG_ROCKCHIP_RK3328) += sysreset_rk3328.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o
> obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
> obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
> diff --git a/drivers/sysreset/sysreset_rk3328.c b/drivers/sysreset/sysreset_rk3328.c
> new file mode 100644
> index 0000000..7b22342
> --- /dev/null
> +++ b/drivers/sysreset/sysreset_rk3328.c
> @@ -0,0 +1,45 @@
> +/*
> + * (C) Copyright 2016 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk3328.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/io.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <linux/err.h>
> +#include <sysreset.h>
Please fix header file order.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 6/7] board: rockchip: add support for rk3328 evb
2017-02-17 8:07 [U-Boot] [PATCH 0/7] add support for rk3328 SoC Kever Yang
` (4 preceding siblings ...)
2017-02-17 8:07 ` [U-Boot] [PATCH 5/7] sysreset: add support for rockchip rk3328 soc Kever Yang
@ 2017-02-17 8:07 ` Kever Yang
2017-02-21 18:07 ` Simon Glass
2017-02-17 8:07 ` [U-Boot] [PATCH 7/7] config: add support for evb-rk3328 Kever Yang
2017-02-21 18:07 ` [U-Boot] [PATCH 0/7] add support for rk3328 SoC Simon Glass
7 siblings, 1 reply; 18+ messages in thread
From: Kever Yang @ 2017-02-17 8:07 UTC (permalink / raw)
To: u-boot
evb-rk3328 is an evb from Rockchip based on rk3328 SoC:
- 2 USB2.0 Host port;
- 1 USB3.0 Host port;
- 1 HDMI port;
- 2 10/100M eth port;
- 2GB ddr;
- 16GB eMMC;
- UART to USB debug port;
Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
board/rockchip/evb_rk3328/Kconfig | 15 ++++++++
board/rockchip/evb_rk3328/MAINTAINERS | 6 +++
board/rockchip/evb_rk3328/Makefile | 7 ++++
board/rockchip/evb_rk3328/README | 70 ++++++++++++++++++++++++++++++++++
board/rockchip/evb_rk3328/evb-rk3328.c | 40 +++++++++++++++++++
include/configs/evb_rk3328.h | 26 +++++++++++++
6 files changed, 164 insertions(+)
create mode 100644 board/rockchip/evb_rk3328/Kconfig
create mode 100644 board/rockchip/evb_rk3328/MAINTAINERS
create mode 100644 board/rockchip/evb_rk3328/Makefile
create mode 100644 board/rockchip/evb_rk3328/README
create mode 100644 board/rockchip/evb_rk3328/evb-rk3328.c
create mode 100644 include/configs/evb_rk3328.h
diff --git a/board/rockchip/evb_rk3328/Kconfig b/board/rockchip/evb_rk3328/Kconfig
new file mode 100644
index 0000000..ef446b4
--- /dev/null
+++ b/board/rockchip/evb_rk3328/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3328
+
+config SYS_BOARD
+ default "evb_rk3328"
+
+config SYS_VENDOR
+ default "rockchip"
+
+config SYS_CONFIG_NAME
+ default "evb_rk3328"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS
new file mode 100644
index 0000000..9db604f
--- /dev/null
+++ b/board/rockchip/evb_rk3328/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3328
+M: William Zhang <william.zhang@rock-chips.com>
+S: Maintained
+F: board/rockchip/evb_rk3328
+F: include/configs/evb_rk3328.h
+F: configs/evb-rk3328_defconfig
diff --git a/board/rockchip/evb_rk3328/Makefile b/board/rockchip/evb_rk3328/Makefile
new file mode 100644
index 0000000..81c5de8
--- /dev/null
+++ b/board/rockchip/evb_rk3328/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += evb-rk3328.o
diff --git a/board/rockchip/evb_rk3328/README b/board/rockchip/evb_rk3328/README
new file mode 100644
index 0000000..d0a0df3
--- /dev/null
+++ b/board/rockchip/evb_rk3328/README
@@ -0,0 +1,70 @@
+Introduction
+============
+
+RK3328 key features we might use in U-Boot:
+* CPU: ARMv8 64bit quad-core Cortex-A53
+* IRAM: 36KB
+* DRAM: 4GB-16MB dual-channel
+* eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50
+* SD/MMC: support SD 3.0, MMC 4.51
+* USB: USB2.0 EHCI host port *2
+* Display: RGB/HDMI/DP/MIPI/EDP
+
+evb key features:
+* regulator: pwm regulator for CPU B/L
+* PMIC: rk808
+* debug console: UART2
+
+In order to support Arm Trust Firmware(ATF), we need to use the
+miniloader from rockchip which:
+* do DRAM init
+* load and verify ATF image
+* load and verify U-Boot image
+
+Here is the step-by-step to boot to U-Boot on rk3328.
+
+Get the Source and prebuild binary
+==================================
+
+ > mkdir ~/evb_rk3328
+ > cd ~/evb_rk3328
+ > git clone https://github.com/ARM-software/arm-trusted-firmware.git
+ > git clone https://github.com/rockchip-linux/rkbin
+ > git clone https://github.com/rockchip-linux/rkflashtool
+
+Compile the ATF
+===============
+
+ > cd arm-trusted-firmware
+ > make realclean
+ > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3328 bl31
+
+Compile the U-Boot
+==================
+
+ > cd ../u-boot
+ > make CROSS_COMPILE=aarch64-linux-gnu- evb-rk3328_defconfig all
+
+Compile the rkflashtool
+=======================
+
+ > cd ../rkflashtool
+ > make
+
+Package the image for miniloader
+================================
+ > cd ..
+ > cp arm-trusted-firmware/build/rk3328/release/bl31.bin rkbin/rk33
+ > ./rkbin/tools/trust_merger rkbin/tools/RK3328TRUST.ini
+ > ./rkbin/tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img
+ > mkdir image
+ > mv trust.img ./image/
+ > mv uboot.img ./image/rk3328evb-uboot.bin
+
+Flash the image
+===============
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+
+ > ./rkflashtool/rkflashloader rk3328evb
+
+You should be able to get U-Boot log message in console/UART2 now.
diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c
new file mode 100644
index 0000000..7e70f38
--- /dev/null
+++ b/board/rockchip/evb_rk3328/evb-rk3328.c
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <dwc3-uboot.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = 0x80000000;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ /* Reserve 0x200000 for ATF bl31 */
+ gd->bd->bi_dram[0].start = 0x200000;
+ gd->bd->bi_dram[0].size = 0x7e000000;
+}
+
+int usb_gadget_handle_interrupts(void)
+{
+ return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ return 0;
+}
diff --git a/include/configs/evb_rk3328.h b/include/configs/evb_rk3328.h
new file mode 100644
index 0000000..3a39a1b
--- /dev/null
+++ b/include/configs/evb_rk3328.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __EVB_RK3328_H
+#define __EVB_RK3328_H
+
+#include <configs/rk3328_common.h>
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 1
+/*
+ * SPL @ 32k for ~36k
+ * ENV @ 96k
+ * u-boot @ 128K
+ */
+#define CONFIG_ENV_OFFSET (96 * 1024)
+
+#define SDRAM_BANK_SIZE (2UL << 30)
+
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES 10
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [U-Boot] [PATCH 6/7] board: rockchip: add support for rk3328 evb
2017-02-17 8:07 ` [U-Boot] [PATCH 6/7] board: rockchip: add support for rk3328 evb Kever Yang
@ 2017-02-21 18:07 ` Simon Glass
0 siblings, 0 replies; 18+ messages in thread
From: Simon Glass @ 2017-02-21 18:07 UTC (permalink / raw)
To: u-boot
On 17 February 2017 at 01:07, Kever Yang <kever.yang@rock-chips.com> wrote:
> evb-rk3328 is an evb from Rockchip based on rk3328 SoC:
> - 2 USB2.0 Host port;
> - 1 USB3.0 Host port;
> - 1 HDMI port;
> - 2 10/100M eth port;
> - 2GB ddr;
> - 16GB eMMC;
> - UART to USB debug port;
>
> Signed-off-by: William Zhang <william.zhang@rock-chips.com>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> board/rockchip/evb_rk3328/Kconfig | 15 ++++++++
> board/rockchip/evb_rk3328/MAINTAINERS | 6 +++
> board/rockchip/evb_rk3328/Makefile | 7 ++++
> board/rockchip/evb_rk3328/README | 70 ++++++++++++++++++++++++++++++++++
> board/rockchip/evb_rk3328/evb-rk3328.c | 40 +++++++++++++++++++
> include/configs/evb_rk3328.h | 26 +++++++++++++
> 6 files changed, 164 insertions(+)
> create mode 100644 board/rockchip/evb_rk3328/Kconfig
> create mode 100644 board/rockchip/evb_rk3328/MAINTAINERS
> create mode 100644 board/rockchip/evb_rk3328/Makefile
> create mode 100644 board/rockchip/evb_rk3328/README
> create mode 100644 board/rockchip/evb_rk3328/evb-rk3328.c
> create mode 100644 include/configs/evb_rk3328.h
Acked-by: Simon Glass <sjg@chromium.org>
nits: In your README I think it would read better to say "Compile ATF"
and "Compile U-Boot" instead of "Compile the ATF", etc. The word 'the'
isn't needed.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 7/7] config: add support for evb-rk3328
2017-02-17 8:07 [U-Boot] [PATCH 0/7] add support for rk3328 SoC Kever Yang
` (5 preceding siblings ...)
2017-02-17 8:07 ` [U-Boot] [PATCH 6/7] board: rockchip: add support for rk3328 evb Kever Yang
@ 2017-02-17 8:07 ` Kever Yang
2017-02-21 18:07 ` Simon Glass
2017-02-21 18:07 ` [U-Boot] [PATCH 0/7] add support for rk3328 SoC Simon Glass
7 siblings, 1 reply; 18+ messages in thread
From: Kever Yang @ 2017-02-17 8:07 UTC (permalink / raw)
To: u-boot
Enable board config for evb-rk3328.
SDcard and eMMC boot is OK in this initial version,
USB and EMAC function is not available now, will comes later.
Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
configs/evb-rk3328_defconfig | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 configs/evb-rk3328_defconfig
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
new file mode 100644
index 0000000..df22105
--- /dev/null
+++ b/configs/evb-rk3328_defconfig
@@ -0,0 +1,36 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb"
+CONFIG_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_ROCKCHIP_RK3328_PINCTRL=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_RAM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_ERRNO_STR=y
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [U-Boot] [PATCH 7/7] config: add support for evb-rk3328
2017-02-17 8:07 ` [U-Boot] [PATCH 7/7] config: add support for evb-rk3328 Kever Yang
@ 2017-02-21 18:07 ` Simon Glass
0 siblings, 0 replies; 18+ messages in thread
From: Simon Glass @ 2017-02-21 18:07 UTC (permalink / raw)
To: u-boot
On 17 February 2017 at 01:07, Kever Yang <kever.yang@rock-chips.com> wrote:
> Enable board config for evb-rk3328.
> SDcard and eMMC boot is OK in this initial version,
> USB and EMAC function is not available now, will comes later.
>
> Signed-off-by: William Zhang <william.zhang@rock-chips.com>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> configs/evb-rk3328_defconfig | 36 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
> create mode 100644 configs/evb-rk3328_defconfig
Acked-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 0/7] add support for rk3328 SoC
2017-02-17 8:07 [U-Boot] [PATCH 0/7] add support for rk3328 SoC Kever Yang
` (6 preceding siblings ...)
2017-02-17 8:07 ` [U-Boot] [PATCH 7/7] config: add support for evb-rk3328 Kever Yang
@ 2017-02-21 18:07 ` Simon Glass
7 siblings, 0 replies; 18+ messages in thread
From: Simon Glass @ 2017-02-21 18:07 UTC (permalink / raw)
To: u-boot
Hi Kever,
On 17 February 2017 at 01:07, Kever Yang <kever.yang@rock-chips.com> wrote:
> This patchset is to support rk3328 Soc, including some basic
> driver like clock, pinctrl, sysreset and etc. This version
> enables eMMC and sd-card boot, USB and MAC driver is not ready.
>
> RK3328 is a quad-core cortex-A53 SoC, it needs ATF support,
> so I would like to send the U-Boot driver without SPL in this
> version, for the ATF patches is still under discussion, we'd
> better have a version which able to work.
>
>
>
> Kever Yang (7):
> arm64: dts: add support for Rockchip rk3328 soc
> ARM64: rockchip: add support for rk3328 SoC
> clk: rockchip: add support for rk3328
> pinctrl: rockchip: add support for rk3328
> sysreset: add support for rockchip rk3328 soc
> board: rockchip: add support for rk3328 evb
> config: add support for evb-rk3328
With v2, can you please make sure that the 'rockchip:' tag is first,
and that all rockchip patches have it?
Regards,
Simon
^ permalink raw reply [flat|nested] 18+ messages in thread