* [U-Boot] [PATCH v2 01/10] powerpc, 8xx: move immap.c in arch/powerpc/cpu/mpc8xx/
2017-07-06 8:33 [U-Boot] [PATCH v2 0/10] powerpc, 8xx: Modernise the 8xx Christophe Leroy
@ 2017-07-06 8:33 ` Christophe Leroy
2017-07-06 8:41 ` Christophe LEROY
` (2 more replies)
2017-07-06 8:33 ` [U-Boot] [PATCH v2 02/10] powerpc, 8xx: move specific reginfo Christophe Leroy
` (8 subsequent siblings)
9 siblings, 3 replies; 35+ messages in thread
From: Christophe Leroy @ 2017-07-06 8:33 UTC (permalink / raw)
To: u-boot
immap.c used to be common to several CPUs. It is now
only linked to the 8xx, so this patch moves it into
arch/powerpc/cpu/mpc8xx/
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/Kconfig | 2 --
arch/powerpc/cpu/mpc8xx/Kconfig | 9 +++++++++
arch/powerpc/cpu/mpc8xx/Makefile | 1 +
arch/powerpc/{lib => cpu/mpc8xx}/immap.c | 3 ---
arch/powerpc/lib/Kconfig | 7 -------
arch/powerpc/lib/Makefile | 1 -
6 files changed, 10 insertions(+), 13 deletions(-)
rename arch/powerpc/{lib => cpu/mpc8xx}/immap.c (99%)
delete mode 100644 arch/powerpc/lib/Kconfig
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index a7558d59b2..e9002a76ab 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -34,8 +34,6 @@ config 8xx
endchoice
-source "arch/powerpc/lib/Kconfig"
-
source "arch/powerpc/cpu/mpc83xx/Kconfig"
source "arch/powerpc/cpu/mpc85xx/Kconfig"
source "arch/powerpc/cpu/mpc86xx/Kconfig"
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index a425cba8aa..cb15dc5ebc 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -10,4 +10,13 @@ choice
endchoice
+comment "Specific commands"
+
+config CMD_IMMAP
+ bool "Enable various commands to dump IMMR information"
+ help
+ This enables various commands such as:
+
+ siuinfo - print System Interface Unit (SIU) registers
+ memcinfo - print Memory Controller registers
endmenu
diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile
index 5dd801d76e..eae02da636 100644
--- a/arch/powerpc/cpu/mpc8xx/Makefile
+++ b/arch/powerpc/cpu/mpc8xx/Makefile
@@ -11,6 +11,7 @@ obj-y += cpu.o
obj-y += cpu_init.o
obj-y += fec.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_CMD_IMMAP) += immap.o
obj-y += interrupts.o
obj-y += serial.o
obj-y += speed.o
diff --git a/arch/powerpc/lib/immap.c b/arch/powerpc/cpu/mpc8xx/immap.c
similarity index 99%
rename from arch/powerpc/lib/immap.c
rename to arch/powerpc/cpu/mpc8xx/immap.c
index 1beed1fa40..5ff6aa5e3b 100644
--- a/arch/powerpc/lib/immap.c
+++ b/arch/powerpc/cpu/mpc8xx/immap.c
@@ -12,8 +12,6 @@
#include <common.h>
#include <command.h>
-#if defined(CONFIG_8xx)
-
#include <asm/8xx_immap.h>
#include <commproc.h>
#include <asm/iopin_8xx.h>
@@ -394,4 +392,3 @@ U_BOOT_CMD(
"print Baud Rate Generator (BRG) registers",
""
);
-#endif
diff --git a/arch/powerpc/lib/Kconfig b/arch/powerpc/lib/Kconfig
deleted file mode 100644
index 7c8ea971c3..0000000000
--- a/arch/powerpc/lib/Kconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-config CMD_IMMAP
- bool "Enable various commands to dump IMMR information"
- help
- This enables various commands such as:
-
- siuinfo - print System Interface Unit (SIU) registers
- memcinfo - print Memory Controller registers
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 4aa41836a2..9a3043abf8 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -32,7 +32,6 @@ obj-$(CONFIG_BAT_RW) += bat_rw.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += cache.o
obj-y += extable.o
-obj-$(CONFIG_CMD_IMMAP) += immap.o
obj-y += interrupts.o
obj-$(CONFIG_CMD_KGDB) += kgdb.o
obj-y += stack.o
--
2.12.0
^ permalink raw reply related [flat|nested] 35+ messages in thread* [U-Boot] [PATCH v2 01/10] powerpc, 8xx: move immap.c in arch/powerpc/cpu/mpc8xx/
2017-07-06 8:33 ` [U-Boot] [PATCH v2 01/10] powerpc, 8xx: move immap.c in arch/powerpc/cpu/mpc8xx/ Christophe Leroy
@ 2017-07-06 8:41 ` Christophe LEROY
2017-07-06 9:40 ` Heiko Schocher
2017-07-09 0:24 ` [U-Boot] [U-Boot, v2, " Tom Rini
2 siblings, 0 replies; 35+ messages in thread
From: Christophe LEROY @ 2017-07-06 8:41 UTC (permalink / raw)
To: u-boot
Le 06/07/2017 à 10:33, Christophe Leroy a écrit :
> immap.c used to be common to several CPUs. It is now
> only linked to the 8xx, so this patch moves it into
> arch/powerpc/cpu/mpc8xx/
>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
Forgot to tell that this serie applies after '[v6] powerpc: Partialy
restore core of mpc8xx'
Christophe
> arch/powerpc/Kconfig | 2 --
> arch/powerpc/cpu/mpc8xx/Kconfig | 9 +++++++++
> arch/powerpc/cpu/mpc8xx/Makefile | 1 +
> arch/powerpc/{lib => cpu/mpc8xx}/immap.c | 3 ---
> arch/powerpc/lib/Kconfig | 7 -------
> arch/powerpc/lib/Makefile | 1 -
> 6 files changed, 10 insertions(+), 13 deletions(-)
> rename arch/powerpc/{lib => cpu/mpc8xx}/immap.c (99%)
> delete mode 100644 arch/powerpc/lib/Kconfig
>
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index a7558d59b2..e9002a76ab 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -34,8 +34,6 @@ config 8xx
>
> endchoice
>
> -source "arch/powerpc/lib/Kconfig"
> -
> source "arch/powerpc/cpu/mpc83xx/Kconfig"
> source "arch/powerpc/cpu/mpc85xx/Kconfig"
> source "arch/powerpc/cpu/mpc86xx/Kconfig"
> diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
> index a425cba8aa..cb15dc5ebc 100644
> --- a/arch/powerpc/cpu/mpc8xx/Kconfig
> +++ b/arch/powerpc/cpu/mpc8xx/Kconfig
> @@ -10,4 +10,13 @@ choice
>
> endchoice
>
> +comment "Specific commands"
> +
> +config CMD_IMMAP
> + bool "Enable various commands to dump IMMR information"
> + help
> + This enables various commands such as:
> +
> + siuinfo - print System Interface Unit (SIU) registers
> + memcinfo - print Memory Controller registers
> endmenu
> diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile
> index 5dd801d76e..eae02da636 100644
> --- a/arch/powerpc/cpu/mpc8xx/Makefile
> +++ b/arch/powerpc/cpu/mpc8xx/Makefile
> @@ -11,6 +11,7 @@ obj-y += cpu.o
> obj-y += cpu_init.o
> obj-y += fec.o
> obj-$(CONFIG_OF_LIBFDT) += fdt.o
> +obj-$(CONFIG_CMD_IMMAP) += immap.o
> obj-y += interrupts.o
> obj-y += serial.o
> obj-y += speed.o
> diff --git a/arch/powerpc/lib/immap.c b/arch/powerpc/cpu/mpc8xx/immap.c
> similarity index 99%
> rename from arch/powerpc/lib/immap.c
> rename to arch/powerpc/cpu/mpc8xx/immap.c
> index 1beed1fa40..5ff6aa5e3b 100644
> --- a/arch/powerpc/lib/immap.c
> +++ b/arch/powerpc/cpu/mpc8xx/immap.c
> @@ -12,8 +12,6 @@
> #include <common.h>
> #include <command.h>
>
> -#if defined(CONFIG_8xx)
> -
> #include <asm/8xx_immap.h>
> #include <commproc.h>
> #include <asm/iopin_8xx.h>
> @@ -394,4 +392,3 @@ U_BOOT_CMD(
> "print Baud Rate Generator (BRG) registers",
> ""
> );
> -#endif
> diff --git a/arch/powerpc/lib/Kconfig b/arch/powerpc/lib/Kconfig
> deleted file mode 100644
> index 7c8ea971c3..0000000000
> --- a/arch/powerpc/lib/Kconfig
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -config CMD_IMMAP
> - bool "Enable various commands to dump IMMR information"
> - help
> - This enables various commands such as:
> -
> - siuinfo - print System Interface Unit (SIU) registers
> - memcinfo - print Memory Controller registers
> diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
> index 4aa41836a2..9a3043abf8 100644
> --- a/arch/powerpc/lib/Makefile
> +++ b/arch/powerpc/lib/Makefile
> @@ -32,7 +32,6 @@ obj-$(CONFIG_BAT_RW) += bat_rw.o
> obj-$(CONFIG_CMD_BOOTM) += bootm.o
> obj-y += cache.o
> obj-y += extable.o
> -obj-$(CONFIG_CMD_IMMAP) += immap.o
> obj-y += interrupts.o
> obj-$(CONFIG_CMD_KGDB) += kgdb.o
> obj-y += stack.o
>
^ permalink raw reply [flat|nested] 35+ messages in thread* [U-Boot] [PATCH v2 01/10] powerpc, 8xx: move immap.c in arch/powerpc/cpu/mpc8xx/
2017-07-06 8:33 ` [U-Boot] [PATCH v2 01/10] powerpc, 8xx: move immap.c in arch/powerpc/cpu/mpc8xx/ Christophe Leroy
2017-07-06 8:41 ` Christophe LEROY
@ 2017-07-06 9:40 ` Heiko Schocher
2017-07-09 0:24 ` [U-Boot] [U-Boot, v2, " Tom Rini
2 siblings, 0 replies; 35+ messages in thread
From: Heiko Schocher @ 2017-07-06 9:40 UTC (permalink / raw)
To: u-boot
Hello Christophe,
Am 06.07.2017 um 10:33 schrieb Christophe Leroy:
> immap.c used to be common to several CPUs. It is now
> only linked to the 8xx, so this patch moves it into
> arch/powerpc/cpu/mpc8xx/
>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
> arch/powerpc/Kconfig | 2 --
> arch/powerpc/cpu/mpc8xx/Kconfig | 9 +++++++++
> arch/powerpc/cpu/mpc8xx/Makefile | 1 +
> arch/powerpc/{lib => cpu/mpc8xx}/immap.c | 3 ---
> arch/powerpc/lib/Kconfig | 7 -------
> arch/powerpc/lib/Makefile | 1 -
> 6 files changed, 10 insertions(+), 13 deletions(-)
> rename arch/powerpc/{lib => cpu/mpc8xx}/immap.c (99%)
> delete mode 100644 arch/powerpc/lib/Kconfig
Reviewed-by: Heiko Schocher <hs@denx.de>
bye,
Heiko
>
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index a7558d59b2..e9002a76ab 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -34,8 +34,6 @@ config 8xx
>
> endchoice
>
> -source "arch/powerpc/lib/Kconfig"
> -
> source "arch/powerpc/cpu/mpc83xx/Kconfig"
> source "arch/powerpc/cpu/mpc85xx/Kconfig"
> source "arch/powerpc/cpu/mpc86xx/Kconfig"
> diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
> index a425cba8aa..cb15dc5ebc 100644
> --- a/arch/powerpc/cpu/mpc8xx/Kconfig
> +++ b/arch/powerpc/cpu/mpc8xx/Kconfig
> @@ -10,4 +10,13 @@ choice
>
> endchoice
>
> +comment "Specific commands"
> +
> +config CMD_IMMAP
> + bool "Enable various commands to dump IMMR information"
> + help
> + This enables various commands such as:
> +
> + siuinfo - print System Interface Unit (SIU) registers
> + memcinfo - print Memory Controller registers
> endmenu
> diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile
> index 5dd801d76e..eae02da636 100644
> --- a/arch/powerpc/cpu/mpc8xx/Makefile
> +++ b/arch/powerpc/cpu/mpc8xx/Makefile
> @@ -11,6 +11,7 @@ obj-y += cpu.o
> obj-y += cpu_init.o
> obj-y += fec.o
> obj-$(CONFIG_OF_LIBFDT) += fdt.o
> +obj-$(CONFIG_CMD_IMMAP) += immap.o
> obj-y += interrupts.o
> obj-y += serial.o
> obj-y += speed.o
> diff --git a/arch/powerpc/lib/immap.c b/arch/powerpc/cpu/mpc8xx/immap.c
> similarity index 99%
> rename from arch/powerpc/lib/immap.c
> rename to arch/powerpc/cpu/mpc8xx/immap.c
> index 1beed1fa40..5ff6aa5e3b 100644
> --- a/arch/powerpc/lib/immap.c
> +++ b/arch/powerpc/cpu/mpc8xx/immap.c
> @@ -12,8 +12,6 @@
> #include <common.h>
> #include <command.h>
>
> -#if defined(CONFIG_8xx)
> -
> #include <asm/8xx_immap.h>
> #include <commproc.h>
> #include <asm/iopin_8xx.h>
> @@ -394,4 +392,3 @@ U_BOOT_CMD(
> "print Baud Rate Generator (BRG) registers",
> ""
> );
> -#endif
> diff --git a/arch/powerpc/lib/Kconfig b/arch/powerpc/lib/Kconfig
> deleted file mode 100644
> index 7c8ea971c3..0000000000
> --- a/arch/powerpc/lib/Kconfig
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -config CMD_IMMAP
> - bool "Enable various commands to dump IMMR information"
> - help
> - This enables various commands such as:
> -
> - siuinfo - print System Interface Unit (SIU) registers
> - memcinfo - print Memory Controller registers
> diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
> index 4aa41836a2..9a3043abf8 100644
> --- a/arch/powerpc/lib/Makefile
> +++ b/arch/powerpc/lib/Makefile
> @@ -32,7 +32,6 @@ obj-$(CONFIG_BAT_RW) += bat_rw.o
> obj-$(CONFIG_CMD_BOOTM) += bootm.o
> obj-y += cache.o
> obj-y += extable.o
> -obj-$(CONFIG_CMD_IMMAP) += immap.o
> obj-y += interrupts.o
> obj-$(CONFIG_CMD_KGDB) += kgdb.o
> obj-y += stack.o
>
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 35+ messages in thread* [U-Boot] [U-Boot, v2, 01/10] powerpc, 8xx: move immap.c in arch/powerpc/cpu/mpc8xx/
2017-07-06 8:33 ` [U-Boot] [PATCH v2 01/10] powerpc, 8xx: move immap.c in arch/powerpc/cpu/mpc8xx/ Christophe Leroy
2017-07-06 8:41 ` Christophe LEROY
2017-07-06 9:40 ` Heiko Schocher
@ 2017-07-09 0:24 ` Tom Rini
2 siblings, 0 replies; 35+ messages in thread
From: Tom Rini @ 2017-07-09 0:24 UTC (permalink / raw)
To: u-boot
On Thu, Jul 06, 2017 at 10:33:09AM +0200, Christophe Leroy wrote:
> immap.c used to be common to several CPUs. It is now
> only linked to the 8xx, so this patch moves it into
> arch/powerpc/cpu/mpc8xx/
>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> Reviewed-by: Heiko Schocher <hs@denx.de>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [U-Boot] [PATCH v2 02/10] powerpc, 8xx: move specific reginfo
2017-07-06 8:33 [U-Boot] [PATCH v2 0/10] powerpc, 8xx: Modernise the 8xx Christophe Leroy
2017-07-06 8:33 ` [U-Boot] [PATCH v2 01/10] powerpc, 8xx: move immap.c in arch/powerpc/cpu/mpc8xx/ Christophe Leroy
@ 2017-07-06 8:33 ` Christophe Leroy
2017-07-06 9:40 ` Heiko Schocher
2017-07-09 0:24 ` [U-Boot] [U-Boot,v2,02/10] " Tom Rini
2017-07-06 8:33 ` [U-Boot] [PATCH v2 03/10] powerpc, 8xx: Use IO accessors to access IO memory Christophe Leroy
` (7 subsequent siblings)
9 siblings, 2 replies; 35+ messages in thread
From: Christophe Leroy @ 2017-07-06 8:33 UTC (permalink / raw)
To: u-boot
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/cpu/mpc8xx/Makefile | 1 +
{cmd => arch/powerpc/cpu/mpc8xx}/reginfo.c | 30 +----------------
cmd/reginfo.c | 54 ++----------------------------
3 files changed, 4 insertions(+), 81 deletions(-)
copy {cmd => arch/powerpc/cpu/mpc8xx}/reginfo.c (78%)
diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile
index eae02da636..b5b4bfafb9 100644
--- a/arch/powerpc/cpu/mpc8xx/Makefile
+++ b/arch/powerpc/cpu/mpc8xx/Makefile
@@ -13,6 +13,7 @@ obj-y += fec.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_CMD_IMMAP) += immap.o
obj-y += interrupts.o
+obj-$(CONFIG_CMD_REGINFO) += reginfo.o
obj-y += serial.o
obj-y += speed.o
obj-y += spi.o
diff --git a/cmd/reginfo.c b/arch/powerpc/cpu/mpc8xx/reginfo.c
similarity index 78%
copy from cmd/reginfo.c
copy to arch/powerpc/cpu/mpc8xx/reginfo.c
index 850f28cabc..b5a962431e 100644
--- a/cmd/reginfo.c
+++ b/arch/powerpc/cpu/mpc8xx/reginfo.c
@@ -6,19 +6,10 @@
*/
#include <common.h>
-#include <command.h>
-#if defined(CONFIG_8xx)
#include <mpc8xx.h>
-#elif defined(CONFIG_MPC86xx)
-extern void mpc86xx_reginfo(void);
-#elif defined(CONFIG_MPC85xx)
-extern void mpc85xx_reginfo(void);
-#endif
-static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
+void mpc8xx_reginfo(void)
{
-#if defined(CONFIG_8xx)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
@@ -70,23 +61,4 @@ static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
/*
* May be some CPM info here?
*/
-
-#elif defined(CONFIG_MPC86xx)
- mpc86xx_reginfo();
-
-#elif defined(CONFIG_MPC85xx)
- mpc85xx_reginfo();
-#endif
-
- return 0;
}
-
- /**************************************************/
-
-#if defined(CONFIG_CMD_REGINFO)
-U_BOOT_CMD(
- reginfo, 2, 1, do_reginfo,
- "print register information",
- ""
-);
-#endif
diff --git a/cmd/reginfo.c b/cmd/reginfo.c
index 850f28cabc..b364cc899a 100644
--- a/cmd/reginfo.c
+++ b/cmd/reginfo.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <command.h>
#if defined(CONFIG_8xx)
-#include <mpc8xx.h>
+void mpc8xx_reginfo(void);
#elif defined(CONFIG_MPC86xx)
extern void mpc86xx_reginfo(void);
#elif defined(CONFIG_MPC85xx)
@@ -19,57 +19,7 @@ static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
#if defined(CONFIG_8xx)
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
- volatile sit8xx_t *timers = &immap->im_sit;
-
- /* Hopefully more PowerPC knowledgable people will add code to display
- * other useful registers
- */
-
- printf ("\nSystem Configuration registers\n"
-
- "\tIMMR\t0x%08X\n", get_immr(0));
-
- printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
- printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
-
- printf("\tSWT\t0x%08X", sysconf->sc_swt);
- printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
-
- printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
- sysconf->sc_sipend, sysconf->sc_simask);
- printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
- sysconf->sc_siel, sysconf->sc_sivec);
- printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
- sysconf->sc_tesr, sysconf->sc_sdcr);
-
- printf ("Memory Controller Registers\n"
-
- "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
- printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
- printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
- printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
- printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
- printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
- printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
- printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
- printf ("\n"
- "\tmamr\t0x%08X\tmbmr\t0x%08X \n",
- memctl->memc_mamr, memctl->memc_mbmr );
- printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
- memctl->memc_mstat, memctl->memc_mptpr );
- printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
-
- printf ("\nSystem Integration Timers\n"
- "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
- timers->sit_tbscr, timers->sit_rtcsc);
- printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
-
- /*
- * May be some CPM info here?
- */
+ mpc8xx_reginfo();
#elif defined(CONFIG_MPC86xx)
mpc86xx_reginfo();
--
2.12.0
^ permalink raw reply related [flat|nested] 35+ messages in thread* [U-Boot] [PATCH v2 02/10] powerpc, 8xx: move specific reginfo
2017-07-06 8:33 ` [U-Boot] [PATCH v2 02/10] powerpc, 8xx: move specific reginfo Christophe Leroy
@ 2017-07-06 9:40 ` Heiko Schocher
2017-07-09 0:24 ` [U-Boot] [U-Boot,v2,02/10] " Tom Rini
1 sibling, 0 replies; 35+ messages in thread
From: Heiko Schocher @ 2017-07-06 9:40 UTC (permalink / raw)
To: u-boot
Hello Christophe,
Am 06.07.2017 um 10:33 schrieb Christophe Leroy:
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
> arch/powerpc/cpu/mpc8xx/Makefile | 1 +
> {cmd => arch/powerpc/cpu/mpc8xx}/reginfo.c | 30 +----------------
> cmd/reginfo.c | 54 ++----------------------------
> 3 files changed, 4 insertions(+), 81 deletions(-)
> copy {cmd => arch/powerpc/cpu/mpc8xx}/reginfo.c (78%)
Reviewed-by: Heiko Schocher <hs@denx.de>
bye,
Heiko
>
> diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile
> index eae02da636..b5b4bfafb9 100644
> --- a/arch/powerpc/cpu/mpc8xx/Makefile
> +++ b/arch/powerpc/cpu/mpc8xx/Makefile
> @@ -13,6 +13,7 @@ obj-y += fec.o
> obj-$(CONFIG_OF_LIBFDT) += fdt.o
> obj-$(CONFIG_CMD_IMMAP) += immap.o
> obj-y += interrupts.o
> +obj-$(CONFIG_CMD_REGINFO) += reginfo.o
> obj-y += serial.o
> obj-y += speed.o
> obj-y += spi.o
> diff --git a/cmd/reginfo.c b/arch/powerpc/cpu/mpc8xx/reginfo.c
> similarity index 78%
> copy from cmd/reginfo.c
> copy to arch/powerpc/cpu/mpc8xx/reginfo.c
> index 850f28cabc..b5a962431e 100644
> --- a/cmd/reginfo.c
> +++ b/arch/powerpc/cpu/mpc8xx/reginfo.c
> @@ -6,19 +6,10 @@
> */
>
> #include <common.h>
> -#include <command.h>
> -#if defined(CONFIG_8xx)
> #include <mpc8xx.h>
> -#elif defined(CONFIG_MPC86xx)
> -extern void mpc86xx_reginfo(void);
> -#elif defined(CONFIG_MPC85xx)
> -extern void mpc85xx_reginfo(void);
> -#endif
>
> -static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
> - char * const argv[])
> +void mpc8xx_reginfo(void)
> {
> -#if defined(CONFIG_8xx)
> volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
> volatile memctl8xx_t *memctl = &immap->im_memctl;
> volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
> @@ -70,23 +61,4 @@ static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
> /*
> * May be some CPM info here?
> */
> -
> -#elif defined(CONFIG_MPC86xx)
> - mpc86xx_reginfo();
> -
> -#elif defined(CONFIG_MPC85xx)
> - mpc85xx_reginfo();
> -#endif
> -
> - return 0;
> }
> -
> - /**************************************************/
> -
> -#if defined(CONFIG_CMD_REGINFO)
> -U_BOOT_CMD(
> - reginfo, 2, 1, do_reginfo,
> - "print register information",
> - ""
> -);
> -#endif
> diff --git a/cmd/reginfo.c b/cmd/reginfo.c
> index 850f28cabc..b364cc899a 100644
> --- a/cmd/reginfo.c
> +++ b/cmd/reginfo.c
> @@ -8,7 +8,7 @@
> #include <common.h>
> #include <command.h>
> #if defined(CONFIG_8xx)
> -#include <mpc8xx.h>
> +void mpc8xx_reginfo(void);
> #elif defined(CONFIG_MPC86xx)
> extern void mpc86xx_reginfo(void);
> #elif defined(CONFIG_MPC85xx)
> @@ -19,57 +19,7 @@ static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
> char * const argv[])
> {
> #if defined(CONFIG_8xx)
> - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
> - volatile memctl8xx_t *memctl = &immap->im_memctl;
> - volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
> - volatile sit8xx_t *timers = &immap->im_sit;
> -
> - /* Hopefully more PowerPC knowledgable people will add code to display
> - * other useful registers
> - */
> -
> - printf ("\nSystem Configuration registers\n"
> -
> - "\tIMMR\t0x%08X\n", get_immr(0));
> -
> - printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
> - printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
> -
> - printf("\tSWT\t0x%08X", sysconf->sc_swt);
> - printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
> -
> - printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
> - sysconf->sc_sipend, sysconf->sc_simask);
> - printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
> - sysconf->sc_siel, sysconf->sc_sivec);
> - printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
> - sysconf->sc_tesr, sysconf->sc_sdcr);
> -
> - printf ("Memory Controller Registers\n"
> -
> - "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
> - printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
> - printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
> - printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
> - printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
> - printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
> - printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
> - printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
> - printf ("\n"
> - "\tmamr\t0x%08X\tmbmr\t0x%08X \n",
> - memctl->memc_mamr, memctl->memc_mbmr );
> - printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
> - memctl->memc_mstat, memctl->memc_mptpr );
> - printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
> -
> - printf ("\nSystem Integration Timers\n"
> - "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
> - timers->sit_tbscr, timers->sit_rtcsc);
> - printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
> -
> - /*
> - * May be some CPM info here?
> - */
> + mpc8xx_reginfo();
>
> #elif defined(CONFIG_MPC86xx)
> mpc86xx_reginfo();
>
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 35+ messages in thread* [U-Boot] [U-Boot,v2,02/10] powerpc, 8xx: move specific reginfo
2017-07-06 8:33 ` [U-Boot] [PATCH v2 02/10] powerpc, 8xx: move specific reginfo Christophe Leroy
2017-07-06 9:40 ` Heiko Schocher
@ 2017-07-09 0:24 ` Tom Rini
1 sibling, 0 replies; 35+ messages in thread
From: Tom Rini @ 2017-07-09 0:24 UTC (permalink / raw)
To: u-boot
On Thu, Jul 06, 2017 at 10:33:11AM +0200, Christophe Leroy wrote:
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> Reviewed-by: Heiko Schocher <hs@denx.de>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [U-Boot] [PATCH v2 03/10] powerpc, 8xx: Use IO accessors to access IO memory
2017-07-06 8:33 [U-Boot] [PATCH v2 0/10] powerpc, 8xx: Modernise the 8xx Christophe Leroy
2017-07-06 8:33 ` [U-Boot] [PATCH v2 01/10] powerpc, 8xx: move immap.c in arch/powerpc/cpu/mpc8xx/ Christophe Leroy
2017-07-06 8:33 ` [U-Boot] [PATCH v2 02/10] powerpc, 8xx: move specific reginfo Christophe Leroy
@ 2017-07-06 8:33 ` Christophe Leroy
2017-07-06 9:41 ` Heiko Schocher
2017-07-09 0:24 ` [U-Boot] [U-Boot, v2, " Tom Rini
2017-07-06 8:33 ` [U-Boot] [PATCH v2 04/10] powerpc, 8xx: Implement GLL2 ERRATA Christophe Leroy
` (6 subsequent siblings)
9 siblings, 2 replies; 35+ messages in thread
From: Christophe Leroy @ 2017-07-06 8:33 UTC (permalink / raw)
To: u-boot
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/cpu/mpc8xx/cpu.c | 58 +++---
arch/powerpc/cpu/mpc8xx/cpu_init.c | 98 ++++------
arch/powerpc/cpu/mpc8xx/fec.c | 262 +++++++++++++------------
arch/powerpc/cpu/mpc8xx/immap.c | 120 ++++++------
arch/powerpc/cpu/mpc8xx/interrupts.c | 65 +++---
arch/powerpc/cpu/mpc8xx/reginfo.c | 70 ++++---
arch/powerpc/cpu/mpc8xx/serial.c | 182 ++++++++---------
arch/powerpc/cpu/mpc8xx/speed.c | 5 +-
arch/powerpc/cpu/mpc8xx/spi.c | 166 +++++++---------
arch/powerpc/include/asm/iopin_8xx.h | 369 +++++++++++++++++++++++------------
arch/powerpc/lib/time.c | 7 +-
include/watchdog.h | 2 +-
12 files changed, 739 insertions(+), 665 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c
index 80b9596813..28cc182957 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu.c
@@ -41,7 +41,7 @@ static int check_CPU (long clock, uint pvr, uint immr)
{
char *id_str =
NULL;
- volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
+ immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
uint k, m;
char buf[32];
char pre = 'X';
@@ -54,7 +54,7 @@ static int check_CPU (long clock, uint pvr, uint immr)
return -1;
k = (immr << 16) |
- immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
+ in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
m = 0;
suf = "";
@@ -95,10 +95,9 @@ static int check_CPU (long clock, uint pvr, uint immr)
/* do we have a FEC (860T/P or 852/859/866/885)? */
- immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
- if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
+ out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678);
+ if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
printf (" FEC present");
- }
if (!m) {
puts (cpu_warning);
@@ -127,11 +126,11 @@ int checkcpu (void)
int checkicache (void)
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ memctl8xx_t __iomem *memctl = &immap->im_memctl;
u32 cacheon = rd_ic_cst () & IDC_ENABLED;
-
- u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
+ /* probe in flash memoryarea */
+ u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
u32 m;
u32 lines = -1;
@@ -168,11 +167,11 @@ int checkicache (void)
int checkdcache (void)
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ memctl8xx_t __iomem *memctl = &immap->im_memctl;
u32 cacheon = rd_dc_cst () & IDC_ENABLED;
-
- u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
+ /* probe in flash memoryarea */
+ u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
u32 m;
u32 lines = -1;
@@ -204,12 +203,12 @@ void upmconfig (uint upm, uint * table, uint size)
{
uint i;
uint addr = 0;
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ memctl8xx_t __iomem *memctl = &immap->im_memctl;
for (i = 0; i < size; i++) {
- memctl->memc_mdr = table[i]; /* (16-15) */
- memctl->memc_mcr = addr | upm; /* (16-16) */
+ out_be32(&memctl->memc_mdr, table[i]); /* (16-15) */
+ out_be32(&memctl->memc_mcr, addr | upm); /* (16-16) */
addr++;
}
}
@@ -220,9 +219,10 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong msr, addr;
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
- immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */
+ /* Checkstop Reset enable */
+ setbits_be32(&immap->im_clkrst.car_plprcr, PLPRCR_CSR);
/* Interrupts and MMU off */
__asm__ volatile ("mtspr 81, 0");
@@ -260,14 +260,13 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
unsigned long get_tbclk (void)
{
uint immr = get_immr (0); /* Return full IMMR contents */
- volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
+ immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
ulong oscclk, factor, pll;
- if (immap->im_clkrst.car_sccr & SCCR_TBS) {
+ if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
return (gd->cpu_clk / 16);
- }
- pll = immap->im_clkrst.car_plprcr;
+ pll = in_be32(&immap->im_clkrst.car_plprcr);
#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
@@ -287,9 +286,10 @@ unsigned long get_tbclk (void)
oscclk = gd->cpu_clk / factor;
- if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
+ if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
+ factor > 2)
return (oscclk / 4);
- }
+
return (oscclk / 16);
}
@@ -300,7 +300,7 @@ void watchdog_reset (void)
{
int re_enable = disable_interrupts ();
- reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
+ reset_8xx_watchdog((immap_t __iomem *)CONFIG_SYS_IMMR);
if (re_enable)
enable_interrupts ();
}
@@ -308,13 +308,13 @@ void watchdog_reset (void)
#if defined(CONFIG_WATCHDOG)
-void reset_8xx_watchdog (volatile immap_t * immr)
+void reset_8xx_watchdog(immap_t __iomem *immr)
{
/*
* All other boards use the MPC8xx Internal Watchdog
*/
- immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
- immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
+ out_be16(&immr->im_siu_conf.sc_swsr, 0x556c); /* write magic1 */
+ out_be16(&immr->im_siu_conf.sc_swsr, 0xaa39); /* write magic2 */
}
#endif /* CONFIG_WATCHDOG */
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index 0f935aff9e..cf1280983a 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -10,6 +10,7 @@
#include <mpc8xx.h>
#include <commproc.h>
+#include <asm/io.h>
/*
* Breath some life into the CPU...
@@ -18,46 +19,41 @@
* initialize a bunch of registers,
* initialize the UPM's
*/
-void cpu_init_f (volatile immap_t * immr)
+void cpu_init_f(immap_t __iomem *immr)
{
- volatile memctl8xx_t *memctl = &immr->im_memctl;
-# ifdef CONFIG_SYS_PLPRCR
- ulong mfmask;
-# endif
+ memctl8xx_t __iomem *memctl = &immr->im_memctl;
ulong reg;
/* SYPCR - contains watchdog control (11-9) */
- immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR;
+ out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR);
#if defined(CONFIG_WATCHDOG)
reset_8xx_watchdog (immr);
#endif /* CONFIG_WATCHDOG */
/* SIUMCR - contains debug pin configuration (11-6) */
- immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR;
+ setbits_be32(&immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR);
/* initialize timebase status and control register (11-26) */
/* unlock TBSCRK */
- immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
- immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR;
+ out_be32(&immr->im_sitk.sitk_tbscrk, KAPWR_KEY);
+ out_be16(&immr->im_sit.sit_tbscr, CONFIG_SYS_TBSCR);
/* initialize the PIT (11-31) */
- immr->im_sitk.sitk_piscrk = KAPWR_KEY;
- immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
+ out_be32(&immr->im_sitk.sitk_piscrk, KAPWR_KEY);
+ out_be16(&immr->im_sit.sit_piscr, CONFIG_SYS_PISCR);
/* System integration timers. Don't change EBDF! (15-27) */
- immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
- reg = immr->im_clkrst.car_sccr;
- reg &= SCCR_MASK;
- reg |= CONFIG_SYS_SCCR;
- immr->im_clkrst.car_sccr = reg;
+ out_be32(&immr->im_clkrstk.cark_sccrk, KAPWR_KEY);
+ clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK,
+ CONFIG_SYS_SCCR);
/* PLL (CPU clock) settings (15-30) */
- immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
+ out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
/* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
* set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
@@ -67,27 +63,19 @@ void cpu_init_f (volatile immap_t * immr)
* For newer (starting MPC866) chips PLPRCR layout is different.
*/
#ifdef CONFIG_SYS_PLPRCR
- mfmask = PLPRCR_MFACT_MSK;
-
- if ((CONFIG_SYS_PLPRCR & mfmask) != 0)
- reg = CONFIG_SYS_PLPRCR; /* reset control bits */
- else {
- reg = immr->im_clkrst.car_plprcr;
- reg &= mfmask; /* isolate MF-related fields */
- reg |= CONFIG_SYS_PLPRCR; /* reset control bits */
- }
- immr->im_clkrst.car_plprcr = reg;
+ if ((CONFIG_SYS_PLPRCR & PLPRCR_MFACT_MSK) != 0) /* reset control bits*/
+ out_be32(&immr->im_clkrst.car_plprcr, CONFIG_SYS_PLPRCR);
+ else /* isolate MF-related fields and reset control bits */
+ clrsetbits_be32(&immr->im_clkrst.car_plprcr, ~PLPRCR_MFACT_MSK,
+ CONFIG_SYS_PLPRCR);
#endif
/*
* Memory Controller:
*/
- /* perform BR0 reset that MPC850 Rev. A can't guarantee */
- reg = memctl->memc_br0;
- reg &= BR_PS_MSK; /* Clear everything except Port Size bits */
- reg |= BR_V; /* then add just the "Bank Valid" bit */
- memctl->memc_br0 = reg;
+ /* Clear everything except Port Size bits & add the "Bank Valid" bit */
+ clrsetbits_be32(&memctl->memc_br0, ~BR_PS_MSK, BR_V);
/* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
* preliminary addresses - these have to be modified later
@@ -114,61 +102,61 @@ void cpu_init_f (volatile immap_t * immr)
*/
#if defined(CONFIG_SYS_OR0_REMAP)
- memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
+ out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_REMAP);
#endif
#if defined(CONFIG_SYS_OR1_REMAP)
- memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
+ out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_REMAP);
#endif
#if defined(CONFIG_SYS_OR5_REMAP)
- memctl->memc_or5 = CONFIG_SYS_OR5_REMAP;
+ out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_REMAP);
#endif
/* now restrict to preliminary range */
- memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
- memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
+ out_be32(&memctl->memc_br0, CONFIG_SYS_BR0_PRELIM);
+ out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_PRELIM);
#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+ out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
+ out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
#endif
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
- memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
- memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
+ out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_PRELIM);
+ out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_PRELIM);
#endif
#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
- memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
- memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
+ out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_PRELIM);
+ out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_PRELIM);
#endif
#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
- memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
- memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
+ out_be32(&memctl->memc_or4, CONFIG_SYS_OR4_PRELIM);
+ out_be32(&memctl->memc_br4, CONFIG_SYS_BR4_PRELIM);
#endif
#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
- memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
- memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
+ out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_PRELIM);
+ out_be32(&memctl->memc_br5, CONFIG_SYS_BR5_PRELIM);
#endif
#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
- memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM;
- memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM;
+ out_be32(&memctl->memc_or6, CONFIG_SYS_OR6_PRELIM);
+ out_be32(&memctl->memc_br6, CONFIG_SYS_BR6_PRELIM);
#endif
#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
- memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM;
- memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
+ out_be32(&memctl->memc_or7, CONFIG_SYS_OR7_PRELIM);
+ out_be32(&memctl->memc_br7, CONFIG_SYS_BR7_PRELIM);
#endif
/*
* Reset CPM
*/
- immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG;
- do { /* Spin until command processed */
- __asm__ ("eieio");
- } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
+ out_be16(&immr->im_cpm.cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
+ /* Spin until command processed */
+ while (in_be16(&immr->im_cpm.cp_cpcr) & CPM_CR_FLG)
+ ;
}
/*
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index 7aa526d7ec..eaaea2d4e8 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -10,6 +10,7 @@
#include <commproc.h>
#include <malloc.h>
#include <net.h>
+#include <asm/io.h>
#include <phy.h>
@@ -115,12 +116,12 @@ static uint txIdx; /* index of the current TX buffer */
* Provide for Double Buffering
*/
-typedef volatile struct CommonBufferDescriptor {
+struct common_buf_desc {
cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
-} RTXBD;
+};
-static RTXBD *rtx = NULL;
+static struct common_buf_desc __iomem *rtx;
static int fec_send(struct eth_device *dev, void *packet, int length);
static int fec_recv(struct eth_device* dev);
@@ -189,13 +190,15 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
{
int j, rc;
struct ether_fcc_info_s *efis = dev->priv;
- volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
+ fec_t __iomem *fecp =
+ (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
/* section 16.9.23.3
* Wait for ready
*/
j = 0;
- while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
+ while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
+ (j < TOUT_LOOP)) {
udelay(1);
j++;
}
@@ -203,16 +206,18 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
printf("TX not ready\n");
}
- rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
- rtx->txbd[txIdx].cbd_datlen = length;
- rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
- __asm__ ("eieio");
+ out_be32(&rtx->txbd[txIdx].cbd_bufaddr, (uint)packet);
+ out_be16(&rtx->txbd[txIdx].cbd_datlen, length);
+ setbits_be16(&rtx->txbd[txIdx].cbd_sc,
+ BD_ENET_TX_READY | BD_ENET_TX_LAST);
/* Activate transmit Buffer Descriptor polling */
- fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
+ /* Descriptor polling active */
+ out_be32(&fecp->fec_x_des_active, 0x01000000);
j = 0;
- while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
+ while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
+ (j < TOUT_LOOP)) {
udelay(1);
j++;
}
@@ -220,7 +225,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
printf("TX timeout\n");
}
/* return only status bits */;
- rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
+ rc = in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_STATS;
txIdx = (txIdx + 1) % TX_BUF_CNT;
@@ -230,21 +235,20 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
static int fec_recv (struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
- volatile fec_t *fecp =
- (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
+ fec_t __iomem *fecp =
+ (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
int length;
for (;;) {
/* section 16.9.23.2 */
- if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
+ if (in_be16(&rtx->rxbd[rxIdx].cbd_sc) & BD_ENET_RX_EMPTY) {
length = -1;
break; /* nothing received - leave for() loop */
}
- length = rtx->rxbd[rxIdx].cbd_datlen;
+ length = in_be16(&rtx->rxbd[rxIdx].cbd_datlen);
- if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
- } else {
+ if (!(in_be16(&rtx->rxbd[rxIdx].cbd_sc) & 0x003f)) {
uchar *rx = net_rx_packets[rxIdx];
length -= 4;
@@ -263,22 +267,21 @@ static int fec_recv (struct eth_device *dev)
}
/* Give the buffer back to the FEC. */
- rtx->rxbd[rxIdx].cbd_datlen = 0;
+ out_be16(&rtx->rxbd[rxIdx].cbd_datlen, 0);
/* wrap around buffer index when necessary */
if ((rxIdx + 1) >= PKTBUFSRX) {
- rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
- (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
+ out_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc,
+ BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
rxIdx = 0;
} else {
- rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
+ out_be16(&rtx->rxbd[rxIdx].cbd_sc, BD_ENET_RX_EMPTY);
rxIdx++;
}
- __asm__ ("eieio");
-
/* Try to fill Buffer Descriptors */
- fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
+ /* Descriptor polling active */
+ out_be32(&fecp->fec_r_des_active, 0x01000000);
}
return length;
@@ -313,11 +316,12 @@ static inline void fec_10Mbps(struct eth_device *dev)
struct ether_fcc_info_s *efis = dev->priv;
int fecidx = efis->ether_index;
uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
if ((unsigned int)fecidx >= 2)
hang();
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr |= mask;
+ setbits_be32(&immr->im_cpm.cp_cptr, mask);
}
static inline void fec_100Mbps(struct eth_device *dev)
@@ -325,11 +329,12 @@ static inline void fec_100Mbps(struct eth_device *dev)
struct ether_fcc_info_s *efis = dev->priv;
int fecidx = efis->ether_index;
uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
if ((unsigned int)fecidx >= 2)
hang();
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr &= ~mask;
+ clrbits_be32(&immr->im_cpm.cp_cptr, mask);
}
#endif
@@ -337,25 +342,27 @@ static inline void fec_100Mbps(struct eth_device *dev)
static inline void fec_full_duplex(struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
- volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
+ fec_t __iomem *fecp =
+ (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
- fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT;
- fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */
+ clrbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
+ setbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */
}
static inline void fec_half_duplex(struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
- volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
+ fec_t __iomem *fecp =
+ (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
- fecp->fec_r_cntrl |= FEC_RCNTRL_DRT;
- fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */
+ setbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
+ clrbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */
}
static void fec_pin_init(int fecidx)
{
bd_t *bd = gd->bd;
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
/*
* Set MII speed to 2.5 MHz or slightly below.
@@ -369,12 +376,13 @@ static void fec_pin_init(int fecidx)
*
* All MII configuration is done via FEC1 registers:
*/
- immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
+ out_be32(&immr->im_cpm.cp_fec1.fec_mii_speed,
+ ((bd->bi_intfreq + 4999999) / 5000000) << 1);
#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
/* use MDC for MII */
- immr->im_ioport.iop_pdpar |= 0x0080;
- immr->im_ioport.iop_pddir &= ~0x0080;
+ setbits_be16(&immr->im_ioport.iop_pdpar, 0x0080);
+ clrbits_be16(&immr->im_ioport.iop_pddir, 0x0080);
#endif
if (fecidx == 0) {
@@ -384,37 +392,37 @@ static void fec_pin_init(int fecidx)
#if !defined(CONFIG_RMII)
- immr->im_ioport.iop_papar |= 0xf830;
- immr->im_ioport.iop_padir |= 0x0830;
- immr->im_ioport.iop_padir &= ~0xf000;
+ setbits_be16(&immr->im_ioport.iop_papar, 0xf830);
+ setbits_be16(&immr->im_ioport.iop_padir, 0x0830);
+ clrbits_be16(&immr->im_ioport.iop_padir, 0xf000);
- immr->im_cpm.cp_pbpar |= 0x00001001;
- immr->im_cpm.cp_pbdir &= ~0x00001001;
+ setbits_be32(&immr->im_cpm.cp_pbpar, 0x00001001);
+ clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00001001);
- immr->im_ioport.iop_pcpar |= 0x000c;
- immr->im_ioport.iop_pcdir &= ~0x000c;
+ setbits_be16(&immr->im_ioport.iop_pcpar, 0x000c);
+ clrbits_be16(&immr->im_ioport.iop_pcdir, 0x000c);
- immr->im_cpm.cp_pepar |= 0x00000003;
- immr->im_cpm.cp_pedir |= 0x00000003;
- immr->im_cpm.cp_peso &= ~0x00000003;
+ setbits_be32(&immr->im_cpm.cp_pepar, 0x00000003);
+ setbits_be32(&immr->im_cpm.cp_pedir, 0x00000003);
+ clrbits_be32(&immr->im_cpm.cp_peso, 0x00000003);
- immr->im_cpm.cp_cptr &= ~0x00000100;
+ clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
#else
#if !defined(CONFIG_FEC1_PHY_NORXERR)
- immr->im_ioport.iop_papar |= 0x1000;
- immr->im_ioport.iop_padir &= ~0x1000;
+ setbits_be16(&immr->im_ioport.iop_papar, 0x1000);
+ clrbits_be16(&immr->im_ioport.iop_padir, 0x1000);
#endif
- immr->im_ioport.iop_papar |= 0xe810;
- immr->im_ioport.iop_padir |= 0x0810;
- immr->im_ioport.iop_padir &= ~0xe000;
+ setbits_be16(&immr->im_ioport.iop_papar, 0xe810);
+ setbits_be16(&immr->im_ioport.iop_padir, 0x0810);
+ clrbits_be16(&immr->im_ioport.iop_padir, 0xe000);
- immr->im_cpm.cp_pbpar |= 0x00000001;
- immr->im_cpm.cp_pbdir &= ~0x00000001;
+ setbits_be32(&immr->im_cpm.cp_pbpar, 0x00000001);
+ clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00000001);
- immr->im_cpm.cp_cptr |= 0x00000100;
- immr->im_cpm.cp_cptr &= ~0x00000050;
+ setbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
+ clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000050);
#endif /* !CONFIG_RMII */
@@ -422,9 +430,8 @@ static void fec_pin_init(int fecidx)
/*
* Configure all of port D for MII.
*/
- immr->im_ioport.iop_pdpar = 0x1fff;
-
- immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
+ out_be16(&immr->im_ioport.iop_pdpar, 0x1fff);
+ out_be16(&immr->im_ioport.iop_pddir, 0x1fff);
#endif
#endif /* CONFIG_ETHER_ON_FEC1 */
@@ -435,26 +442,26 @@ static void fec_pin_init(int fecidx)
#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
#if !defined(CONFIG_RMII)
- immr->im_cpm.cp_pepar |= 0x0003fffc;
- immr->im_cpm.cp_pedir |= 0x0003fffc;
- immr->im_cpm.cp_peso &= ~0x000087fc;
- immr->im_cpm.cp_peso |= 0x00037800;
+ setbits_be32(&immr->im_cpm.cp_pepar, 0x0003fffc);
+ setbits_be32(&immr->im_cpm.cp_pedir, 0x0003fffc);
+ clrbits_be32(&immr->im_cpm.cp_peso, 0x000087fc);
+ setbits_be32(&immr->im_cpm.cp_peso, 0x00037800);
- immr->im_cpm.cp_cptr &= ~0x00000080;
+ clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
#else
#if !defined(CONFIG_FEC2_PHY_NORXERR)
- immr->im_cpm.cp_pepar |= 0x00000010;
- immr->im_cpm.cp_pedir |= 0x00000010;
- immr->im_cpm.cp_peso &= ~0x00000010;
+ setbits_be32(&immr->im_cpm.cp_pepar, 0x00000010);
+ setbits_be32(&immr->im_cpm.cp_pedir, 0x00000010);
+ clrbits_be32(&immr->im_cpm.cp_peso, 0x00000010);
#endif
- immr->im_cpm.cp_pepar |= 0x00039620;
- immr->im_cpm.cp_pedir |= 0x00039620;
- immr->im_cpm.cp_peso |= 0x00031000;
- immr->im_cpm.cp_peso &= ~0x00008620;
+ setbits_be32(&immr->im_cpm.cp_pepar, 0x00039620);
+ setbits_be32(&immr->im_cpm.cp_pedir, 0x00039620);
+ setbits_be32(&immr->im_cpm.cp_peso, 0x00031000);
+ clrbits_be32(&immr->im_cpm.cp_peso, 0x00008620);
- immr->im_cpm.cp_cptr |= 0x00000080;
- immr->im_cpm.cp_cptr &= ~0x00000028;
+ setbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
+ clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000028);
#endif /* CONFIG_RMII */
#endif /* CONFIG_MPC885_FAMILY */
@@ -464,7 +471,7 @@ static void fec_pin_init(int fecidx)
}
}
-static int fec_reset(volatile fec_t *fecp)
+static int fec_reset(fec_t __iomem *fecp)
{
int i;
@@ -476,12 +483,11 @@ static int fec_reset(volatile fec_t *fecp)
* still in progress.
*/
- fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
- for (i = 0;
- (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
- ++i) {
+ out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
+ for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
+ (i < FEC_RESET_DELAY); ++i)
udelay (1);
- }
+
if (i == FEC_RESET_DELAY)
return -1;
@@ -491,9 +497,9 @@ static int fec_reset(volatile fec_t *fecp)
static int fec_init (struct eth_device *dev, bd_t * bd)
{
struct ether_fcc_info_s *efis = dev->priv;
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile fec_t *fecp =
- (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ fec_t __iomem *fecp =
+ (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
int i;
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
@@ -510,41 +516,42 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
/* We use strictly polling mode only
*/
- fecp->fec_imask = 0;
+ out_be32(&fecp->fec_imask, 0);
/* Clear any pending interrupt
*/
- fecp->fec_ievent = 0xffc0;
+ out_be32(&fecp->fec_ievent, 0xffc0);
/* No need to set the IVEC register */
/* Set station address
*/
#define ea dev->enetaddr
- fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
- fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
+ out_be32(&fecp->fec_addr_low, (ea[0] << 24) | (ea[1] << 16) |
+ (ea[2] << 8) | ea[3]);
+ out_be16(&fecp->fec_addr_high, (ea[4] << 8) | ea[5]);
#undef ea
#if defined(CONFIG_CMD_CDP)
/*
* Turn on multicast address hash table
*/
- fecp->fec_hash_table_high = 0xffffffff;
- fecp->fec_hash_table_low = 0xffffffff;
+ out_be32(&fecp->fec_hash_table_high, 0xffffffff);
+ out_be32(&fecp->fec_hash_table_low, 0xffffffff);
#else
/* Clear multicast address hash table
*/
- fecp->fec_hash_table_high = 0;
- fecp->fec_hash_table_low = 0;
+ out_be32(&fecp->fec_hash_table_high, 0);
+ out_be32(&fecp->fec_hash_table_low, 0);
#endif
/* Set maximum receive buffer size.
*/
- fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
+ out_be32(&fecp->fec_r_buff_size, PKT_MAXBLR_SIZE);
/* Set maximum frame length
*/
- fecp->fec_r_hash = PKT_MAXBUF_SIZE;
+ out_be32(&fecp->fec_r_hash, PKT_MAXBUF_SIZE);
/*
* Setup Buffers and Buffer Desriptors
@@ -553,18 +560,19 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
txIdx = 0;
if (!rtx)
- rtx = (RTXBD *)(immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
+ rtx = (struct common_buf_desc __iomem *)
+ (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
/*
* Setup Receiver Buffer Descriptors (13.14.24.18)
* Settings:
* Empty, Wrap
*/
for (i = 0; i < PKTBUFSRX; i++) {
- rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
- rtx->rxbd[i].cbd_datlen = 0; /* Reset */
- rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
+ out_be16(&rtx->rxbd[i].cbd_sc, BD_ENET_RX_EMPTY);
+ out_be16(&rtx->rxbd[i].cbd_datlen, 0); /* Reset */
+ out_be32(&rtx->rxbd[i].cbd_bufaddr, (uint)net_rx_packets[i]);
}
- rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
+ setbits_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc, BD_ENET_RX_WRAP);
/*
* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
@@ -572,26 +580,26 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
* Last, Tx CRC
*/
for (i = 0; i < TX_BUF_CNT; i++) {
- rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
- rtx->txbd[i].cbd_datlen = 0; /* Reset */
- rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
+ out_be16(&rtx->txbd[i].cbd_sc, BD_ENET_TX_LAST | BD_ENET_TX_TC);
+ out_be16(&rtx->txbd[i].cbd_datlen, 0); /* Reset */
+ out_be32(&rtx->txbd[i].cbd_bufaddr, (uint)txbuf);
}
- rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
+ setbits_be16(&rtx->txbd[TX_BUF_CNT - 1].cbd_sc, BD_ENET_TX_WRAP);
/* Set receive and transmit descriptor base
*/
- fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
- fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
+ out_be32(&fecp->fec_r_des_start, (__force unsigned int)rtx->rxbd);
+ out_be32(&fecp->fec_x_des_start, (__force unsigned int)rtx->txbd);
/* Enable MII mode
*/
/* Half duplex mode */
- fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
- fecp->fec_x_cntrl = 0;
+ out_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT);
+ out_be32(&fecp->fec_x_cntrl, 0);
/* Enable big endian and don't care about SDMA FC.
*/
- fecp->fec_fun_code = 0x78000000;
+ out_be32(&fecp->fec_fun_code, 0x78000000);
/*
* Setup the pin configuration of the FEC
@@ -604,7 +612,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
/*
* Now enable the transmit and receive processing
*/
- fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
+ out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
if (efis->phy_addr == -1) {
#ifdef CONFIG_SYS_DISCOVER_PHY
@@ -647,7 +655,8 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
#endif
/* And last, try to fill Rx Buffer Descriptors */
- fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
+ /* Descriptor polling active */
+ out_be32(&fecp->fec_r_des_active, 0x01000000);
efis->initialized = 1;
@@ -658,7 +667,8 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
static void fec_halt(struct eth_device* dev)
{
struct ether_fcc_info_s *efis = dev->priv;
- volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
+ fec_t __iomem *fecp =
+ (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
int i;
/* avoid halt if initialized; mii gets stuck otherwise */
@@ -673,12 +683,11 @@ static void fec_halt(struct eth_device* dev)
* still in progress.
*/
- fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
- for (i = 0;
- (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
- ++i) {
+ out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
+ for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
+ (i < FEC_RESET_DELAY); ++i)
udelay (1);
- }
+
if (i == FEC_RESET_DELAY) {
printf ("FEC_RESET_DELAY timeout\n");
return;
@@ -717,23 +726,24 @@ static uint
mii_send(uint mii_cmd)
{
uint mii_reply;
- volatile fec_t *ep;
+ fec_t __iomem *ep;
int cnt;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
- ep = &(((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_fec);
+ ep = &immr->im_cpm.cp_fec;
- ep->fec_mii_data = mii_cmd; /* command to phy */
+ out_be32(&ep->fec_mii_data, mii_cmd); /* command to phy */
/* wait for mii complete */
cnt = 0;
- while (!(ep->fec_ievent & FEC_ENET_MII)) {
+ while (!(in_be32(&ep->fec_ievent) & FEC_ENET_MII)) {
if (++cnt > 1000) {
printf("mii_send STUCK!\n");
break;
}
}
- mii_reply = ep->fec_mii_data; /* result from phy */
- ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
+ mii_reply = in_be32(&ep->fec_mii_data); /* result from phy */
+ out_be32(&ep->fec_ievent, FEC_ENET_MII); /* clear MII complete */
return (mii_reply & 0xffff); /* data read from phy */
}
#endif
@@ -782,23 +792,23 @@ static int mii_discover_phy(struct eth_device *dev)
*/
static void __mii_init(void)
{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ fec_t __iomem *fecp = &immr->im_cpm.cp_fec;
if (fec_reset(fecp) < 0)
printf ("FEC_RESET_DELAY timeout\n");
/* We use strictly polling mode only
*/
- fecp->fec_imask = 0;
+ out_be32(&fecp->fec_imask, 0);
/* Clear any pending interrupt
*/
- fecp->fec_ievent = 0xffc0;
+ out_be32(&fecp->fec_ievent, 0xffc0);
/* Now enable the transmit and receive processing
*/
- fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
+ out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
}
void mii_init (void)
diff --git a/arch/powerpc/cpu/mpc8xx/immap.c b/arch/powerpc/cpu/mpc8xx/immap.c
index 5ff6aa5e3b..63cc664e92 100644
--- a/arch/powerpc/cpu/mpc8xx/immap.c
+++ b/arch/powerpc/cpu/mpc8xx/immap.c
@@ -15,64 +15,60 @@
#include <asm/8xx_immap.h>
#include <commproc.h>
#include <asm/iopin_8xx.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int
do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- volatile sysconf8xx_t *sc = &immap->im_siu_conf;
-
- printf ("SIUMCR= %08x SYPCR = %08x\n", sc->sc_siumcr, sc->sc_sypcr);
- printf ("SWT = %08x\n", sc->sc_swt);
- printf ("SIPEND= %08x SIMASK= %08x\n", sc->sc_sipend, sc->sc_simask);
- printf ("SIEL = %08x SIVEC = %08x\n", sc->sc_siel, sc->sc_sivec);
- printf ("TESR = %08x SDCR = %08x\n", sc->sc_tesr, sc->sc_sdcr);
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ sysconf8xx_t __iomem *sc = &immap->im_siu_conf;
+
+ printf("SIUMCR= %08x SYPCR = %08x\n",
+ in_be32(&sc->sc_siumcr), in_be32(&sc->sc_sypcr));
+ printf("SWT = %08x\n", in_be32(&sc->sc_swt));
+ printf("SIPEND= %08x SIMASK= %08x\n",
+ in_be32(&sc->sc_sipend), in_be32(&sc->sc_simask));
+ printf("SIEL = %08x SIVEC = %08x\n",
+ in_be32(&sc->sc_siel), in_be32(&sc->sc_sivec));
+ printf("TESR = %08x SDCR = %08x\n",
+ in_be32(&sc->sc_tesr), in_be32(&sc->sc_sdcr));
return 0;
}
int
do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- volatile memctl8xx_t *memctl = &immap->im_memctl;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ memctl8xx_t __iomem *memctl = &immap->im_memctl;
int nbanks = 8;
- volatile uint *p = &memctl->memc_br0;
+ uint __iomem *p = &memctl->memc_br0;
int i;
- for (i = 0; i < nbanks; i++, p += 2) {
- if (i < 10) {
- printf ("BR%d = %08x OR%d = %08x\n",
- i, p[0], i, p[1]);
- } else {
- printf ("BR%d = %08x OR%d = %08x\n",
- i, p[0], i, p[1]);
- }
- }
-
- printf ("MAR = %08x", memctl->memc_mar);
- printf (" MCR = %08x\n", memctl->memc_mcr);
- printf ("MAMR = %08x MBMR = %08x",
- memctl->memc_mamr, memctl->memc_mbmr);
- printf ("\nMSTAT = %04x\n", memctl->memc_mstat);
- printf ("MPTPR = %04x MDR = %08x\n",
- memctl->memc_mptpr, memctl->memc_mdr);
+ for (i = 0; i < nbanks; i++, p += 2)
+ printf("BR%-2d = %08x OR%-2d = %08x\n",
+ i, in_be32(p), i, in_be32(p + 1));
+
+ printf("MAR = %08x", in_be32(&memctl->memc_mar));
+ printf(" MCR = %08x\n", in_be32(&memctl->memc_mcr));
+ printf("MAMR = %08x MBMR = %08x",
+ in_be32(&memctl->memc_mamr), in_be32(&memctl->memc_mbmr));
+ printf("\nMSTAT = %04x\n", in_be16(&memctl->memc_mstat));
+ printf("MPTPR = %04x MDR = %08x\n",
+ in_be16(&memctl->memc_mptpr), in_be32(&memctl->memc_mdr));
return 0;
}
int
do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- volatile car8xx_t *car = &immap->im_clkrst;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ car8xx_t __iomem *car = &immap->im_clkrst;
- printf ("SCCR = %08x\n", car->car_sccr);
- printf ("PLPRCR= %08x\n", car->car_plprcr);
- printf ("RSR = %08x\n", car->car_rsr);
+ printf("SCCR = %08x\n", in_be32(&car->car_sccr));
+ printf("PLPRCR= %08x\n", in_be32(&car->car_plprcr));
+ printf("RSR = %08x\n", in_be32(&car->car_rsr));
return 0;
}
@@ -130,11 +126,10 @@ static void binary (char *label, uint value, int nbits)
int
do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- volatile iop8xx_t *iop = &immap->im_ioport;
- volatile ushort *l, *r;
- volatile uint *R;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ iop8xx_t __iomem *iop = &immap->im_ioport;
+ ushort __iomem *l, *r;
+ uint __iomem *R;
counter = 0;
header ();
@@ -145,14 +140,14 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
l = &iop->iop_padir;
R = &immap->im_cpm.cp_pbdir;
- binary ("PA_DIR", *l++, PA_NBITS);
- binary ("PB_DIR", *R++, PB_NBITS);
- binary ("PA_PAR", *l++, PA_NBITS);
- binary ("PB_PAR", *R++, PB_NBITS);
- binary ("PA_ODR", *l++, PA_NB_ODR);
- binary ("PB_ODR", *R++, PB_NB_ODR);
- binary ("PA_DAT", *l++, PA_NBITS);
- binary ("PB_DAT", *R++, PB_NBITS);
+ binary("PA_DIR", in_be16(l++), PA_NBITS);
+ binary("PB_DIR", in_be32(R++), PB_NBITS);
+ binary("PA_PAR", in_be16(l++), PA_NBITS);
+ binary("PB_PAR", in_be32(R++), PB_NBITS);
+ binary("PA_ODR", in_be16(l++), PA_NB_ODR);
+ binary("PB_ODR", in_be32(R++), PB_NB_ODR);
+ binary("PA_DAT", in_be16(l++), PA_NBITS);
+ binary("PB_DAT", in_be32(R++), PB_NBITS);
header ();
@@ -162,16 +157,16 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
l = &iop->iop_pcdir;
r = &iop->iop_pddir;
- binary ("PC_DIR", *l++, PC_NBITS);
- binary ("PD_DIR", *r++, PD_NBITS);
- binary ("PC_PAR", *l++, PC_NBITS);
- binary ("PD_PAR", *r++, PD_NBITS);
- binary ("PC_SO ", *l++, PC_NBITS);
- binary (" ", 0, 0);
+ binary("PC_DIR", in_be16(l++), PC_NBITS);
+ binary("PD_DIR", in_be16(r++), PD_NBITS);
+ binary("PC_PAR", in_be16(l++), PC_NBITS);
+ binary("PD_PAR", in_be16(r++), PD_NBITS);
+ binary("PC_SO ", in_be16(l++), PC_NBITS);
+ binary(" ", 0, 0);
r++;
- binary ("PC_DAT", *l++, PC_NBITS);
- binary ("PD_DAT", *r++, PD_NBITS);
- binary ("PC_INT", *l++, PC_NBITS);
+ binary("PC_DAT", in_be16(l++), PC_NBITS);
+ binary("PD_DAT", in_be16(r++), PD_NBITS);
+ binary("PC_INT", in_be16(l++), PC_NBITS);
header ();
return 0;
@@ -343,14 +338,13 @@ static void prbrg (int n, uint val)
int
do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- volatile cpm8xx_t *cp = &immap->im_cpm;
- volatile uint *p = &cp->cp_brgc1;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ cpm8xx_t __iomem *cp = &immap->im_cpm;
+ uint __iomem *p = &cp->cp_brgc1;
int i = 1;
while (i <= 4)
- prbrg (i++, *p++);
+ prbrg(i++, in_be32(p++));
return 0;
}
diff --git a/arch/powerpc/cpu/mpc8xx/interrupts.c b/arch/powerpc/cpu/mpc8xx/interrupts.c
index f090ad9ecb..db6df74b5e 100644
--- a/arch/powerpc/cpu/mpc8xx/interrupts.c
+++ b/arch/powerpc/cpu/mpc8xx/interrupts.c
@@ -9,6 +9,7 @@
#include <mpc8xx.h>
#include <mpc8xx_irq.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <commproc.h>
/************************************************************************/
@@ -31,12 +32,12 @@ static void cpm_interrupt (void *regs);
int interrupt_init_cpu (unsigned *decrementer_count)
{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
*decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
/* disable all interrupts */
- immr->im_siu_conf.sc_simask = 0;
+ out_be32(&immr->im_siu_conf.sc_simask, 0);
/* Configure CPM interrupts */
cpm_interrupt_init ();
@@ -51,25 +52,24 @@ int interrupt_init_cpu (unsigned *decrementer_count)
*/
void external_interrupt (struct pt_regs *regs)
{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
int irq;
- ulong simask, newmask;
+ ulong simask;
ulong vec, v_bit;
/*
* read the SIVEC register and shift the bits down
* to get the irq number
*/
- vec = immr->im_siu_conf.sc_sivec;
+ vec = in_be32(&immr->im_siu_conf.sc_sivec);
irq = vec >> 26;
v_bit = 0x80000000UL >> irq;
/*
* Read Interrupt Mask Register and Mask Interrupts
*/
- simask = immr->im_siu_conf.sc_simask;
- newmask = simask & (~(0xFFFF0000 >> irq));
- immr->im_siu_conf.sc_simask = newmask;
+ simask = in_be32(&immr->im_siu_conf.sc_simask);
+ clrbits_be32(&immr->im_siu_conf.sc_simask, 0xFFFF0000 >> irq);
if (!(irq & 0x1)) { /* External Interrupt ? */
ulong siel;
@@ -77,13 +77,13 @@ void external_interrupt (struct pt_regs *regs)
/*
* Read Interrupt Edge/Level Register
*/
- siel = immr->im_siu_conf.sc_siel;
+ siel = in_be32(&immr->im_siu_conf.sc_siel);
if (siel & v_bit) { /* edge triggered interrupt ? */
/*
* Rewrite SIPEND Register to clear interrupt
*/
- immr->im_siu_conf.sc_sipend = v_bit;
+ out_be32(&immr->im_siu_conf.sc_sipend, v_bit);
}
}
@@ -98,7 +98,7 @@ void external_interrupt (struct pt_regs *regs)
/*
* Re-Enable old Interrupt Mask
*/
- immr->im_siu_conf.sc_simask = simask;
+ out_be32(&immr->im_siu_conf.sc_simask, simask);
}
/************************************************************************/
@@ -108,28 +108,28 @@ void external_interrupt (struct pt_regs *regs)
*/
static void cpm_interrupt (void *regs)
{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
uint vec;
/*
* Get the vector by setting the ACK bit
* and then reading the register.
*/
- immr->im_cpic.cpic_civr = 1;
- vec = immr->im_cpic.cpic_civr;
+ out_be16(&immr->im_cpic.cpic_civr, 1);
+ vec = in_be16(&immr->im_cpic.cpic_civr);
vec >>= 11;
if (cpm_vecs[vec].handler != NULL) {
(*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
} else {
- immr->im_cpic.cpic_cimr &= ~(1 << vec);
+ clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
printf ("Masking bogus CPM interrupt vector 0x%x\n", vec);
}
/*
* After servicing the interrupt,
* we have to remove the status indicator.
*/
- immr->im_cpic.cpic_cisr |= (1 << vec);
+ setbits_be32(&immr->im_cpic.cpic_cisr, 1 << vec);
}
/*
@@ -149,7 +149,7 @@ static void cpm_error_interrupt (void *dummy)
void irq_install_handler (int vec, interrupt_handler_t * handler,
void *arg)
{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
if ((vec & CPMVEC_OFFSET) != 0) {
/* CPM interrupt */
@@ -161,7 +161,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler,
}
cpm_vecs[vec].handler = handler;
cpm_vecs[vec].arg = arg;
- immr->im_cpic.cpic_cimr |= (1 << vec);
+ setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
} else {
/* SIU interrupt */
if (irq_vecs[vec].handler != NULL) {
@@ -172,23 +172,23 @@ void irq_install_handler (int vec, interrupt_handler_t * handler,
}
irq_vecs[vec].handler = handler;
irq_vecs[vec].arg = arg;
- immr->im_siu_conf.sc_simask |= 1 << (31 - vec);
+ setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
}
}
void irq_free_handler (int vec)
{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
if ((vec & CPMVEC_OFFSET) != 0) {
/* CPM interrupt */
vec &= 0xffff;
- immr->im_cpic.cpic_cimr &= ~(1 << vec);
+ clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
cpm_vecs[vec].handler = NULL;
cpm_vecs[vec].arg = NULL;
} else {
/* SIU interrupt */
- immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec));
+ clrbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
irq_vecs[vec].handler = NULL;
irq_vecs[vec].arg = NULL;
}
@@ -198,26 +198,25 @@ void irq_free_handler (int vec)
static void cpm_interrupt_init (void)
{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ uint cicr;
/*
* Initialize the CPM interrupt controller.
*/
- immr->im_cpic.cpic_cicr =
- (CICR_SCD_SCC4 |
- CICR_SCC_SCC3 |
- CICR_SCB_SCC2 |
- CICR_SCA_SCC1) | ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK;
+ cicr = CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1 |
+ ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK;
- immr->im_cpic.cpic_cimr = 0;
+ out_be32(&immr->im_cpic.cpic_cicr, cicr);
+ out_be32(&immr->im_cpic.cpic_cimr, 0);
/*
* Install the error handler.
*/
irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL);
- immr->im_cpic.cpic_cicr |= CICR_IEN;
+ setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN);
/*
* Install the cpm interrupt handler
@@ -234,10 +233,10 @@ static void cpm_interrupt_init (void)
*/
void timer_interrupt_cpu (struct pt_regs *regs)
{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
/* Reset Timer Expired and Timers Interrupt Status */
- immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
+ out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
__asm__ ("nop");
/*
Clear TEXPS (and TMIST on older chips). SPLSS (on older
@@ -253,7 +252,7 @@ void timer_interrupt_cpu (struct pt_regs *regs)
to itself. If a bit value should be preserved, read the
register, ZERO the bit and write, not OR, the result back.
*/
- immr->im_clkrst.car_plprcr = immr->im_clkrst.car_plprcr;
+ setbits_be32(&immr->im_clkrst.car_plprcr, 0);
}
/************************************************************************/
diff --git a/arch/powerpc/cpu/mpc8xx/reginfo.c b/arch/powerpc/cpu/mpc8xx/reginfo.c
index b5a962431e..48615cad01 100644
--- a/arch/powerpc/cpu/mpc8xx/reginfo.c
+++ b/arch/powerpc/cpu/mpc8xx/reginfo.c
@@ -7,56 +7,62 @@
#include <common.h>
#include <mpc8xx.h>
+#include <asm/io.h>
void mpc8xx_reginfo(void)
{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
- volatile sit8xx_t *timers = &immap->im_sit;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ memctl8xx_t __iomem *memctl = &immap->im_memctl;
+ sysconf8xx_t __iomem *sysconf = &immap->im_siu_conf;
+ sit8xx_t __iomem *timers = &immap->im_sit;
/* Hopefully more PowerPC knowledgable people will add code to display
* other useful registers
*/
printf ("\nSystem Configuration registers\n"
-
"\tIMMR\t0x%08X\n", get_immr(0));
- printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
- printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
+ printf("\tSIUMCR\t0x%08X", in_be32(&sysconf->sc_siumcr));
+ printf("\tSYPCR\t0x%08X\n", in_be32(&sysconf->sc_sypcr));
- printf("\tSWT\t0x%08X", sysconf->sc_swt);
- printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
+ printf("\tSWT\t0x%08X", in_be32(&sysconf->sc_swt));
+ printf("\tSWSR\t0x%04X\n", in_be16(&sysconf->sc_swsr));
printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
- sysconf->sc_sipend, sysconf->sc_simask);
+ in_be32(&sysconf->sc_sipend), in_be32(&sysconf->sc_simask));
printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
- sysconf->sc_siel, sysconf->sc_sivec);
+ in_be32(&sysconf->sc_siel), in_be32(&sysconf->sc_sivec));
printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
- sysconf->sc_tesr, sysconf->sc_sdcr);
-
- printf ("Memory Controller Registers\n"
+ in_be32(&sysconf->sc_tesr), in_be32(&sysconf->sc_sdcr));
- "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
- printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
- printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
- printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
- printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
- printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
- printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
- printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
- printf ("\n"
- "\tmamr\t0x%08X\tmbmr\t0x%08X \n",
- memctl->memc_mamr, memctl->memc_mbmr );
- printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
- memctl->memc_mstat, memctl->memc_mptpr );
- printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
+ printf("Memory Controller Registers\n");
+ printf("\tBR0\t0x%08X\tOR0\t0x%08X\n", in_be32(&memctl->memc_br0),
+ in_be32(&memctl->memc_or0));
+ printf("\tBR1\t0x%08X\tOR1\t0x%08X\n", in_be32(&memctl->memc_br1),
+ in_be32(&memctl->memc_or1));
+ printf("\tBR2\t0x%08X\tOR2\t0x%08X\n", in_be32(&memctl->memc_br2),
+ in_be32(&memctl->memc_or2));
+ printf("\tBR3\t0x%08X\tOR3\t0x%08X\n", in_be32(&memctl->memc_br3),
+ in_be32(&memctl->memc_or3));
+ printf("\tBR4\t0x%08X\tOR4\t0x%08X\n", in_be32(&memctl->memc_br4),
+ in_be32(&memctl->memc_or4));
+ printf("\tBR5\t0x%08X\tOR5\t0x%08X\n", in_be32(&memctl->memc_br5),
+ in_be32(&memctl->memc_or5));
+ printf("\tBR6\t0x%08X\tOR6\t0x%08X\n", in_be32(&memctl->memc_br6),
+ in_be32(&memctl->memc_or6));
+ printf("\tBR7\t0x%08X\tOR7\t0x%08X\n", in_be32(&memctl->memc_br7),
+ in_be32(&memctl->memc_or7));
+ printf("\n\tmamr\t0x%08X\tmbmr\t0x%08X\n", in_be32(&memctl->memc_mamr),
+ in_be32(&memctl->memc_mbmr));
+ printf("\tmstat\t0x%04X\tmptpr\t0x%04X\n", in_be16(&memctl->memc_mstat),
+ in_be16(&memctl->memc_mptpr));
+ printf("\tmdr\t0x%08X\n", in_be32(&memctl->memc_mdr));
- printf ("\nSystem Integration Timers\n"
- "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
- timers->sit_tbscr, timers->sit_rtcsc);
- printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
+ printf("\nSystem Integration Timers\n");
+ printf("\tTBSCR\t0x%04X\tRTCSC\t0x%04X\n",
+ in_be16(&timers->sit_tbscr), in_be16(&timers->sit_rtcsc));
+ printf("\tPISCR\t0x%04X\n", in_be16(&timers->sit_piscr));
/*
* May be some CPM info here?
diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c
index d4f1a41a1a..598ca2a7b0 100644
--- a/arch/powerpc/cpu/mpc8xx/serial.c
+++ b/arch/powerpc/cpu/mpc8xx/serial.c
@@ -20,11 +20,13 @@ DECLARE_GLOBAL_DATA_PTR;
#define SMC_INDEX 0
#define PROFF_SMC PROFF_SMC1
#define CPM_CR_CH_SMC CPM_CR_CH_SMC1
+#define IOPINS 0xc0
#elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
#define SMC_INDEX 1
#define PROFF_SMC PROFF_SMC2
#define CPM_CR_CH_SMC CPM_CR_CH_SMC2
+#define IOPINS 0xc00
#endif /* CONFIG_8xx_CONS_SMCx */
@@ -37,15 +39,15 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
#endif
-typedef volatile struct serialbuffer {
+struct serialbuffer {
cbd_t rxbd; /* Rx BD */
cbd_t txbd; /* Tx BD */
uint rxindex; /* index for next character to read */
- volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
- volatile uchar txbuf; /* tx buffers */
-} serialbuffer_t;
+ uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
+ uchar txbuf; /* tx buffers */
+};
-static void serial_setdivisor(volatile cpm8xx_t *cp)
+static void serial_setdivisor(cpm8xx_t __iomem *cp)
{
int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
@@ -58,11 +60,11 @@ static void serial_setdivisor(volatile cpm8xx_t *cp)
divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
#endif
- if(divisor<=0x1000) {
- cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
- } else {
- cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
- }
+ if (divisor <= 0x1000)
+ out_be32(&cp->cp_brgc1, ((divisor - 1) << 1) | CPM_BRG_EN);
+ else
+ out_be32(&cp->cp_brgc1, ((divisor / 16 - 1) << 1) | CPM_BRG_EN |
+ CPM_BRG_DIV16);
}
/*
@@ -72,8 +74,8 @@ static void serial_setdivisor(volatile cpm8xx_t *cp)
static void smc_setbrg (void)
{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile cpm8xx_t *cp = &(im->im_cpm);
+ immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ cpm8xx_t __iomem *cp = &(im->im_cpm);
/* Set up the baud rate generator.
* See 8xx_io/commproc.c for details.
@@ -81,117 +83,107 @@ static void smc_setbrg (void)
* Wire BRG1 to SMCx
*/
- cp->cp_simode = 0x00000000;
+ out_be32(&cp->cp_simode, 0);
serial_setdivisor(cp);
}
static int smc_init (void)
{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile smc_t *sp;
- volatile smc_uart_t *up;
- volatile cpm8xx_t *cp = &(im->im_cpm);
- uint dpaddr;
- volatile serialbuffer_t *rtx;
+ immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ smc_t __iomem *sp;
+ smc_uart_t __iomem *up;
+ cpm8xx_t __iomem *cp = &(im->im_cpm);
+ struct serialbuffer __iomem *rtx;
/* initialize pointers to SMC */
- sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
- up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
+ sp = cp->cp_smc + SMC_INDEX;
+ up = (smc_uart_t __iomem *)&cp->cp_dparam[PROFF_SMC];
/* Disable relocation */
- up->smc_rpbase = 0;
+ out_be16(&up->smc_rpbase, 0);
/* Disable transmitter/receiver. */
- sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
+ clrbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
/* Enable SDMA. */
- im->im_siu_conf.sc_sdcr = 1;
+ out_be32(&im->im_siu_conf.sc_sdcr, 1);
/* clear error conditions */
#ifdef CONFIG_SYS_SDSR
- im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
+ out_8(&im->im_sdma.sdma_sdsr, CONFIG_SYS_SDSR);
#else
- im->im_sdma.sdma_sdsr = 0x83;
+ out_8(&im->im_sdma.sdma_sdsr, 0x83);
#endif
/* clear SDMA interrupt mask */
#ifdef CONFIG_SYS_SDMR
- im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
+ out_8(&im->im_sdma.sdma_sdmr, CONFIG_SYS_SDMR);
#else
- im->im_sdma.sdma_sdmr = 0x00;
+ out_8(&im->im_sdma.sdma_sdmr, 0x00);
#endif
-#if defined(CONFIG_8xx_CONS_SMC1)
- /* Use Port B for SMC1 instead of other functions. */
- cp->cp_pbpar |= 0x000000c0;
- cp->cp_pbdir &= ~0x000000c0;
- cp->cp_pbodr &= ~0x000000c0;
-#else /* CONFIG_8xx_CONS_SMC2 */
- /* Use Port B for SMC2 instead of other functions.
- */
- cp->cp_pbpar |= 0x00000c00;
- cp->cp_pbdir &= ~0x00000c00;
- cp->cp_pbodr &= ~0x00000c00;
-#endif
+ /* Use Port B for SMCx instead of other functions. */
+ setbits_be32(&cp->cp_pbpar, IOPINS);
+ clrbits_be32(&cp->cp_pbdir, IOPINS);
+ clrbits_be16(&cp->cp_pbodr, IOPINS);
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
- dpaddr = CPM_SERIAL_BASE;
-
- rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr];
+ rtx = (struct serialbuffer __iomem *)&cp->cp_dpmem[CPM_SERIAL_BASE];
/* Allocate space for two buffer descriptors in the DP ram.
* For now, this address seems OK, but it may have to
* change with newer versions of the firmware.
* damm: allocating space after the two buffers for rx/tx data
*/
- rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
- rtx->rxbd.cbd_sc = 0;
+ out_be32(&rtx->rxbd.cbd_bufaddr, (__force uint)&rtx->rxbuf);
+ out_be16(&rtx->rxbd.cbd_sc, 0);
- rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
- rtx->txbd.cbd_sc = 0;
+ out_be32(&rtx->txbd.cbd_bufaddr, (__force uint)&rtx->txbuf);
+ out_be16(&rtx->txbd.cbd_sc, 0);
/* Set up the uart parameters in the parameter ram. */
- up->smc_rbase = dpaddr;
- up->smc_tbase = dpaddr+sizeof(cbd_t);
- up->smc_rfcr = SMC_EB;
- up->smc_tfcr = SMC_EB;
+ out_be16(&up->smc_rbase, CPM_SERIAL_BASE);
+ out_be16(&up->smc_tbase, CPM_SERIAL_BASE + sizeof(cbd_t));
+ out_8(&up->smc_rfcr, SMC_EB);
+ out_8(&up->smc_tfcr, SMC_EB);
/* Set UART mode, 8 bit, no parity, one stop.
* Enable receive and transmit.
*/
- sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
+ out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);
/* Mask all interrupts and remove anything pending.
*/
- sp->smc_smcm = 0;
- sp->smc_smce = 0xff;
+ out_8(&sp->smc_smcm, 0);
+ out_8(&sp->smc_smce, 0xff);
/* Set up the baud rate generator */
smc_setbrg ();
/* Make the first buffer the only buffer. */
- rtx->txbd.cbd_sc |= BD_SC_WRAP;
- rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
+ setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP);
+ setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
/* single/multi character receive. */
- up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
- up->smc_maxidl = CONFIG_SYS_MAXIDLE;
- rtx->rxindex = 0;
+ out_be16(&up->smc_mrblr, CONFIG_SYS_SMC_RXBUFLEN);
+ out_be16(&up->smc_maxidl, CONFIG_SYS_MAXIDLE);
+ out_be32(&rtx->rxindex, 0);
/* Initialize Tx/Rx parameters. */
- while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
- ;
+ while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) /* wait if cp is busy */
+ ;
- cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+ out_be16(&cp->cp_cpcr,
+ mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG);
- while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
- ;
+ while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) /* wait if cp is busy */
+ ;
/* Enable transmitter/receiver. */
- sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
+ setbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
return (0);
}
@@ -199,28 +191,22 @@ static int smc_init (void)
static void
smc_putc(const char c)
{
- volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile cpm8xx_t *cpmp = &(im->im_cpm);
- volatile serialbuffer_t *rtx;
+ immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ cpm8xx_t __iomem *cpmp = &(im->im_cpm);
+ struct serialbuffer __iomem *rtx;
if (c == '\n')
smc_putc ('\r');
- up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
-
- rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
+ rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
/* Wait for last character to go. */
- rtx->txbuf = c;
- rtx->txbd.cbd_datlen = 1;
- rtx->txbd.cbd_sc |= BD_SC_READY;
- __asm__("eieio");
+ out_8(&rtx->txbuf, c);
+ out_be16(&rtx->txbd.cbd_datlen, 1);
+ setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);
- while (rtx->txbd.cbd_sc & BD_SC_READY) {
+ while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
WATCHDOG_RESET ();
- __asm__("eieio");
- }
}
static void
@@ -234,46 +220,44 @@ smc_puts (const char *s)
static int
smc_getc(void)
{
- volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile cpm8xx_t *cpmp = &(im->im_cpm);
- volatile serialbuffer_t *rtx;
+ immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ cpm8xx_t __iomem *cpmp = &(im->im_cpm);
+ struct serialbuffer __iomem *rtx;
unsigned char c;
+ uint rxindex;
- up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
- rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
+ rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
/* Wait for character to show up. */
- while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
+ while (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
WATCHDOG_RESET ();
/* the characters are read one by one,
* use the rxindex to know the next char to deliver
*/
- c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex);
- rtx->rxindex++;
+ rxindex = in_be32(&rtx->rxindex);
+ c = in_8(rtx->rxbuf + rxindex);
+ rxindex++;
/* check if all char are readout, then make prepare for next receive */
- if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
- rtx->rxindex = 0;
- rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
+ if (rxindex >= in_be16(&rtx->rxbd.cbd_datlen)) {
+ rxindex = 0;
+ setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY);
}
+ out_be32(&rtx->rxindex, rxindex);
return(c);
}
static int
smc_tstc(void)
{
- volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile cpm8xx_t *cpmp = &(im->im_cpm);
- volatile serialbuffer_t *rtx;
-
- up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
+ immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ cpm8xx_t __iomem *cpmp = &(im->im_cpm);
+ struct serialbuffer __iomem *rtx;
- rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
+ rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
- return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
+ return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY);
}
struct serial_device serial_smc_device =
diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c
index 751c089a6d..c91427e904 100644
--- a/arch/powerpc/cpu/mpc8xx/speed.c
+++ b/arch/powerpc/cpu/mpc8xx/speed.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <mpc8xx.h>
#include <asm/processor.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -38,8 +39,8 @@ void get_brgclk(uint sccr)
int get_clocks (void)
{
uint immr = get_immr (0); /* Return full IMMR contents */
- volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
- uint sccr = immap->im_clkrst.car_sccr;
+ immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
+ uint sccr = in_be32(&immap->im_clkrst.car_sccr);
/*
* If for some reason measuring the gclk frequency won't
* work, we return the hardwired value.
diff --git a/arch/powerpc/cpu/mpc8xx/spi.c b/arch/powerpc/cpu/mpc8xx/spi.c
index c7863ecd09..e7d197f968 100644
--- a/arch/powerpc/cpu/mpc8xx/spi.c
+++ b/arch/powerpc/cpu/mpc8xx/spi.c
@@ -44,6 +44,9 @@
#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
#endif
+#define CPM_SPI_BASE_RX CPM_SPI_BASE
+#define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t))
+
/* -------------------
* Function prototypes
* ------------------- */
@@ -80,19 +83,13 @@ static uchar *txbuf =
* *********************************************************************** */
void spi_init_f (void)
{
- unsigned int dpaddr;
-
- volatile spi_t *spi;
- volatile immap_t *immr;
- volatile cpm8xx_t *cp;
- volatile cbd_t *tbdf, *rbdf;
-
- immr = (immap_t *) CONFIG_SYS_IMMR;
- cp = (cpm8xx_t *) &immr->im_cpm;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ cpm8xx_t __iomem *cp = &immr->im_cpm;
+ spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
+ cbd_t __iomem *tbdf, *rbdf;
- spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
/* Disable relocation */
- spi->spi_rpbase = 0;
+ out_be16(&spi->spi_rpbase, 0);
/* 1 */
/* ------------------------------------------------
@@ -107,8 +104,7 @@ void spi_init_f (void)
* PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK)
* PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM)
* -------------------------------------------- */
- cp->cp_pbpar |= 0x0000000E; /* set bits */
- cp->cp_pbpar &= ~0x00000001; /* reset bit */
+ clrsetbits_be32(&cp->cp_pbpar, 0x00000001, 0x0000000E); /* set bits */
/* ----------------------------------------------
* In/Out or per. Function 0/1
@@ -117,7 +113,7 @@ void spi_init_f (void)
* PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK
* PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM
* ---------------------------------------------- */
- cp->cp_pbdir |= 0x0000000F;
+ setbits_be32(&cp->cp_pbdir, 0x0000000F);
/* ----------------------------------------------
* open drain or active output
@@ -127,29 +123,26 @@ void spi_init_f (void)
* PBODR[31] = 0 [0x00000001] -> active output: GPIO OUT: CS for PCUE/CCM
* ---------------------------------------------- */
- cp->cp_pbodr |= 0x00000008;
- cp->cp_pbodr &= ~0x00000007;
+ clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008);
/* Initialize the parameter ram.
* We need to make sure many things are initialized to zero
*/
- spi->spi_rstate = 0;
- spi->spi_rdp = 0;
- spi->spi_rbptr = 0;
- spi->spi_rbc = 0;
- spi->spi_rxtmp = 0;
- spi->spi_tstate = 0;
- spi->spi_tdp = 0;
- spi->spi_tbptr = 0;
- spi->spi_tbc = 0;
- spi->spi_txtmp = 0;
-
- dpaddr = CPM_SPI_BASE;
+ out_be32(&spi->spi_rstate, 0);
+ out_be32(&spi->spi_rdp, 0);
+ out_be16(&spi->spi_rbptr, 0);
+ out_be16(&spi->spi_rbc, 0);
+ out_be32(&spi->spi_rxtmp, 0);
+ out_be32(&spi->spi_tstate, 0);
+ out_be32(&spi->spi_tdp, 0);
+ out_be16(&spi->spi_tbptr, 0);
+ out_be16(&spi->spi_tbc, 0);
+ out_be32(&spi->spi_txtmp, 0);
/* 3 */
/* Set up the SPI parameters in the parameter ram */
- spi->spi_rbase = dpaddr;
- spi->spi_tbase = dpaddr + sizeof (cbd_t);
+ out_be16(&spi->spi_rbase, CPM_SPI_BASE_RX);
+ out_be16(&spi->spi_tbase, CPM_SPI_BASE_TX);
/***********IMPORTANT******************/
@@ -160,45 +153,47 @@ void spi_init_f (void)
* is missing from the sample I2C driver. If you dont
* initialize these pointers, the kernel hangs.
*/
- spi->spi_rbptr = spi->spi_rbase;
- spi->spi_tbptr = spi->spi_tbase;
+ out_be16(&spi->spi_rbptr, CPM_SPI_BASE_RX);
+ out_be16(&spi->spi_tbptr, CPM_SPI_BASE_TX);
/* 4 */
/* Init SPI Tx + Rx Parameters */
- while (cp->cp_cpcr & CPM_CR_FLG)
+ while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
;
- cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | CPM_CR_FLG;
- while (cp->cp_cpcr & CPM_CR_FLG)
+
+ out_be16(&cp->cp_cpcr, mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) |
+ CPM_CR_FLG);
+ while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
;
/* 5 */
/* Set SDMA configuration register */
- immr->im_siu_conf.sc_sdcr = 0x0001;
+ out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001);
/* 6 */
/* Set to big endian. */
- spi->spi_tfcr = SMC_EB;
- spi->spi_rfcr = SMC_EB;
+ out_8(&spi->spi_tfcr, SMC_EB);
+ out_8(&spi->spi_rfcr, SMC_EB);
/* 7 */
/* Set maximum receive size. */
- spi->spi_mrblr = MAX_BUFFER;
+ out_be16(&spi->spi_mrblr, MAX_BUFFER);
/* 8 + 9 */
/* tx and rx buffer descriptors */
- tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
- rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];
+ tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
+ rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
- tbdf->cbd_sc &= ~BD_SC_READY;
- rbdf->cbd_sc &= ~BD_SC_EMPTY;
+ clrbits_be16(&tbdf->cbd_sc, BD_SC_READY);
+ clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY);
/* Set the bd's rx and tx buffer address pointers */
- rbdf->cbd_bufaddr = (ulong) rxbuf;
- tbdf->cbd_bufaddr = (ulong) txbuf;
+ out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf);
+ out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf);
/* 10 + 11 */
- cp->cp_spim = 0; /* Mask all SPI events */
- cp->cp_spie = SPI_EMASK; /* Clear all SPI events */
+ out_8(&cp->cp_spim, 0); /* Mask all SPI events */
+ out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
return;
}
@@ -216,28 +211,24 @@ void spi_init_f (void)
* *********************************************************************** */
void spi_init_r (void)
{
- volatile cpm8xx_t *cp;
- volatile spi_t *spi;
- volatile immap_t *immr;
- volatile cbd_t *tbdf, *rbdf;
-
- immr = (immap_t *) CONFIG_SYS_IMMR;
- cp = (cpm8xx_t *) &immr->im_cpm;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ cpm8xx_t __iomem *cp = &immr->im_cpm;
+ spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
+ cbd_t __iomem *tbdf, *rbdf;
- spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
/* Disable relocation */
- spi->spi_rpbase = 0;
+ out_be16(&spi->spi_rpbase, 0);
/* tx and rx buffer descriptors */
- tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
- rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];
+ tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
+ rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
/* Allocate memory for RX and TX buffers */
rxbuf = (uchar *) malloc (MAX_BUFFER);
txbuf = (uchar *) malloc (MAX_BUFFER);
- rbdf->cbd_bufaddr = (ulong) rxbuf;
- tbdf->cbd_bufaddr = (ulong) txbuf;
+ out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf);
+ out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf);
return;
}
@@ -301,59 +292,46 @@ ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
**************************************************************************** */
ssize_t spi_xfer (size_t count)
{
- volatile immap_t *immr;
- volatile cpm8xx_t *cp;
- volatile spi_t *spi;
- cbd_t *tbdf, *rbdf;
- ushort loop;
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ cpm8xx_t __iomem *cp = &immr->im_cpm;
+ spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
+ cbd_t __iomem *tbdf, *rbdf;
int tm;
- immr = (immap_t *) CONFIG_SYS_IMMR;
- cp = (cpm8xx_t *) &immr->im_cpm;
-
- spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
/* Disable relocation */
- spi->spi_rpbase = 0;
+ out_be16(&spi->spi_rpbase, 0);
- tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
- rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];
+ tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
+ rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
/* Set CS for device */
- cp->cp_pbdat &= ~0x0001;
+ clrbits_be32(&cp->cp_pbdat, 0x0001);
/* Setting tx bd status and data length */
- tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP;
- tbdf->cbd_datlen = count;
+ out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP);
+ out_be16(&tbdf->cbd_datlen, count);
/* Setting rx bd status and data length */
- rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
- rbdf->cbd_datlen = 0; /* rx length has no significance */
-
- loop = cp->cp_spmode & SPMODE_LOOP;
- cp->cp_spmode = /*SPMODE_DIV16 |*/ /* BRG/16 mode not used here */
- loop |
- SPMODE_REV |
- SPMODE_MSTR |
- SPMODE_EN |
- SPMODE_LEN(8) | /* 8 Bits per char */
- SPMODE_PM(0x8) ; /* medium speed */
- cp->cp_spim = 0; /* Mask all SPI events */
- cp->cp_spie = SPI_EMASK; /* Clear all SPI events */
+ out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
+ out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */
+
+ clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR |
+ SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8));
+ out_8(&cp->cp_spim, 0); /* Mask all SPI events */
+ out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
/* start spi transfer */
- cp->cp_spcom |= SPI_STR; /* Start transmit */
+ setbits_8(&cp->cp_spcom, SPI_STR); /* Start transmit */
/* --------------------------------
* Wait for SPI transmit to get out
* or time out (1 second = 1000 ms)
* -------------------------------- */
for (tm=0; tm<1000; ++tm) {
- if (cp->cp_spie & SPI_TXB) { /* Tx Buffer Empty */
+ if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */
break;
- }
- if ((tbdf->cbd_sc & BD_SC_READY) == 0) {
+ if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0)
break;
- }
udelay (1000);
}
if (tm >= 1000) {
@@ -361,7 +339,7 @@ ssize_t spi_xfer (size_t count)
}
/* Clear CS for device */
- cp->cp_pbdat |= 0x0001;
+ setbits_be32(&cp->cp_pbdat, 0x0001);
return count;
}
diff --git a/arch/powerpc/include/asm/iopin_8xx.h b/arch/powerpc/include/asm/iopin_8xx.h
index 8db0fa2a1c..beca988d77 100644
--- a/arch/powerpc/include/asm/iopin_8xx.h
+++ b/arch/powerpc/include/asm/iopin_8xx.h
@@ -12,6 +12,7 @@
#include <linux/types.h>
#include <asm/8xx_immap.h>
+#include <asm/io.h>
#ifdef __KERNEL__
@@ -29,54 +30,72 @@ typedef struct {
static __inline__ void
iopin_set_high(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
- *datp |= (1 << (15 - iopin->pin));
+ ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+ setbits_be16(datp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
- *datp |= (1 << (31 - iopin->pin));
+ uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+ setbits_be32(datp, 1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
- *datp |= (1 << (15 - iopin->pin));
+ ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+ setbits_be16(datp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
- *datp |= (1 << (15 - iopin->pin));
+ ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+ setbits_be16(datp, 1 << (15 - iopin->pin));
}
}
static __inline__ void
iopin_set_low(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
- *datp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+ clrbits_be16(datp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
- *datp &= ~(1 << (31 - iopin->pin));
+ uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+ clrbits_be32(datp, 1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
- *datp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+ clrbits_be16(datp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
- *datp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+ clrbits_be16(datp, 1 << (15 - iopin->pin));
}
}
static __inline__ uint
iopin_is_high(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
- return (*datp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+ return (in_be16(datp) >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
- return (*datp >> (31 - iopin->pin)) & 1;
+ uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+ return (in_be32(datp) >> (31 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
- return (*datp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+ return (in_be16(datp) >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
- return (*datp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+ return (in_be16(datp) >> (15 - iopin->pin)) & 1;
}
return 0;
}
@@ -84,18 +103,24 @@ iopin_is_high(iopin_t *iopin)
static __inline__ uint
iopin_is_low(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
- return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+ return ((in_be16(datp) >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
- return ((*datp >> (31 - iopin->pin)) & 1) ^ 1;
+ uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+ return ((in_be32(datp) >> (31 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
- return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+ return ((in_be16(datp) >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
- return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+ return ((in_be16(datp) >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
}
@@ -103,54 +128,72 @@ iopin_is_low(iopin_t *iopin)
static __inline__ void
iopin_set_out(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
- *dirp |= (1 << (15 - iopin->pin));
+ ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+ setbits_be16(dirp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
- *dirp |= (1 << (31 - iopin->pin));
+ uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+ setbits_be32(dirp, 1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
- *dirp |= (1 << (15 - iopin->pin));
+ ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+ setbits_be16(dirp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
- *dirp |= (1 << (15 - iopin->pin));
+ ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+ setbits_be16(dirp, 1 << (15 - iopin->pin));
}
}
static __inline__ void
iopin_set_in(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
- *dirp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+ clrbits_be16(dirp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
- *dirp &= ~(1 << (31 - iopin->pin));
+ uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+ clrbits_be32(dirp, 1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
- *dirp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+ clrbits_be16(dirp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
- *dirp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+ clrbits_be16(dirp, 1 << (15 - iopin->pin));
}
}
static __inline__ uint
iopin_is_out(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
- return (*dirp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+ return (in_be16(dirp) >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
- return (*dirp >> (31 - iopin->pin)) & 1;
+ uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+ return (in_be32(dirp) >> (31 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
- return (*dirp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+ return (in_be16(dirp) >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
- return (*dirp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+ return (in_be16(dirp) >> (15 - iopin->pin)) & 1;
}
return 0;
}
@@ -158,18 +201,24 @@ iopin_is_out(iopin_t *iopin)
static __inline__ uint
iopin_is_in(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
- return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+ return ((in_be16(dirp) >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
- return ((*dirp >> (31 - iopin->pin)) & 1) ^ 1;
+ uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+ return ((in_be32(dirp) >> (31 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
- return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+ return ((in_be16(dirp) >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
- return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+ return ((in_be16(dirp) >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
}
@@ -177,36 +226,48 @@ iopin_is_in(iopin_t *iopin)
static __inline__ void
iopin_set_odr(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
- *odrp |= (1 << (15 - iopin->pin));
+ ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+ setbits_be16(odrp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
- *odrp |= (1 << (31 - iopin->pin));
+ ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+ setbits_be16(odrp, 1 << (31 - iopin->pin));
}
}
static __inline__ void
iopin_set_act(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
- *odrp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+ clrbits_be16(odrp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
- *odrp &= ~(1 << (31 - iopin->pin));
+ ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+ clrbits_be16(odrp, 1 << (31 - iopin->pin));
}
}
static __inline__ uint
iopin_is_odr(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
- return (*odrp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+ return (in_be16(odrp) >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
- return (*odrp >> (31 - iopin->pin)) & 1;
+ ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+ return (in_be16(odrp) >> (31 - iopin->pin)) & 1;
}
return 0;
}
@@ -214,12 +275,16 @@ iopin_is_odr(iopin_t *iopin)
static __inline__ uint
iopin_is_act(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
- return ((*odrp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+ return ((in_be16(odrp) >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
- return ((*odrp >> (31 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+ return ((in_be16(odrp) >> (31 - iopin->pin)) & 1) ^ 1;
}
return 0;
}
@@ -227,54 +292,72 @@ iopin_is_act(iopin_t *iopin)
static __inline__ void
iopin_set_ded(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
- *parp |= (1 << (15 - iopin->pin));
+ ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+ setbits_be16(parp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
- *parp |= (1 << (31 - iopin->pin));
+ uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+ setbits_be32(parp, 1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
- *parp |= (1 << (15 - iopin->pin));
+ ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+ setbits_be16(parp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
- *parp |= (1 << (15 - iopin->pin));
+ ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+ setbits_be16(parp, 1 << (15 - iopin->pin));
}
}
static __inline__ void
iopin_set_gen(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
- *parp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+ clrbits_be16(parp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
- *parp &= ~(1 << (31 - iopin->pin));
+ uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+ clrbits_be32(parp, 1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
- *parp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+ clrbits_be16(parp, 1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
- *parp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+ clrbits_be16(parp, 1 << (15 - iopin->pin));
}
}
static __inline__ uint
iopin_is_ded(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
- return (*parp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+ return (in_be16(parp) >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
- return (*parp >> (31 - iopin->pin)) & 1;
+ uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+ return (in_be32(parp) >> (31 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
- return (*parp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+ return (in_be16(parp) >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
- return (*parp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+ return (in_be16(parp) >> (15 - iopin->pin)) & 1;
}
return 0;
}
@@ -282,18 +365,24 @@ iopin_is_ded(iopin_t *iopin)
static __inline__ uint
iopin_is_gen(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
- return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+ return ((in_be16(parp) >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
- return ((*parp >> (31 - iopin->pin)) & 1) ^ 1;
+ uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+ return ((in_be32(parp) >> (31 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
- return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+ return ((in_be16(parp) >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
- return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+ return ((in_be16(parp) >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
}
@@ -301,27 +390,36 @@ iopin_is_gen(iopin_t *iopin)
static __inline__ void
iopin_set_opt2(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
- *sorp |= (1 << (15 - iopin->pin));
+ ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+ setbits_be16(sorp, 1 << (15 - iopin->pin));
}
}
static __inline__ void
iopin_set_opt1(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
- *sorp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+ clrbits_be16(sorp, 1 << (15 - iopin->pin));
}
}
static __inline__ uint
iopin_is_opt2(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
- return (*sorp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+ return (in_be16(sorp) >> (15 - iopin->pin)) & 1;
}
return 0;
}
@@ -329,9 +427,12 @@ iopin_is_opt2(iopin_t *iopin)
static __inline__ uint
iopin_is_opt1(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
- return ((*sorp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+ return ((in_be16(sorp) >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
}
@@ -339,27 +440,36 @@ iopin_is_opt1(iopin_t *iopin)
static __inline__ void
iopin_set_falledge(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
- *intp |= (1 << (15 - iopin->pin));
+ ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+ setbits_be16(intp, 1 << (15 - iopin->pin));
}
}
static __inline__ void
iopin_set_anyedge(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
- *intp &= ~(1 << (15 - iopin->pin));
+ ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+ clrbits_be16(intp, 1 << (15 - iopin->pin));
}
}
static __inline__ uint
iopin_is_falledge(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
- return (*intp >> (15 - iopin->pin)) & 1;
+ ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+ return (in_be16(intp) >> (15 - iopin->pin)) & 1;
}
return 0;
}
@@ -367,9 +477,12 @@ iopin_is_falledge(iopin_t *iopin)
static __inline__ uint
iopin_is_anyedge(iopin_t *iopin)
{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
- return ((*intp >> (15 - iopin->pin)) & 1) ^ 1;
+ ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+ return ((in_be16(intp) >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
}
diff --git a/arch/powerpc/lib/time.c b/arch/powerpc/lib/time.c
index 4cbb65eb68..41a271a42d 100644
--- a/arch/powerpc/lib/time.c
+++ b/arch/powerpc/lib/time.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <asm/io.h>
/* ------------------------------------------------------------------------- */
@@ -65,10 +66,10 @@ int timer_init(void)
unsigned long temp;
#if defined(CONFIG_8xx)
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
/* unlock */
- immap->im_sitk.sitk_tbk = KAPWR_KEY;
+ out_be32(&immap->im_sitk.sitk_tbk, KAPWR_KEY);
#endif
/* reset */
@@ -77,7 +78,7 @@ int timer_init(void)
#if defined(CONFIG_8xx)
/* enable */
- immap->im_sit.sit_tbscr |= TBSCR_TBE;
+ setbits_be16(&immap->im_sit.sit_tbscr, TBSCR_TBE);
#endif
return (0);
}
diff --git a/include/watchdog.h b/include/watchdog.h
index a3a2eeaf1b..64b59f107a 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -74,7 +74,7 @@ int init_func_watchdog_reset(void);
/* MPC 8xx */
#if defined(CONFIG_8xx) && !defined(__ASSEMBLY__)
- void reset_8xx_watchdog(volatile immap_t *immr);
+ void reset_8xx_watchdog(immap_t __iomem *immr);
#endif
#if defined(CONFIG_HW_WATCHDOG) && !defined(__ASSEMBLY__)
--
2.12.0
^ permalink raw reply related [flat|nested] 35+ messages in thread* [U-Boot] [PATCH v2 03/10] powerpc, 8xx: Use IO accessors to access IO memory
2017-07-06 8:33 ` [U-Boot] [PATCH v2 03/10] powerpc, 8xx: Use IO accessors to access IO memory Christophe Leroy
@ 2017-07-06 9:41 ` Heiko Schocher
2017-07-09 0:24 ` [U-Boot] [U-Boot, v2, " Tom Rini
1 sibling, 0 replies; 35+ messages in thread
From: Heiko Schocher @ 2017-07-06 9:41 UTC (permalink / raw)
To: u-boot
Hello Christophe,
Am 06.07.2017 um 10:33 schrieb Christophe Leroy:
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
> arch/powerpc/cpu/mpc8xx/cpu.c | 58 +++---
> arch/powerpc/cpu/mpc8xx/cpu_init.c | 98 ++++------
> arch/powerpc/cpu/mpc8xx/fec.c | 262 +++++++++++++------------
> arch/powerpc/cpu/mpc8xx/immap.c | 120 ++++++------
> arch/powerpc/cpu/mpc8xx/interrupts.c | 65 +++---
> arch/powerpc/cpu/mpc8xx/reginfo.c | 70 ++++---
> arch/powerpc/cpu/mpc8xx/serial.c | 182 ++++++++---------
> arch/powerpc/cpu/mpc8xx/speed.c | 5 +-
> arch/powerpc/cpu/mpc8xx/spi.c | 166 +++++++---------
> arch/powerpc/include/asm/iopin_8xx.h | 369 +++++++++++++++++++++++------------
> arch/powerpc/lib/time.c | 7 +-
> include/watchdog.h | 2 +-
> 12 files changed, 739 insertions(+), 665 deletions(-)
Reviewed-by: Heiko Schocher <hs@denx.de>
bye,
Heiko
>
> diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c
> index 80b9596813..28cc182957 100644
> --- a/arch/powerpc/cpu/mpc8xx/cpu.c
> +++ b/arch/powerpc/cpu/mpc8xx/cpu.c
> @@ -41,7 +41,7 @@ static int check_CPU (long clock, uint pvr, uint immr)
> {
> char *id_str =
> NULL;
> - volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
> + immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
> uint k, m;
> char buf[32];
> char pre = 'X';
> @@ -54,7 +54,7 @@ static int check_CPU (long clock, uint pvr, uint immr)
> return -1;
>
> k = (immr << 16) |
> - immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)];
> + in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
> m = 0;
> suf = "";
>
> @@ -95,10 +95,9 @@ static int check_CPU (long clock, uint pvr, uint immr)
>
> /* do we have a FEC (860T/P or 852/859/866/885)? */
>
> - immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
> - if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
> + out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678);
> + if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
> printf (" FEC present");
> - }
>
> if (!m) {
> puts (cpu_warning);
> @@ -127,11 +126,11 @@ int checkcpu (void)
>
> int checkicache (void)
> {
> - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
> - volatile memctl8xx_t *memctl = &immap->im_memctl;
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + memctl8xx_t __iomem *memctl = &immap->im_memctl;
> u32 cacheon = rd_ic_cst () & IDC_ENABLED;
> -
> - u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
> + /* probe in flash memoryarea */
> + u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
> u32 m;
> u32 lines = -1;
>
> @@ -168,11 +167,11 @@ int checkicache (void)
>
> int checkdcache (void)
> {
> - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
> - volatile memctl8xx_t *memctl = &immap->im_memctl;
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + memctl8xx_t __iomem *memctl = &immap->im_memctl;
> u32 cacheon = rd_dc_cst () & IDC_ENABLED;
> -
> - u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
> + /* probe in flash memoryarea */
> + u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
> u32 m;
> u32 lines = -1;
>
> @@ -204,12 +203,12 @@ void upmconfig (uint upm, uint * table, uint size)
> {
> uint i;
> uint addr = 0;
> - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
> - volatile memctl8xx_t *memctl = &immap->im_memctl;
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + memctl8xx_t __iomem *memctl = &immap->im_memctl;
>
> for (i = 0; i < size; i++) {
> - memctl->memc_mdr = table[i]; /* (16-15) */
> - memctl->memc_mcr = addr | upm; /* (16-16) */
> + out_be32(&memctl->memc_mdr, table[i]); /* (16-15) */
> + out_be32(&memctl->memc_mcr, addr | upm); /* (16-16) */
> addr++;
> }
> }
> @@ -220,9 +219,10 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> {
> ulong msr, addr;
>
> - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> - immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */
> + /* Checkstop Reset enable */
> + setbits_be32(&immap->im_clkrst.car_plprcr, PLPRCR_CSR);
>
> /* Interrupts and MMU off */
> __asm__ volatile ("mtspr 81, 0");
> @@ -260,14 +260,13 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> unsigned long get_tbclk (void)
> {
> uint immr = get_immr (0); /* Return full IMMR contents */
> - volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
> + immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
> ulong oscclk, factor, pll;
>
> - if (immap->im_clkrst.car_sccr & SCCR_TBS) {
> + if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
> return (gd->cpu_clk / 16);
> - }
>
> - pll = immap->im_clkrst.car_plprcr;
> + pll = in_be32(&immap->im_clkrst.car_plprcr);
>
> #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
>
> @@ -287,9 +286,10 @@ unsigned long get_tbclk (void)
>
> oscclk = gd->cpu_clk / factor;
>
> - if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
> + if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
> + factor > 2)
> return (oscclk / 4);
> - }
> +
> return (oscclk / 16);
> }
>
> @@ -300,7 +300,7 @@ void watchdog_reset (void)
> {
> int re_enable = disable_interrupts ();
>
> - reset_8xx_watchdog ((immap_t *) CONFIG_SYS_IMMR);
> + reset_8xx_watchdog((immap_t __iomem *)CONFIG_SYS_IMMR);
> if (re_enable)
> enable_interrupts ();
> }
> @@ -308,13 +308,13 @@ void watchdog_reset (void)
>
> #if defined(CONFIG_WATCHDOG)
>
> -void reset_8xx_watchdog (volatile immap_t * immr)
> +void reset_8xx_watchdog(immap_t __iomem *immr)
> {
> /*
> * All other boards use the MPC8xx Internal Watchdog
> */
> - immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */
> - immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */
> + out_be16(&immr->im_siu_conf.sc_swsr, 0x556c); /* write magic1 */
> + out_be16(&immr->im_siu_conf.sc_swsr, 0xaa39); /* write magic2 */
> }
> #endif /* CONFIG_WATCHDOG */
>
> diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
> index 0f935aff9e..cf1280983a 100644
> --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
> +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
> @@ -10,6 +10,7 @@
>
> #include <mpc8xx.h>
> #include <commproc.h>
> +#include <asm/io.h>
>
> /*
> * Breath some life into the CPU...
> @@ -18,46 +19,41 @@
> * initialize a bunch of registers,
> * initialize the UPM's
> */
> -void cpu_init_f (volatile immap_t * immr)
> +void cpu_init_f(immap_t __iomem *immr)
> {
> - volatile memctl8xx_t *memctl = &immr->im_memctl;
> -# ifdef CONFIG_SYS_PLPRCR
> - ulong mfmask;
> -# endif
> + memctl8xx_t __iomem *memctl = &immr->im_memctl;
> ulong reg;
>
> /* SYPCR - contains watchdog control (11-9) */
>
> - immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR;
> + out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR);
>
> #if defined(CONFIG_WATCHDOG)
> reset_8xx_watchdog (immr);
> #endif /* CONFIG_WATCHDOG */
>
> /* SIUMCR - contains debug pin configuration (11-6) */
> - immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR;
> + setbits_be32(&immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR);
> /* initialize timebase status and control register (11-26) */
> /* unlock TBSCRK */
>
> - immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
> - immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR;
> + out_be32(&immr->im_sitk.sitk_tbscrk, KAPWR_KEY);
> + out_be16(&immr->im_sit.sit_tbscr, CONFIG_SYS_TBSCR);
>
> /* initialize the PIT (11-31) */
>
> - immr->im_sitk.sitk_piscrk = KAPWR_KEY;
> - immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
> + out_be32(&immr->im_sitk.sitk_piscrk, KAPWR_KEY);
> + out_be16(&immr->im_sit.sit_piscr, CONFIG_SYS_PISCR);
>
> /* System integration timers. Don't change EBDF! (15-27) */
>
> - immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
> - reg = immr->im_clkrst.car_sccr;
> - reg &= SCCR_MASK;
> - reg |= CONFIG_SYS_SCCR;
> - immr->im_clkrst.car_sccr = reg;
> + out_be32(&immr->im_clkrstk.cark_sccrk, KAPWR_KEY);
> + clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK,
> + CONFIG_SYS_SCCR);
>
> /* PLL (CPU clock) settings (15-30) */
>
> - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
> + out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
>
> /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
> * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
> @@ -67,27 +63,19 @@ void cpu_init_f (volatile immap_t * immr)
> * For newer (starting MPC866) chips PLPRCR layout is different.
> */
> #ifdef CONFIG_SYS_PLPRCR
> - mfmask = PLPRCR_MFACT_MSK;
> -
> - if ((CONFIG_SYS_PLPRCR & mfmask) != 0)
> - reg = CONFIG_SYS_PLPRCR; /* reset control bits */
> - else {
> - reg = immr->im_clkrst.car_plprcr;
> - reg &= mfmask; /* isolate MF-related fields */
> - reg |= CONFIG_SYS_PLPRCR; /* reset control bits */
> - }
> - immr->im_clkrst.car_plprcr = reg;
> + if ((CONFIG_SYS_PLPRCR & PLPRCR_MFACT_MSK) != 0) /* reset control bits*/
> + out_be32(&immr->im_clkrst.car_plprcr, CONFIG_SYS_PLPRCR);
> + else /* isolate MF-related fields and reset control bits */
> + clrsetbits_be32(&immr->im_clkrst.car_plprcr, ~PLPRCR_MFACT_MSK,
> + CONFIG_SYS_PLPRCR);
> #endif
>
> /*
> * Memory Controller:
> */
>
> - /* perform BR0 reset that MPC850 Rev. A can't guarantee */
> - reg = memctl->memc_br0;
> - reg &= BR_PS_MSK; /* Clear everything except Port Size bits */
> - reg |= BR_V; /* then add just the "Bank Valid" bit */
> - memctl->memc_br0 = reg;
> + /* Clear everything except Port Size bits & add the "Bank Valid" bit */
> + clrsetbits_be32(&memctl->memc_br0, ~BR_PS_MSK, BR_V);
>
> /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
> * preliminary addresses - these have to be modified later
> @@ -114,61 +102,61 @@ void cpu_init_f (volatile immap_t * immr)
> */
>
> #if defined(CONFIG_SYS_OR0_REMAP)
> - memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
> + out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_REMAP);
> #endif
> #if defined(CONFIG_SYS_OR1_REMAP)
> - memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
> + out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_REMAP);
> #endif
> #if defined(CONFIG_SYS_OR5_REMAP)
> - memctl->memc_or5 = CONFIG_SYS_OR5_REMAP;
> + out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_REMAP);
> #endif
>
> /* now restrict to preliminary range */
> - memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
> - memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
> + out_be32(&memctl->memc_br0, CONFIG_SYS_BR0_PRELIM);
> + out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_PRELIM);
>
> #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
> - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
> - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
> + out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
> + out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
> #endif
>
> #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
> - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
> - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
> + out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_PRELIM);
> + out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_PRELIM);
> #endif
>
> #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
> - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
> - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
> + out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_PRELIM);
> + out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_PRELIM);
> #endif
>
> #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
> - memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
> - memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
> + out_be32(&memctl->memc_or4, CONFIG_SYS_OR4_PRELIM);
> + out_be32(&memctl->memc_br4, CONFIG_SYS_BR4_PRELIM);
> #endif
>
> #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
> - memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
> - memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
> + out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_PRELIM);
> + out_be32(&memctl->memc_br5, CONFIG_SYS_BR5_PRELIM);
> #endif
>
> #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
> - memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM;
> - memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM;
> + out_be32(&memctl->memc_or6, CONFIG_SYS_OR6_PRELIM);
> + out_be32(&memctl->memc_br6, CONFIG_SYS_BR6_PRELIM);
> #endif
>
> #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
> - memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM;
> - memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
> + out_be32(&memctl->memc_or7, CONFIG_SYS_OR7_PRELIM);
> + out_be32(&memctl->memc_br7, CONFIG_SYS_BR7_PRELIM);
> #endif
>
> /*
> * Reset CPM
> */
> - immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG;
> - do { /* Spin until command processed */
> - __asm__ ("eieio");
> - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
> + out_be16(&immr->im_cpm.cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
> + /* Spin until command processed */
> + while (in_be16(&immr->im_cpm.cp_cpcr) & CPM_CR_FLG)
> + ;
> }
>
> /*
> diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
> index 7aa526d7ec..eaaea2d4e8 100644
> --- a/arch/powerpc/cpu/mpc8xx/fec.c
> +++ b/arch/powerpc/cpu/mpc8xx/fec.c
> @@ -10,6 +10,7 @@
> #include <commproc.h>
> #include <malloc.h>
> #include <net.h>
> +#include <asm/io.h>
>
> #include <phy.h>
>
> @@ -115,12 +116,12 @@ static uint txIdx; /* index of the current TX buffer */
> * Provide for Double Buffering
> */
>
> -typedef volatile struct CommonBufferDescriptor {
> +struct common_buf_desc {
> cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
> cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
> -} RTXBD;
> +};
>
> -static RTXBD *rtx = NULL;
> +static struct common_buf_desc __iomem *rtx;
>
> static int fec_send(struct eth_device *dev, void *packet, int length);
> static int fec_recv(struct eth_device* dev);
> @@ -189,13 +190,15 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
> {
> int j, rc;
> struct ether_fcc_info_s *efis = dev->priv;
> - volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
> + fec_t __iomem *fecp =
> + (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
>
> /* section 16.9.23.3
> * Wait for ready
> */
> j = 0;
> - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
> + while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
> + (j < TOUT_LOOP)) {
> udelay(1);
> j++;
> }
> @@ -203,16 +206,18 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
> printf("TX not ready\n");
> }
>
> - rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
> - rtx->txbd[txIdx].cbd_datlen = length;
> - rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
> - __asm__ ("eieio");
> + out_be32(&rtx->txbd[txIdx].cbd_bufaddr, (uint)packet);
> + out_be16(&rtx->txbd[txIdx].cbd_datlen, length);
> + setbits_be16(&rtx->txbd[txIdx].cbd_sc,
> + BD_ENET_TX_READY | BD_ENET_TX_LAST);
>
> /* Activate transmit Buffer Descriptor polling */
> - fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
> + /* Descriptor polling active */
> + out_be32(&fecp->fec_x_des_active, 0x01000000);
>
> j = 0;
> - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
> + while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
> + (j < TOUT_LOOP)) {
> udelay(1);
> j++;
> }
> @@ -220,7 +225,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
> printf("TX timeout\n");
> }
> /* return only status bits */;
> - rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
> + rc = in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_STATS;
>
> txIdx = (txIdx + 1) % TX_BUF_CNT;
>
> @@ -230,21 +235,20 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
> static int fec_recv (struct eth_device *dev)
> {
> struct ether_fcc_info_s *efis = dev->priv;
> - volatile fec_t *fecp =
> - (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
> + fec_t __iomem *fecp =
> + (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
> int length;
>
> for (;;) {
> /* section 16.9.23.2 */
> - if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
> + if (in_be16(&rtx->rxbd[rxIdx].cbd_sc) & BD_ENET_RX_EMPTY) {
> length = -1;
> break; /* nothing received - leave for() loop */
> }
>
> - length = rtx->rxbd[rxIdx].cbd_datlen;
> + length = in_be16(&rtx->rxbd[rxIdx].cbd_datlen);
>
> - if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
> - } else {
> + if (!(in_be16(&rtx->rxbd[rxIdx].cbd_sc) & 0x003f)) {
> uchar *rx = net_rx_packets[rxIdx];
>
> length -= 4;
> @@ -263,22 +267,21 @@ static int fec_recv (struct eth_device *dev)
> }
>
> /* Give the buffer back to the FEC. */
> - rtx->rxbd[rxIdx].cbd_datlen = 0;
> + out_be16(&rtx->rxbd[rxIdx].cbd_datlen, 0);
>
> /* wrap around buffer index when necessary */
> if ((rxIdx + 1) >= PKTBUFSRX) {
> - rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
> - (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
> + out_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc,
> + BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
> rxIdx = 0;
> } else {
> - rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
> + out_be16(&rtx->rxbd[rxIdx].cbd_sc, BD_ENET_RX_EMPTY);
> rxIdx++;
> }
>
> - __asm__ ("eieio");
> -
> /* Try to fill Buffer Descriptors */
> - fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
> + /* Descriptor polling active */
> + out_be32(&fecp->fec_r_des_active, 0x01000000);
> }
>
> return length;
> @@ -313,11 +316,12 @@ static inline void fec_10Mbps(struct eth_device *dev)
> struct ether_fcc_info_s *efis = dev->priv;
> int fecidx = efis->ether_index;
> uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> if ((unsigned int)fecidx >= 2)
> hang();
>
> - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr |= mask;
> + setbits_be32(&immr->im_cpm.cp_cptr, mask);
> }
>
> static inline void fec_100Mbps(struct eth_device *dev)
> @@ -325,11 +329,12 @@ static inline void fec_100Mbps(struct eth_device *dev)
> struct ether_fcc_info_s *efis = dev->priv;
> int fecidx = efis->ether_index;
> uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> if ((unsigned int)fecidx >= 2)
> hang();
>
> - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_cptr &= ~mask;
> + clrbits_be32(&immr->im_cpm.cp_cptr, mask);
> }
>
> #endif
> @@ -337,25 +342,27 @@ static inline void fec_100Mbps(struct eth_device *dev)
> static inline void fec_full_duplex(struct eth_device *dev)
> {
> struct ether_fcc_info_s *efis = dev->priv;
> - volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
> + fec_t __iomem *fecp =
> + (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
>
> - fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT;
> - fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */
> + clrbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
> + setbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */
> }
>
> static inline void fec_half_duplex(struct eth_device *dev)
> {
> struct ether_fcc_info_s *efis = dev->priv;
> - volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
> + fec_t __iomem *fecp =
> + (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
>
> - fecp->fec_r_cntrl |= FEC_RCNTRL_DRT;
> - fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */
> + setbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
> + clrbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */
> }
>
> static void fec_pin_init(int fecidx)
> {
> bd_t *bd = gd->bd;
> - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> /*
> * Set MII speed to 2.5 MHz or slightly below.
> @@ -369,12 +376,13 @@ static void fec_pin_init(int fecidx)
> *
> * All MII configuration is done via FEC1 registers:
> */
> - immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
> + out_be32(&immr->im_cpm.cp_fec1.fec_mii_speed,
> + ((bd->bi_intfreq + 4999999) / 5000000) << 1);
>
> #if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
> /* use MDC for MII */
> - immr->im_ioport.iop_pdpar |= 0x0080;
> - immr->im_ioport.iop_pddir &= ~0x0080;
> + setbits_be16(&immr->im_ioport.iop_pdpar, 0x0080);
> + clrbits_be16(&immr->im_ioport.iop_pddir, 0x0080);
> #endif
>
> if (fecidx == 0) {
> @@ -384,37 +392,37 @@ static void fec_pin_init(int fecidx)
>
> #if !defined(CONFIG_RMII)
>
> - immr->im_ioport.iop_papar |= 0xf830;
> - immr->im_ioport.iop_padir |= 0x0830;
> - immr->im_ioport.iop_padir &= ~0xf000;
> + setbits_be16(&immr->im_ioport.iop_papar, 0xf830);
> + setbits_be16(&immr->im_ioport.iop_padir, 0x0830);
> + clrbits_be16(&immr->im_ioport.iop_padir, 0xf000);
>
> - immr->im_cpm.cp_pbpar |= 0x00001001;
> - immr->im_cpm.cp_pbdir &= ~0x00001001;
> + setbits_be32(&immr->im_cpm.cp_pbpar, 0x00001001);
> + clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00001001);
>
> - immr->im_ioport.iop_pcpar |= 0x000c;
> - immr->im_ioport.iop_pcdir &= ~0x000c;
> + setbits_be16(&immr->im_ioport.iop_pcpar, 0x000c);
> + clrbits_be16(&immr->im_ioport.iop_pcdir, 0x000c);
>
> - immr->im_cpm.cp_pepar |= 0x00000003;
> - immr->im_cpm.cp_pedir |= 0x00000003;
> - immr->im_cpm.cp_peso &= ~0x00000003;
> + setbits_be32(&immr->im_cpm.cp_pepar, 0x00000003);
> + setbits_be32(&immr->im_cpm.cp_pedir, 0x00000003);
> + clrbits_be32(&immr->im_cpm.cp_peso, 0x00000003);
>
> - immr->im_cpm.cp_cptr &= ~0x00000100;
> + clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
>
> #else
>
> #if !defined(CONFIG_FEC1_PHY_NORXERR)
> - immr->im_ioport.iop_papar |= 0x1000;
> - immr->im_ioport.iop_padir &= ~0x1000;
> + setbits_be16(&immr->im_ioport.iop_papar, 0x1000);
> + clrbits_be16(&immr->im_ioport.iop_padir, 0x1000);
> #endif
> - immr->im_ioport.iop_papar |= 0xe810;
> - immr->im_ioport.iop_padir |= 0x0810;
> - immr->im_ioport.iop_padir &= ~0xe000;
> + setbits_be16(&immr->im_ioport.iop_papar, 0xe810);
> + setbits_be16(&immr->im_ioport.iop_padir, 0x0810);
> + clrbits_be16(&immr->im_ioport.iop_padir, 0xe000);
>
> - immr->im_cpm.cp_pbpar |= 0x00000001;
> - immr->im_cpm.cp_pbdir &= ~0x00000001;
> + setbits_be32(&immr->im_cpm.cp_pbpar, 0x00000001);
> + clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00000001);
>
> - immr->im_cpm.cp_cptr |= 0x00000100;
> - immr->im_cpm.cp_cptr &= ~0x00000050;
> + setbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
> + clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000050);
>
> #endif /* !CONFIG_RMII */
>
> @@ -422,9 +430,8 @@ static void fec_pin_init(int fecidx)
> /*
> * Configure all of port D for MII.
> */
> - immr->im_ioport.iop_pdpar = 0x1fff;
> -
> - immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
> + out_be16(&immr->im_ioport.iop_pdpar, 0x1fff);
> + out_be16(&immr->im_ioport.iop_pddir, 0x1fff);
> #endif
>
> #endif /* CONFIG_ETHER_ON_FEC1 */
> @@ -435,26 +442,26 @@ static void fec_pin_init(int fecidx)
> #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
>
> #if !defined(CONFIG_RMII)
> - immr->im_cpm.cp_pepar |= 0x0003fffc;
> - immr->im_cpm.cp_pedir |= 0x0003fffc;
> - immr->im_cpm.cp_peso &= ~0x000087fc;
> - immr->im_cpm.cp_peso |= 0x00037800;
> + setbits_be32(&immr->im_cpm.cp_pepar, 0x0003fffc);
> + setbits_be32(&immr->im_cpm.cp_pedir, 0x0003fffc);
> + clrbits_be32(&immr->im_cpm.cp_peso, 0x000087fc);
> + setbits_be32(&immr->im_cpm.cp_peso, 0x00037800);
>
> - immr->im_cpm.cp_cptr &= ~0x00000080;
> + clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
> #else
>
> #if !defined(CONFIG_FEC2_PHY_NORXERR)
> - immr->im_cpm.cp_pepar |= 0x00000010;
> - immr->im_cpm.cp_pedir |= 0x00000010;
> - immr->im_cpm.cp_peso &= ~0x00000010;
> + setbits_be32(&immr->im_cpm.cp_pepar, 0x00000010);
> + setbits_be32(&immr->im_cpm.cp_pedir, 0x00000010);
> + clrbits_be32(&immr->im_cpm.cp_peso, 0x00000010);
> #endif
> - immr->im_cpm.cp_pepar |= 0x00039620;
> - immr->im_cpm.cp_pedir |= 0x00039620;
> - immr->im_cpm.cp_peso |= 0x00031000;
> - immr->im_cpm.cp_peso &= ~0x00008620;
> + setbits_be32(&immr->im_cpm.cp_pepar, 0x00039620);
> + setbits_be32(&immr->im_cpm.cp_pedir, 0x00039620);
> + setbits_be32(&immr->im_cpm.cp_peso, 0x00031000);
> + clrbits_be32(&immr->im_cpm.cp_peso, 0x00008620);
>
> - immr->im_cpm.cp_cptr |= 0x00000080;
> - immr->im_cpm.cp_cptr &= ~0x00000028;
> + setbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
> + clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000028);
> #endif /* CONFIG_RMII */
>
> #endif /* CONFIG_MPC885_FAMILY */
> @@ -464,7 +471,7 @@ static void fec_pin_init(int fecidx)
> }
> }
>
> -static int fec_reset(volatile fec_t *fecp)
> +static int fec_reset(fec_t __iomem *fecp)
> {
> int i;
>
> @@ -476,12 +483,11 @@ static int fec_reset(volatile fec_t *fecp)
> * still in progress.
> */
>
> - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
> - for (i = 0;
> - (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
> - ++i) {
> + out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
> + for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
> + (i < FEC_RESET_DELAY); ++i)
> udelay (1);
> - }
> +
> if (i == FEC_RESET_DELAY)
> return -1;
>
> @@ -491,9 +497,9 @@ static int fec_reset(volatile fec_t *fecp)
> static int fec_init (struct eth_device *dev, bd_t * bd)
> {
> struct ether_fcc_info_s *efis = dev->priv;
> - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
> - volatile fec_t *fecp =
> - (volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + fec_t __iomem *fecp =
> + (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
> int i;
>
> #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
> @@ -510,41 +516,42 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
>
> /* We use strictly polling mode only
> */
> - fecp->fec_imask = 0;
> + out_be32(&fecp->fec_imask, 0);
>
> /* Clear any pending interrupt
> */
> - fecp->fec_ievent = 0xffc0;
> + out_be32(&fecp->fec_ievent, 0xffc0);
>
> /* No need to set the IVEC register */
>
> /* Set station address
> */
> #define ea dev->enetaddr
> - fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
> - fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
> + out_be32(&fecp->fec_addr_low, (ea[0] << 24) | (ea[1] << 16) |
> + (ea[2] << 8) | ea[3]);
> + out_be16(&fecp->fec_addr_high, (ea[4] << 8) | ea[5]);
> #undef ea
>
> #if defined(CONFIG_CMD_CDP)
> /*
> * Turn on multicast address hash table
> */
> - fecp->fec_hash_table_high = 0xffffffff;
> - fecp->fec_hash_table_low = 0xffffffff;
> + out_be32(&fecp->fec_hash_table_high, 0xffffffff);
> + out_be32(&fecp->fec_hash_table_low, 0xffffffff);
> #else
> /* Clear multicast address hash table
> */
> - fecp->fec_hash_table_high = 0;
> - fecp->fec_hash_table_low = 0;
> + out_be32(&fecp->fec_hash_table_high, 0);
> + out_be32(&fecp->fec_hash_table_low, 0);
> #endif
>
> /* Set maximum receive buffer size.
> */
> - fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
> + out_be32(&fecp->fec_r_buff_size, PKT_MAXBLR_SIZE);
>
> /* Set maximum frame length
> */
> - fecp->fec_r_hash = PKT_MAXBUF_SIZE;
> + out_be32(&fecp->fec_r_hash, PKT_MAXBUF_SIZE);
>
> /*
> * Setup Buffers and Buffer Desriptors
> @@ -553,18 +560,19 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
> txIdx = 0;
>
> if (!rtx)
> - rtx = (RTXBD *)(immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
> + rtx = (struct common_buf_desc __iomem *)
> + (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
> /*
> * Setup Receiver Buffer Descriptors (13.14.24.18)
> * Settings:
> * Empty, Wrap
> */
> for (i = 0; i < PKTBUFSRX; i++) {
> - rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
> - rtx->rxbd[i].cbd_datlen = 0; /* Reset */
> - rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
> + out_be16(&rtx->rxbd[i].cbd_sc, BD_ENET_RX_EMPTY);
> + out_be16(&rtx->rxbd[i].cbd_datlen, 0); /* Reset */
> + out_be32(&rtx->rxbd[i].cbd_bufaddr, (uint)net_rx_packets[i]);
> }
> - rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
> + setbits_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc, BD_ENET_RX_WRAP);
>
> /*
> * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
> @@ -572,26 +580,26 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
> * Last, Tx CRC
> */
> for (i = 0; i < TX_BUF_CNT; i++) {
> - rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
> - rtx->txbd[i].cbd_datlen = 0; /* Reset */
> - rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
> + out_be16(&rtx->txbd[i].cbd_sc, BD_ENET_TX_LAST | BD_ENET_TX_TC);
> + out_be16(&rtx->txbd[i].cbd_datlen, 0); /* Reset */
> + out_be32(&rtx->txbd[i].cbd_bufaddr, (uint)txbuf);
> }
> - rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
> + setbits_be16(&rtx->txbd[TX_BUF_CNT - 1].cbd_sc, BD_ENET_TX_WRAP);
>
> /* Set receive and transmit descriptor base
> */
> - fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
> - fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
> + out_be32(&fecp->fec_r_des_start, (__force unsigned int)rtx->rxbd);
> + out_be32(&fecp->fec_x_des_start, (__force unsigned int)rtx->txbd);
>
> /* Enable MII mode
> */
> /* Half duplex mode */
> - fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
> - fecp->fec_x_cntrl = 0;
> + out_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT);
> + out_be32(&fecp->fec_x_cntrl, 0);
>
> /* Enable big endian and don't care about SDMA FC.
> */
> - fecp->fec_fun_code = 0x78000000;
> + out_be32(&fecp->fec_fun_code, 0x78000000);
>
> /*
> * Setup the pin configuration of the FEC
> @@ -604,7 +612,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
> /*
> * Now enable the transmit and receive processing
> */
> - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
> + out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
>
> if (efis->phy_addr == -1) {
> #ifdef CONFIG_SYS_DISCOVER_PHY
> @@ -647,7 +655,8 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
> #endif
>
> /* And last, try to fill Rx Buffer Descriptors */
> - fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
> + /* Descriptor polling active */
> + out_be32(&fecp->fec_r_des_active, 0x01000000);
>
> efis->initialized = 1;
>
> @@ -658,7 +667,8 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
> static void fec_halt(struct eth_device* dev)
> {
> struct ether_fcc_info_s *efis = dev->priv;
> - volatile fec_t *fecp = (volatile fec_t *)(CONFIG_SYS_IMMR + efis->fecp_offset);
> + fec_t __iomem *fecp =
> + (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
> int i;
>
> /* avoid halt if initialized; mii gets stuck otherwise */
> @@ -673,12 +683,11 @@ static void fec_halt(struct eth_device* dev)
> * still in progress.
> */
>
> - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
> - for (i = 0;
> - (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
> - ++i) {
> + out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
> + for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
> + (i < FEC_RESET_DELAY); ++i)
> udelay (1);
> - }
> +
> if (i == FEC_RESET_DELAY) {
> printf ("FEC_RESET_DELAY timeout\n");
> return;
> @@ -717,23 +726,24 @@ static uint
> mii_send(uint mii_cmd)
> {
> uint mii_reply;
> - volatile fec_t *ep;
> + fec_t __iomem *ep;
> int cnt;
> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> - ep = &(((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_fec);
> + ep = &immr->im_cpm.cp_fec;
>
> - ep->fec_mii_data = mii_cmd; /* command to phy */
> + out_be32(&ep->fec_mii_data, mii_cmd); /* command to phy */
>
> /* wait for mii complete */
> cnt = 0;
> - while (!(ep->fec_ievent & FEC_ENET_MII)) {
> + while (!(in_be32(&ep->fec_ievent) & FEC_ENET_MII)) {
> if (++cnt > 1000) {
> printf("mii_send STUCK!\n");
> break;
> }
> }
> - mii_reply = ep->fec_mii_data; /* result from phy */
> - ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
> + mii_reply = in_be32(&ep->fec_mii_data); /* result from phy */
> + out_be32(&ep->fec_ievent, FEC_ENET_MII); /* clear MII complete */
> return (mii_reply & 0xffff); /* data read from phy */
> }
> #endif
> @@ -782,23 +792,23 @@ static int mii_discover_phy(struct eth_device *dev)
> */
> static void __mii_init(void)
> {
> - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
> - volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + fec_t __iomem *fecp = &immr->im_cpm.cp_fec;
>
> if (fec_reset(fecp) < 0)
> printf ("FEC_RESET_DELAY timeout\n");
>
> /* We use strictly polling mode only
> */
> - fecp->fec_imask = 0;
> + out_be32(&fecp->fec_imask, 0);
>
> /* Clear any pending interrupt
> */
> - fecp->fec_ievent = 0xffc0;
> + out_be32(&fecp->fec_ievent, 0xffc0);
>
> /* Now enable the transmit and receive processing
> */
> - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
> + out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
> }
>
> void mii_init (void)
> diff --git a/arch/powerpc/cpu/mpc8xx/immap.c b/arch/powerpc/cpu/mpc8xx/immap.c
> index 5ff6aa5e3b..63cc664e92 100644
> --- a/arch/powerpc/cpu/mpc8xx/immap.c
> +++ b/arch/powerpc/cpu/mpc8xx/immap.c
> @@ -15,64 +15,60 @@
> #include <asm/8xx_immap.h>
> #include <commproc.h>
> #include <asm/iopin_8xx.h>
> +#include <asm/io.h>
>
> DECLARE_GLOBAL_DATA_PTR;
>
> int
> do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> {
> - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
> -
> - volatile sysconf8xx_t *sc = &immap->im_siu_conf;
> -
> - printf ("SIUMCR= %08x SYPCR = %08x\n", sc->sc_siumcr, sc->sc_sypcr);
> - printf ("SWT = %08x\n", sc->sc_swt);
> - printf ("SIPEND= %08x SIMASK= %08x\n", sc->sc_sipend, sc->sc_simask);
> - printf ("SIEL = %08x SIVEC = %08x\n", sc->sc_siel, sc->sc_sivec);
> - printf ("TESR = %08x SDCR = %08x\n", sc->sc_tesr, sc->sc_sdcr);
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + sysconf8xx_t __iomem *sc = &immap->im_siu_conf;
> +
> + printf("SIUMCR= %08x SYPCR = %08x\n",
> + in_be32(&sc->sc_siumcr), in_be32(&sc->sc_sypcr));
> + printf("SWT = %08x\n", in_be32(&sc->sc_swt));
> + printf("SIPEND= %08x SIMASK= %08x\n",
> + in_be32(&sc->sc_sipend), in_be32(&sc->sc_simask));
> + printf("SIEL = %08x SIVEC = %08x\n",
> + in_be32(&sc->sc_siel), in_be32(&sc->sc_sivec));
> + printf("TESR = %08x SDCR = %08x\n",
> + in_be32(&sc->sc_tesr), in_be32(&sc->sc_sdcr));
> return 0;
> }
>
> int
> do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> {
> - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
> -
> - volatile memctl8xx_t *memctl = &immap->im_memctl;
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + memctl8xx_t __iomem *memctl = &immap->im_memctl;
> int nbanks = 8;
> - volatile uint *p = &memctl->memc_br0;
> + uint __iomem *p = &memctl->memc_br0;
> int i;
>
> - for (i = 0; i < nbanks; i++, p += 2) {
> - if (i < 10) {
> - printf ("BR%d = %08x OR%d = %08x\n",
> - i, p[0], i, p[1]);
> - } else {
> - printf ("BR%d = %08x OR%d = %08x\n",
> - i, p[0], i, p[1]);
> - }
> - }
> -
> - printf ("MAR = %08x", memctl->memc_mar);
> - printf (" MCR = %08x\n", memctl->memc_mcr);
> - printf ("MAMR = %08x MBMR = %08x",
> - memctl->memc_mamr, memctl->memc_mbmr);
> - printf ("\nMSTAT = %04x\n", memctl->memc_mstat);
> - printf ("MPTPR = %04x MDR = %08x\n",
> - memctl->memc_mptpr, memctl->memc_mdr);
> + for (i = 0; i < nbanks; i++, p += 2)
> + printf("BR%-2d = %08x OR%-2d = %08x\n",
> + i, in_be32(p), i, in_be32(p + 1));
> +
> + printf("MAR = %08x", in_be32(&memctl->memc_mar));
> + printf(" MCR = %08x\n", in_be32(&memctl->memc_mcr));
> + printf("MAMR = %08x MBMR = %08x",
> + in_be32(&memctl->memc_mamr), in_be32(&memctl->memc_mbmr));
> + printf("\nMSTAT = %04x\n", in_be16(&memctl->memc_mstat));
> + printf("MPTPR = %04x MDR = %08x\n",
> + in_be16(&memctl->memc_mptpr), in_be32(&memctl->memc_mdr));
> return 0;
> }
>
> int
> do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> {
> - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
> -
> - volatile car8xx_t *car = &immap->im_clkrst;
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + car8xx_t __iomem *car = &immap->im_clkrst;
>
> - printf ("SCCR = %08x\n", car->car_sccr);
> - printf ("PLPRCR= %08x\n", car->car_plprcr);
> - printf ("RSR = %08x\n", car->car_rsr);
> + printf("SCCR = %08x\n", in_be32(&car->car_sccr));
> + printf("PLPRCR= %08x\n", in_be32(&car->car_plprcr));
> + printf("RSR = %08x\n", in_be32(&car->car_rsr));
> return 0;
> }
>
> @@ -130,11 +126,10 @@ static void binary (char *label, uint value, int nbits)
> int
> do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> {
> - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
> -
> - volatile iop8xx_t *iop = &immap->im_ioport;
> - volatile ushort *l, *r;
> - volatile uint *R;
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + iop8xx_t __iomem *iop = &immap->im_ioport;
> + ushort __iomem *l, *r;
> + uint __iomem *R;
>
> counter = 0;
> header ();
> @@ -145,14 +140,14 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>
> l = &iop->iop_padir;
> R = &immap->im_cpm.cp_pbdir;
> - binary ("PA_DIR", *l++, PA_NBITS);
> - binary ("PB_DIR", *R++, PB_NBITS);
> - binary ("PA_PAR", *l++, PA_NBITS);
> - binary ("PB_PAR", *R++, PB_NBITS);
> - binary ("PA_ODR", *l++, PA_NB_ODR);
> - binary ("PB_ODR", *R++, PB_NB_ODR);
> - binary ("PA_DAT", *l++, PA_NBITS);
> - binary ("PB_DAT", *R++, PB_NBITS);
> + binary("PA_DIR", in_be16(l++), PA_NBITS);
> + binary("PB_DIR", in_be32(R++), PB_NBITS);
> + binary("PA_PAR", in_be16(l++), PA_NBITS);
> + binary("PB_PAR", in_be32(R++), PB_NBITS);
> + binary("PA_ODR", in_be16(l++), PA_NB_ODR);
> + binary("PB_ODR", in_be32(R++), PB_NB_ODR);
> + binary("PA_DAT", in_be16(l++), PA_NBITS);
> + binary("PB_DAT", in_be32(R++), PB_NBITS);
>
> header ();
>
> @@ -162,16 +157,16 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>
> l = &iop->iop_pcdir;
> r = &iop->iop_pddir;
> - binary ("PC_DIR", *l++, PC_NBITS);
> - binary ("PD_DIR", *r++, PD_NBITS);
> - binary ("PC_PAR", *l++, PC_NBITS);
> - binary ("PD_PAR", *r++, PD_NBITS);
> - binary ("PC_SO ", *l++, PC_NBITS);
> - binary (" ", 0, 0);
> + binary("PC_DIR", in_be16(l++), PC_NBITS);
> + binary("PD_DIR", in_be16(r++), PD_NBITS);
> + binary("PC_PAR", in_be16(l++), PC_NBITS);
> + binary("PD_PAR", in_be16(r++), PD_NBITS);
> + binary("PC_SO ", in_be16(l++), PC_NBITS);
> + binary(" ", 0, 0);
> r++;
> - binary ("PC_DAT", *l++, PC_NBITS);
> - binary ("PD_DAT", *r++, PD_NBITS);
> - binary ("PC_INT", *l++, PC_NBITS);
> + binary("PC_DAT", in_be16(l++), PC_NBITS);
> + binary("PD_DAT", in_be16(r++), PD_NBITS);
> + binary("PC_INT", in_be16(l++), PC_NBITS);
>
> header ();
> return 0;
> @@ -343,14 +338,13 @@ static void prbrg (int n, uint val)
> int
> do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> {
> - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
> -
> - volatile cpm8xx_t *cp = &immap->im_cpm;
> - volatile uint *p = &cp->cp_brgc1;
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + cpm8xx_t __iomem *cp = &immap->im_cpm;
> + uint __iomem *p = &cp->cp_brgc1;
> int i = 1;
>
> while (i <= 4)
> - prbrg (i++, *p++);
> + prbrg(i++, in_be32(p++));
>
> return 0;
> }
> diff --git a/arch/powerpc/cpu/mpc8xx/interrupts.c b/arch/powerpc/cpu/mpc8xx/interrupts.c
> index f090ad9ecb..db6df74b5e 100644
> --- a/arch/powerpc/cpu/mpc8xx/interrupts.c
> +++ b/arch/powerpc/cpu/mpc8xx/interrupts.c
> @@ -9,6 +9,7 @@
> #include <mpc8xx.h>
> #include <mpc8xx_irq.h>
> #include <asm/processor.h>
> +#include <asm/io.h>
> #include <commproc.h>
>
> /************************************************************************/
> @@ -31,12 +32,12 @@ static void cpm_interrupt (void *regs);
>
> int interrupt_init_cpu (unsigned *decrementer_count)
> {
> - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> *decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
>
> /* disable all interrupts */
> - immr->im_siu_conf.sc_simask = 0;
> + out_be32(&immr->im_siu_conf.sc_simask, 0);
>
> /* Configure CPM interrupts */
> cpm_interrupt_init ();
> @@ -51,25 +52,24 @@ int interrupt_init_cpu (unsigned *decrementer_count)
> */
> void external_interrupt (struct pt_regs *regs)
> {
> - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
> int irq;
> - ulong simask, newmask;
> + ulong simask;
> ulong vec, v_bit;
>
> /*
> * read the SIVEC register and shift the bits down
> * to get the irq number
> */
> - vec = immr->im_siu_conf.sc_sivec;
> + vec = in_be32(&immr->im_siu_conf.sc_sivec);
> irq = vec >> 26;
> v_bit = 0x80000000UL >> irq;
>
> /*
> * Read Interrupt Mask Register and Mask Interrupts
> */
> - simask = immr->im_siu_conf.sc_simask;
> - newmask = simask & (~(0xFFFF0000 >> irq));
> - immr->im_siu_conf.sc_simask = newmask;
> + simask = in_be32(&immr->im_siu_conf.sc_simask);
> + clrbits_be32(&immr->im_siu_conf.sc_simask, 0xFFFF0000 >> irq);
>
> if (!(irq & 0x1)) { /* External Interrupt ? */
> ulong siel;
> @@ -77,13 +77,13 @@ void external_interrupt (struct pt_regs *regs)
> /*
> * Read Interrupt Edge/Level Register
> */
> - siel = immr->im_siu_conf.sc_siel;
> + siel = in_be32(&immr->im_siu_conf.sc_siel);
>
> if (siel & v_bit) { /* edge triggered interrupt ? */
> /*
> * Rewrite SIPEND Register to clear interrupt
> */
> - immr->im_siu_conf.sc_sipend = v_bit;
> + out_be32(&immr->im_siu_conf.sc_sipend, v_bit);
> }
> }
>
> @@ -98,7 +98,7 @@ void external_interrupt (struct pt_regs *regs)
> /*
> * Re-Enable old Interrupt Mask
> */
> - immr->im_siu_conf.sc_simask = simask;
> + out_be32(&immr->im_siu_conf.sc_simask, simask);
> }
>
> /************************************************************************/
> @@ -108,28 +108,28 @@ void external_interrupt (struct pt_regs *regs)
> */
> static void cpm_interrupt (void *regs)
> {
> - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
> uint vec;
>
> /*
> * Get the vector by setting the ACK bit
> * and then reading the register.
> */
> - immr->im_cpic.cpic_civr = 1;
> - vec = immr->im_cpic.cpic_civr;
> + out_be16(&immr->im_cpic.cpic_civr, 1);
> + vec = in_be16(&immr->im_cpic.cpic_civr);
> vec >>= 11;
>
> if (cpm_vecs[vec].handler != NULL) {
> (*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
> } else {
> - immr->im_cpic.cpic_cimr &= ~(1 << vec);
> + clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
> printf ("Masking bogus CPM interrupt vector 0x%x\n", vec);
> }
> /*
> * After servicing the interrupt,
> * we have to remove the status indicator.
> */
> - immr->im_cpic.cpic_cisr |= (1 << vec);
> + setbits_be32(&immr->im_cpic.cpic_cisr, 1 << vec);
> }
>
> /*
> @@ -149,7 +149,7 @@ static void cpm_error_interrupt (void *dummy)
> void irq_install_handler (int vec, interrupt_handler_t * handler,
> void *arg)
> {
> - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> if ((vec & CPMVEC_OFFSET) != 0) {
> /* CPM interrupt */
> @@ -161,7 +161,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler,
> }
> cpm_vecs[vec].handler = handler;
> cpm_vecs[vec].arg = arg;
> - immr->im_cpic.cpic_cimr |= (1 << vec);
> + setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
> } else {
> /* SIU interrupt */
> if (irq_vecs[vec].handler != NULL) {
> @@ -172,23 +172,23 @@ void irq_install_handler (int vec, interrupt_handler_t * handler,
> }
> irq_vecs[vec].handler = handler;
> irq_vecs[vec].arg = arg;
> - immr->im_siu_conf.sc_simask |= 1 << (31 - vec);
> + setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
> }
> }
>
> void irq_free_handler (int vec)
> {
> - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> if ((vec & CPMVEC_OFFSET) != 0) {
> /* CPM interrupt */
> vec &= 0xffff;
> - immr->im_cpic.cpic_cimr &= ~(1 << vec);
> + clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
> cpm_vecs[vec].handler = NULL;
> cpm_vecs[vec].arg = NULL;
> } else {
> /* SIU interrupt */
> - immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec));
> + clrbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
> irq_vecs[vec].handler = NULL;
> irq_vecs[vec].arg = NULL;
> }
> @@ -198,26 +198,25 @@ void irq_free_handler (int vec)
>
> static void cpm_interrupt_init (void)
> {
> - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + uint cicr;
>
> /*
> * Initialize the CPM interrupt controller.
> */
>
> - immr->im_cpic.cpic_cicr =
> - (CICR_SCD_SCC4 |
> - CICR_SCC_SCC3 |
> - CICR_SCB_SCC2 |
> - CICR_SCA_SCC1) | ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK;
> + cicr = CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1 |
> + ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK;
>
> - immr->im_cpic.cpic_cimr = 0;
> + out_be32(&immr->im_cpic.cpic_cicr, cicr);
> + out_be32(&immr->im_cpic.cpic_cimr, 0);
>
> /*
> * Install the error handler.
> */
> irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL);
>
> - immr->im_cpic.cpic_cicr |= CICR_IEN;
> + setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN);
>
> /*
> * Install the cpm interrupt handler
> @@ -234,10 +233,10 @@ static void cpm_interrupt_init (void)
> */
> void timer_interrupt_cpu (struct pt_regs *regs)
> {
> - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> /* Reset Timer Expired and Timers Interrupt Status */
> - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
> + out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
> __asm__ ("nop");
> /*
> Clear TEXPS (and TMIST on older chips). SPLSS (on older
> @@ -253,7 +252,7 @@ void timer_interrupt_cpu (struct pt_regs *regs)
> to itself. If a bit value should be preserved, read the
> register, ZERO the bit and write, not OR, the result back.
> */
> - immr->im_clkrst.car_plprcr = immr->im_clkrst.car_plprcr;
> + setbits_be32(&immr->im_clkrst.car_plprcr, 0);
> }
>
> /************************************************************************/
> diff --git a/arch/powerpc/cpu/mpc8xx/reginfo.c b/arch/powerpc/cpu/mpc8xx/reginfo.c
> index b5a962431e..48615cad01 100644
> --- a/arch/powerpc/cpu/mpc8xx/reginfo.c
> +++ b/arch/powerpc/cpu/mpc8xx/reginfo.c
> @@ -7,56 +7,62 @@
>
> #include <common.h>
> #include <mpc8xx.h>
> +#include <asm/io.h>
>
> void mpc8xx_reginfo(void)
> {
> - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
> - volatile memctl8xx_t *memctl = &immap->im_memctl;
> - volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
> - volatile sit8xx_t *timers = &immap->im_sit;
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + memctl8xx_t __iomem *memctl = &immap->im_memctl;
> + sysconf8xx_t __iomem *sysconf = &immap->im_siu_conf;
> + sit8xx_t __iomem *timers = &immap->im_sit;
>
> /* Hopefully more PowerPC knowledgable people will add code to display
> * other useful registers
> */
>
> printf ("\nSystem Configuration registers\n"
> -
> "\tIMMR\t0x%08X\n", get_immr(0));
>
> - printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
> - printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
> + printf("\tSIUMCR\t0x%08X", in_be32(&sysconf->sc_siumcr));
> + printf("\tSYPCR\t0x%08X\n", in_be32(&sysconf->sc_sypcr));
>
> - printf("\tSWT\t0x%08X", sysconf->sc_swt);
> - printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
> + printf("\tSWT\t0x%08X", in_be32(&sysconf->sc_swt));
> + printf("\tSWSR\t0x%04X\n", in_be16(&sysconf->sc_swsr));
>
> printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
> - sysconf->sc_sipend, sysconf->sc_simask);
> + in_be32(&sysconf->sc_sipend), in_be32(&sysconf->sc_simask));
> printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
> - sysconf->sc_siel, sysconf->sc_sivec);
> + in_be32(&sysconf->sc_siel), in_be32(&sysconf->sc_sivec));
> printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
> - sysconf->sc_tesr, sysconf->sc_sdcr);
> -
> - printf ("Memory Controller Registers\n"
> + in_be32(&sysconf->sc_tesr), in_be32(&sysconf->sc_sdcr));
>
> - "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
> - printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
> - printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
> - printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
> - printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
> - printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
> - printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
> - printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
> - printf ("\n"
> - "\tmamr\t0x%08X\tmbmr\t0x%08X \n",
> - memctl->memc_mamr, memctl->memc_mbmr );
> - printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
> - memctl->memc_mstat, memctl->memc_mptpr );
> - printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
> + printf("Memory Controller Registers\n");
> + printf("\tBR0\t0x%08X\tOR0\t0x%08X\n", in_be32(&memctl->memc_br0),
> + in_be32(&memctl->memc_or0));
> + printf("\tBR1\t0x%08X\tOR1\t0x%08X\n", in_be32(&memctl->memc_br1),
> + in_be32(&memctl->memc_or1));
> + printf("\tBR2\t0x%08X\tOR2\t0x%08X\n", in_be32(&memctl->memc_br2),
> + in_be32(&memctl->memc_or2));
> + printf("\tBR3\t0x%08X\tOR3\t0x%08X\n", in_be32(&memctl->memc_br3),
> + in_be32(&memctl->memc_or3));
> + printf("\tBR4\t0x%08X\tOR4\t0x%08X\n", in_be32(&memctl->memc_br4),
> + in_be32(&memctl->memc_or4));
> + printf("\tBR5\t0x%08X\tOR5\t0x%08X\n", in_be32(&memctl->memc_br5),
> + in_be32(&memctl->memc_or5));
> + printf("\tBR6\t0x%08X\tOR6\t0x%08X\n", in_be32(&memctl->memc_br6),
> + in_be32(&memctl->memc_or6));
> + printf("\tBR7\t0x%08X\tOR7\t0x%08X\n", in_be32(&memctl->memc_br7),
> + in_be32(&memctl->memc_or7));
> + printf("\n\tmamr\t0x%08X\tmbmr\t0x%08X\n", in_be32(&memctl->memc_mamr),
> + in_be32(&memctl->memc_mbmr));
> + printf("\tmstat\t0x%04X\tmptpr\t0x%04X\n", in_be16(&memctl->memc_mstat),
> + in_be16(&memctl->memc_mptpr));
> + printf("\tmdr\t0x%08X\n", in_be32(&memctl->memc_mdr));
>
> - printf ("\nSystem Integration Timers\n"
> - "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
> - timers->sit_tbscr, timers->sit_rtcsc);
> - printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
> + printf("\nSystem Integration Timers\n");
> + printf("\tTBSCR\t0x%04X\tRTCSC\t0x%04X\n",
> + in_be16(&timers->sit_tbscr), in_be16(&timers->sit_rtcsc));
> + printf("\tPISCR\t0x%04X\n", in_be16(&timers->sit_piscr));
>
> /*
> * May be some CPM info here?
> diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c
> index d4f1a41a1a..598ca2a7b0 100644
> --- a/arch/powerpc/cpu/mpc8xx/serial.c
> +++ b/arch/powerpc/cpu/mpc8xx/serial.c
> @@ -20,11 +20,13 @@ DECLARE_GLOBAL_DATA_PTR;
> #define SMC_INDEX 0
> #define PROFF_SMC PROFF_SMC1
> #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
> +#define IOPINS 0xc0
>
> #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
> #define SMC_INDEX 1
> #define PROFF_SMC PROFF_SMC2
> #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
> +#define IOPINS 0xc00
>
> #endif /* CONFIG_8xx_CONS_SMCx */
>
> @@ -37,15 +39,15 @@ DECLARE_GLOBAL_DATA_PTR;
> #endif
> #endif
>
> -typedef volatile struct serialbuffer {
> +struct serialbuffer {
> cbd_t rxbd; /* Rx BD */
> cbd_t txbd; /* Tx BD */
> uint rxindex; /* index for next character to read */
> - volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
> - volatile uchar txbuf; /* tx buffers */
> -} serialbuffer_t;
> + uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
> + uchar txbuf; /* tx buffers */
> +};
>
> -static void serial_setdivisor(volatile cpm8xx_t *cp)
> +static void serial_setdivisor(cpm8xx_t __iomem *cp)
> {
> int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
>
> @@ -58,11 +60,11 @@ static void serial_setdivisor(volatile cpm8xx_t *cp)
> divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
> #endif
>
> - if(divisor<=0x1000) {
> - cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
> - } else {
> - cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
> - }
> + if (divisor <= 0x1000)
> + out_be32(&cp->cp_brgc1, ((divisor - 1) << 1) | CPM_BRG_EN);
> + else
> + out_be32(&cp->cp_brgc1, ((divisor / 16 - 1) << 1) | CPM_BRG_EN |
> + CPM_BRG_DIV16);
> }
>
> /*
> @@ -72,8 +74,8 @@ static void serial_setdivisor(volatile cpm8xx_t *cp)
>
> static void smc_setbrg (void)
> {
> - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> - volatile cpm8xx_t *cp = &(im->im_cpm);
> + immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + cpm8xx_t __iomem *cp = &(im->im_cpm);
>
> /* Set up the baud rate generator.
> * See 8xx_io/commproc.c for details.
> @@ -81,117 +83,107 @@ static void smc_setbrg (void)
> * Wire BRG1 to SMCx
> */
>
> - cp->cp_simode = 0x00000000;
> + out_be32(&cp->cp_simode, 0);
>
> serial_setdivisor(cp);
> }
>
> static int smc_init (void)
> {
> - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> - volatile smc_t *sp;
> - volatile smc_uart_t *up;
> - volatile cpm8xx_t *cp = &(im->im_cpm);
> - uint dpaddr;
> - volatile serialbuffer_t *rtx;
> + immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + smc_t __iomem *sp;
> + smc_uart_t __iomem *up;
> + cpm8xx_t __iomem *cp = &(im->im_cpm);
> + struct serialbuffer __iomem *rtx;
>
> /* initialize pointers to SMC */
>
> - sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
> - up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
> + sp = cp->cp_smc + SMC_INDEX;
> + up = (smc_uart_t __iomem *)&cp->cp_dparam[PROFF_SMC];
> /* Disable relocation */
> - up->smc_rpbase = 0;
> + out_be16(&up->smc_rpbase, 0);
>
> /* Disable transmitter/receiver. */
> - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
> + clrbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
>
> /* Enable SDMA. */
> - im->im_siu_conf.sc_sdcr = 1;
> + out_be32(&im->im_siu_conf.sc_sdcr, 1);
>
> /* clear error conditions */
> #ifdef CONFIG_SYS_SDSR
> - im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
> + out_8(&im->im_sdma.sdma_sdsr, CONFIG_SYS_SDSR);
> #else
> - im->im_sdma.sdma_sdsr = 0x83;
> + out_8(&im->im_sdma.sdma_sdsr, 0x83);
> #endif
>
> /* clear SDMA interrupt mask */
> #ifdef CONFIG_SYS_SDMR
> - im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
> + out_8(&im->im_sdma.sdma_sdmr, CONFIG_SYS_SDMR);
> #else
> - im->im_sdma.sdma_sdmr = 0x00;
> + out_8(&im->im_sdma.sdma_sdmr, 0x00);
> #endif
>
> -#if defined(CONFIG_8xx_CONS_SMC1)
> - /* Use Port B for SMC1 instead of other functions. */
> - cp->cp_pbpar |= 0x000000c0;
> - cp->cp_pbdir &= ~0x000000c0;
> - cp->cp_pbodr &= ~0x000000c0;
> -#else /* CONFIG_8xx_CONS_SMC2 */
> - /* Use Port B for SMC2 instead of other functions.
> - */
> - cp->cp_pbpar |= 0x00000c00;
> - cp->cp_pbdir &= ~0x00000c00;
> - cp->cp_pbodr &= ~0x00000c00;
> -#endif
> + /* Use Port B for SMCx instead of other functions. */
> + setbits_be32(&cp->cp_pbpar, IOPINS);
> + clrbits_be32(&cp->cp_pbdir, IOPINS);
> + clrbits_be16(&cp->cp_pbodr, IOPINS);
>
> /* Set the physical address of the host memory buffers in
> * the buffer descriptors.
> */
> - dpaddr = CPM_SERIAL_BASE;
> -
> - rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr];
> + rtx = (struct serialbuffer __iomem *)&cp->cp_dpmem[CPM_SERIAL_BASE];
> /* Allocate space for two buffer descriptors in the DP ram.
> * For now, this address seems OK, but it may have to
> * change with newer versions of the firmware.
> * damm: allocating space after the two buffers for rx/tx data
> */
>
> - rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
> - rtx->rxbd.cbd_sc = 0;
> + out_be32(&rtx->rxbd.cbd_bufaddr, (__force uint)&rtx->rxbuf);
> + out_be16(&rtx->rxbd.cbd_sc, 0);
>
> - rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
> - rtx->txbd.cbd_sc = 0;
> + out_be32(&rtx->txbd.cbd_bufaddr, (__force uint)&rtx->txbuf);
> + out_be16(&rtx->txbd.cbd_sc, 0);
>
> /* Set up the uart parameters in the parameter ram. */
> - up->smc_rbase = dpaddr;
> - up->smc_tbase = dpaddr+sizeof(cbd_t);
> - up->smc_rfcr = SMC_EB;
> - up->smc_tfcr = SMC_EB;
> + out_be16(&up->smc_rbase, CPM_SERIAL_BASE);
> + out_be16(&up->smc_tbase, CPM_SERIAL_BASE + sizeof(cbd_t));
> + out_8(&up->smc_rfcr, SMC_EB);
> + out_8(&up->smc_tfcr, SMC_EB);
>
> /* Set UART mode, 8 bit, no parity, one stop.
> * Enable receive and transmit.
> */
> - sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
> + out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);
>
> /* Mask all interrupts and remove anything pending.
> */
> - sp->smc_smcm = 0;
> - sp->smc_smce = 0xff;
> + out_8(&sp->smc_smcm, 0);
> + out_8(&sp->smc_smce, 0xff);
>
> /* Set up the baud rate generator */
> smc_setbrg ();
>
> /* Make the first buffer the only buffer. */
> - rtx->txbd.cbd_sc |= BD_SC_WRAP;
> - rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
> + setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP);
> + setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
>
> /* single/multi character receive. */
> - up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
> - up->smc_maxidl = CONFIG_SYS_MAXIDLE;
> - rtx->rxindex = 0;
> + out_be16(&up->smc_mrblr, CONFIG_SYS_SMC_RXBUFLEN);
> + out_be16(&up->smc_maxidl, CONFIG_SYS_MAXIDLE);
> + out_be32(&rtx->rxindex, 0);
>
> /* Initialize Tx/Rx parameters. */
> - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
> - ;
> + while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) /* wait if cp is busy */
> + ;
>
> - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
> + out_be16(&cp->cp_cpcr,
> + mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG);
>
> - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
> - ;
> + while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) /* wait if cp is busy */
> + ;
>
> /* Enable transmitter/receiver. */
> - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
> + setbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
>
> return (0);
> }
> @@ -199,28 +191,22 @@ static int smc_init (void)
> static void
> smc_putc(const char c)
> {
> - volatile smc_uart_t *up;
> - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> - volatile cpm8xx_t *cpmp = &(im->im_cpm);
> - volatile serialbuffer_t *rtx;
> + immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + cpm8xx_t __iomem *cpmp = &(im->im_cpm);
> + struct serialbuffer __iomem *rtx;
>
> if (c == '\n')
> smc_putc ('\r');
>
> - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
> -
> - rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
> + rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
>
> /* Wait for last character to go. */
> - rtx->txbuf = c;
> - rtx->txbd.cbd_datlen = 1;
> - rtx->txbd.cbd_sc |= BD_SC_READY;
> - __asm__("eieio");
> + out_8(&rtx->txbuf, c);
> + out_be16(&rtx->txbd.cbd_datlen, 1);
> + setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);
>
> - while (rtx->txbd.cbd_sc & BD_SC_READY) {
> + while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
> WATCHDOG_RESET ();
> - __asm__("eieio");
> - }
> }
>
> static void
> @@ -234,46 +220,44 @@ smc_puts (const char *s)
> static int
> smc_getc(void)
> {
> - volatile smc_uart_t *up;
> - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> - volatile cpm8xx_t *cpmp = &(im->im_cpm);
> - volatile serialbuffer_t *rtx;
> + immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + cpm8xx_t __iomem *cpmp = &(im->im_cpm);
> + struct serialbuffer __iomem *rtx;
> unsigned char c;
> + uint rxindex;
>
> - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
> - rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
> + rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
>
> /* Wait for character to show up. */
> - while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
> + while (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
> WATCHDOG_RESET ();
>
> /* the characters are read one by one,
> * use the rxindex to know the next char to deliver
> */
> - c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex);
> - rtx->rxindex++;
> + rxindex = in_be32(&rtx->rxindex);
> + c = in_8(rtx->rxbuf + rxindex);
> + rxindex++;
>
> /* check if all char are readout, then make prepare for next receive */
> - if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
> - rtx->rxindex = 0;
> - rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
> + if (rxindex >= in_be16(&rtx->rxbd.cbd_datlen)) {
> + rxindex = 0;
> + setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY);
> }
> + out_be32(&rtx->rxindex, rxindex);
> return(c);
> }
>
> static int
> smc_tstc(void)
> {
> - volatile smc_uart_t *up;
> - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> - volatile cpm8xx_t *cpmp = &(im->im_cpm);
> - volatile serialbuffer_t *rtx;
> -
> - up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
> + immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + cpm8xx_t __iomem *cpmp = &(im->im_cpm);
> + struct serialbuffer __iomem *rtx;
>
> - rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
> + rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
>
> - return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
> + return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY);
> }
>
> struct serial_device serial_smc_device =
> diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c
> index 751c089a6d..c91427e904 100644
> --- a/arch/powerpc/cpu/mpc8xx/speed.c
> +++ b/arch/powerpc/cpu/mpc8xx/speed.c
> @@ -8,6 +8,7 @@
> #include <common.h>
> #include <mpc8xx.h>
> #include <asm/processor.h>
> +#include <asm/io.h>
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -38,8 +39,8 @@ void get_brgclk(uint sccr)
> int get_clocks (void)
> {
> uint immr = get_immr (0); /* Return full IMMR contents */
> - volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
> - uint sccr = immap->im_clkrst.car_sccr;
> + immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
> + uint sccr = in_be32(&immap->im_clkrst.car_sccr);
> /*
> * If for some reason measuring the gclk frequency won't
> * work, we return the hardwired value.
> diff --git a/arch/powerpc/cpu/mpc8xx/spi.c b/arch/powerpc/cpu/mpc8xx/spi.c
> index c7863ecd09..e7d197f968 100644
> --- a/arch/powerpc/cpu/mpc8xx/spi.c
> +++ b/arch/powerpc/cpu/mpc8xx/spi.c
> @@ -44,6 +44,9 @@
> #define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
> #endif
>
> +#define CPM_SPI_BASE_RX CPM_SPI_BASE
> +#define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t))
> +
> /* -------------------
> * Function prototypes
> * ------------------- */
> @@ -80,19 +83,13 @@ static uchar *txbuf =
> * *********************************************************************** */
> void spi_init_f (void)
> {
> - unsigned int dpaddr;
> -
> - volatile spi_t *spi;
> - volatile immap_t *immr;
> - volatile cpm8xx_t *cp;
> - volatile cbd_t *tbdf, *rbdf;
> -
> - immr = (immap_t *) CONFIG_SYS_IMMR;
> - cp = (cpm8xx_t *) &immr->im_cpm;
> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + cpm8xx_t __iomem *cp = &immr->im_cpm;
> + spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
> + cbd_t __iomem *tbdf, *rbdf;
>
> - spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
> /* Disable relocation */
> - spi->spi_rpbase = 0;
> + out_be16(&spi->spi_rpbase, 0);
>
> /* 1 */
> /* ------------------------------------------------
> @@ -107,8 +104,7 @@ void spi_init_f (void)
> * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK)
> * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM)
> * -------------------------------------------- */
> - cp->cp_pbpar |= 0x0000000E; /* set bits */
> - cp->cp_pbpar &= ~0x00000001; /* reset bit */
> + clrsetbits_be32(&cp->cp_pbpar, 0x00000001, 0x0000000E); /* set bits */
>
> /* ----------------------------------------------
> * In/Out or per. Function 0/1
> @@ -117,7 +113,7 @@ void spi_init_f (void)
> * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK
> * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM
> * ---------------------------------------------- */
> - cp->cp_pbdir |= 0x0000000F;
> + setbits_be32(&cp->cp_pbdir, 0x0000000F);
>
> /* ----------------------------------------------
> * open drain or active output
> @@ -127,29 +123,26 @@ void spi_init_f (void)
> * PBODR[31] = 0 [0x00000001] -> active output: GPIO OUT: CS for PCUE/CCM
> * ---------------------------------------------- */
>
> - cp->cp_pbodr |= 0x00000008;
> - cp->cp_pbodr &= ~0x00000007;
> + clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008);
>
> /* Initialize the parameter ram.
> * We need to make sure many things are initialized to zero
> */
> - spi->spi_rstate = 0;
> - spi->spi_rdp = 0;
> - spi->spi_rbptr = 0;
> - spi->spi_rbc = 0;
> - spi->spi_rxtmp = 0;
> - spi->spi_tstate = 0;
> - spi->spi_tdp = 0;
> - spi->spi_tbptr = 0;
> - spi->spi_tbc = 0;
> - spi->spi_txtmp = 0;
> -
> - dpaddr = CPM_SPI_BASE;
> + out_be32(&spi->spi_rstate, 0);
> + out_be32(&spi->spi_rdp, 0);
> + out_be16(&spi->spi_rbptr, 0);
> + out_be16(&spi->spi_rbc, 0);
> + out_be32(&spi->spi_rxtmp, 0);
> + out_be32(&spi->spi_tstate, 0);
> + out_be32(&spi->spi_tdp, 0);
> + out_be16(&spi->spi_tbptr, 0);
> + out_be16(&spi->spi_tbc, 0);
> + out_be32(&spi->spi_txtmp, 0);
>
> /* 3 */
> /* Set up the SPI parameters in the parameter ram */
> - spi->spi_rbase = dpaddr;
> - spi->spi_tbase = dpaddr + sizeof (cbd_t);
> + out_be16(&spi->spi_rbase, CPM_SPI_BASE_RX);
> + out_be16(&spi->spi_tbase, CPM_SPI_BASE_TX);
>
> /***********IMPORTANT******************/
>
> @@ -160,45 +153,47 @@ void spi_init_f (void)
> * is missing from the sample I2C driver. If you dont
> * initialize these pointers, the kernel hangs.
> */
> - spi->spi_rbptr = spi->spi_rbase;
> - spi->spi_tbptr = spi->spi_tbase;
> + out_be16(&spi->spi_rbptr, CPM_SPI_BASE_RX);
> + out_be16(&spi->spi_tbptr, CPM_SPI_BASE_TX);
>
> /* 4 */
> /* Init SPI Tx + Rx Parameters */
> - while (cp->cp_cpcr & CPM_CR_FLG)
> + while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
> ;
> - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | CPM_CR_FLG;
> - while (cp->cp_cpcr & CPM_CR_FLG)
> +
> + out_be16(&cp->cp_cpcr, mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) |
> + CPM_CR_FLG);
> + while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
> ;
>
> /* 5 */
> /* Set SDMA configuration register */
> - immr->im_siu_conf.sc_sdcr = 0x0001;
> + out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001);
>
> /* 6 */
> /* Set to big endian. */
> - spi->spi_tfcr = SMC_EB;
> - spi->spi_rfcr = SMC_EB;
> + out_8(&spi->spi_tfcr, SMC_EB);
> + out_8(&spi->spi_rfcr, SMC_EB);
>
> /* 7 */
> /* Set maximum receive size. */
> - spi->spi_mrblr = MAX_BUFFER;
> + out_be16(&spi->spi_mrblr, MAX_BUFFER);
>
> /* 8 + 9 */
> /* tx and rx buffer descriptors */
> - tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
> - rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];
> + tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
> + rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
>
> - tbdf->cbd_sc &= ~BD_SC_READY;
> - rbdf->cbd_sc &= ~BD_SC_EMPTY;
> + clrbits_be16(&tbdf->cbd_sc, BD_SC_READY);
> + clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY);
>
> /* Set the bd's rx and tx buffer address pointers */
> - rbdf->cbd_bufaddr = (ulong) rxbuf;
> - tbdf->cbd_bufaddr = (ulong) txbuf;
> + out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf);
> + out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf);
>
> /* 10 + 11 */
> - cp->cp_spim = 0; /* Mask all SPI events */
> - cp->cp_spie = SPI_EMASK; /* Clear all SPI events */
> + out_8(&cp->cp_spim, 0); /* Mask all SPI events */
> + out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
>
> return;
> }
> @@ -216,28 +211,24 @@ void spi_init_f (void)
> * *********************************************************************** */
> void spi_init_r (void)
> {
> - volatile cpm8xx_t *cp;
> - volatile spi_t *spi;
> - volatile immap_t *immr;
> - volatile cbd_t *tbdf, *rbdf;
> -
> - immr = (immap_t *) CONFIG_SYS_IMMR;
> - cp = (cpm8xx_t *) &immr->im_cpm;
> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + cpm8xx_t __iomem *cp = &immr->im_cpm;
> + spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
> + cbd_t __iomem *tbdf, *rbdf;
>
> - spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
> /* Disable relocation */
> - spi->spi_rpbase = 0;
> + out_be16(&spi->spi_rpbase, 0);
>
> /* tx and rx buffer descriptors */
> - tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
> - rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];
> + tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
> + rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
>
> /* Allocate memory for RX and TX buffers */
> rxbuf = (uchar *) malloc (MAX_BUFFER);
> txbuf = (uchar *) malloc (MAX_BUFFER);
>
> - rbdf->cbd_bufaddr = (ulong) rxbuf;
> - tbdf->cbd_bufaddr = (ulong) txbuf;
> + out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf);
> + out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf);
>
> return;
> }
> @@ -301,59 +292,46 @@ ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
> **************************************************************************** */
> ssize_t spi_xfer (size_t count)
> {
> - volatile immap_t *immr;
> - volatile cpm8xx_t *cp;
> - volatile spi_t *spi;
> - cbd_t *tbdf, *rbdf;
> - ushort loop;
> + immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
> + cpm8xx_t __iomem *cp = &immr->im_cpm;
> + spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
> + cbd_t __iomem *tbdf, *rbdf;
> int tm;
>
> - immr = (immap_t *) CONFIG_SYS_IMMR;
> - cp = (cpm8xx_t *) &immr->im_cpm;
> -
> - spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
> /* Disable relocation */
> - spi->spi_rpbase = 0;
> + out_be16(&spi->spi_rpbase, 0);
>
> - tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
> - rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];
> + tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
> + rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
>
> /* Set CS for device */
> - cp->cp_pbdat &= ~0x0001;
> + clrbits_be32(&cp->cp_pbdat, 0x0001);
>
> /* Setting tx bd status and data length */
> - tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP;
> - tbdf->cbd_datlen = count;
> + out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP);
> + out_be16(&tbdf->cbd_datlen, count);
>
> /* Setting rx bd status and data length */
> - rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
> - rbdf->cbd_datlen = 0; /* rx length has no significance */
> -
> - loop = cp->cp_spmode & SPMODE_LOOP;
> - cp->cp_spmode = /*SPMODE_DIV16 |*/ /* BRG/16 mode not used here */
> - loop |
> - SPMODE_REV |
> - SPMODE_MSTR |
> - SPMODE_EN |
> - SPMODE_LEN(8) | /* 8 Bits per char */
> - SPMODE_PM(0x8) ; /* medium speed */
> - cp->cp_spim = 0; /* Mask all SPI events */
> - cp->cp_spie = SPI_EMASK; /* Clear all SPI events */
> + out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
> + out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */
> +
> + clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR |
> + SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8));
> + out_8(&cp->cp_spim, 0); /* Mask all SPI events */
> + out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
>
> /* start spi transfer */
> - cp->cp_spcom |= SPI_STR; /* Start transmit */
> + setbits_8(&cp->cp_spcom, SPI_STR); /* Start transmit */
>
> /* --------------------------------
> * Wait for SPI transmit to get out
> * or time out (1 second = 1000 ms)
> * -------------------------------- */
> for (tm=0; tm<1000; ++tm) {
> - if (cp->cp_spie & SPI_TXB) { /* Tx Buffer Empty */
> + if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */
> break;
> - }
> - if ((tbdf->cbd_sc & BD_SC_READY) == 0) {
> + if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0)
> break;
> - }
> udelay (1000);
> }
> if (tm >= 1000) {
> @@ -361,7 +339,7 @@ ssize_t spi_xfer (size_t count)
> }
>
> /* Clear CS for device */
> - cp->cp_pbdat |= 0x0001;
> + setbits_be32(&cp->cp_pbdat, 0x0001);
>
> return count;
> }
> diff --git a/arch/powerpc/include/asm/iopin_8xx.h b/arch/powerpc/include/asm/iopin_8xx.h
> index 8db0fa2a1c..beca988d77 100644
> --- a/arch/powerpc/include/asm/iopin_8xx.h
> +++ b/arch/powerpc/include/asm/iopin_8xx.h
> @@ -12,6 +12,7 @@
>
> #include <linux/types.h>
> #include <asm/8xx_immap.h>
> +#include <asm/io.h>
>
> #ifdef __KERNEL__
>
> @@ -29,54 +30,72 @@ typedef struct {
> static __inline__ void
> iopin_set_high(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTA) {
> - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
> - *datp |= (1 << (15 - iopin->pin));
> + ushort __iomem *datp = &immap->im_ioport.iop_padat;
> +
> + setbits_be16(datp, 1 << (15 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTB) {
> - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
> - *datp |= (1 << (31 - iopin->pin));
> + uint __iomem *datp = &immap->im_cpm.cp_pbdat;
> +
> + setbits_be32(datp, 1 << (31 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
> - *datp |= (1 << (15 - iopin->pin));
> + ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
> +
> + setbits_be16(datp, 1 << (15 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTD) {
> - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
> - *datp |= (1 << (15 - iopin->pin));
> + ushort __iomem *datp = &immap->im_ioport.iop_pddat;
> +
> + setbits_be16(datp, 1 << (15 - iopin->pin));
> }
> }
>
> static __inline__ void
> iopin_set_low(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTA) {
> - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
> - *datp &= ~(1 << (15 - iopin->pin));
> + ushort __iomem *datp = &immap->im_ioport.iop_padat;
> +
> + clrbits_be16(datp, 1 << (15 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTB) {
> - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
> - *datp &= ~(1 << (31 - iopin->pin));
> + uint __iomem *datp = &immap->im_cpm.cp_pbdat;
> +
> + clrbits_be32(datp, 1 << (31 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
> - *datp &= ~(1 << (15 - iopin->pin));
> + ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
> +
> + clrbits_be16(datp, 1 << (15 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTD) {
> - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
> - *datp &= ~(1 << (15 - iopin->pin));
> + ushort __iomem *datp = &immap->im_ioport.iop_pddat;
> +
> + clrbits_be16(datp, 1 << (15 - iopin->pin));
> }
> }
>
> static __inline__ uint
> iopin_is_high(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTA) {
> - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
> - return (*datp >> (15 - iopin->pin)) & 1;
> + ushort __iomem *datp = &immap->im_ioport.iop_padat;
> +
> + return (in_be16(datp) >> (15 - iopin->pin)) & 1;
> } else if (iopin->port == IOPIN_PORTB) {
> - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
> - return (*datp >> (31 - iopin->pin)) & 1;
> + uint __iomem *datp = &immap->im_cpm.cp_pbdat;
> +
> + return (in_be32(datp) >> (31 - iopin->pin)) & 1;
> } else if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
> - return (*datp >> (15 - iopin->pin)) & 1;
> + ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
> +
> + return (in_be16(datp) >> (15 - iopin->pin)) & 1;
> } else if (iopin->port == IOPIN_PORTD) {
> - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
> - return (*datp >> (15 - iopin->pin)) & 1;
> + ushort __iomem *datp = &immap->im_ioport.iop_pddat;
> +
> + return (in_be16(datp) >> (15 - iopin->pin)) & 1;
> }
> return 0;
> }
> @@ -84,18 +103,24 @@ iopin_is_high(iopin_t *iopin)
> static __inline__ uint
> iopin_is_low(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTA) {
> - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
> - return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
> + ushort __iomem *datp = &immap->im_ioport.iop_padat;
> +
> + return ((in_be16(datp) >> (15 - iopin->pin)) & 1) ^ 1;
> } else if (iopin->port == IOPIN_PORTB) {
> - volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
> - return ((*datp >> (31 - iopin->pin)) & 1) ^ 1;
> + uint __iomem *datp = &immap->im_cpm.cp_pbdat;
> +
> + return ((in_be32(datp) >> (31 - iopin->pin)) & 1) ^ 1;
> } else if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
> - return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
> + ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
> +
> + return ((in_be16(datp) >> (15 - iopin->pin)) & 1) ^ 1;
> } else if (iopin->port == IOPIN_PORTD) {
> - volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
> - return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
> + ushort __iomem *datp = &immap->im_ioport.iop_pddat;
> +
> + return ((in_be16(datp) >> (15 - iopin->pin)) & 1) ^ 1;
> }
> return 0;
> }
> @@ -103,54 +128,72 @@ iopin_is_low(iopin_t *iopin)
> static __inline__ void
> iopin_set_out(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTA) {
> - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
> - *dirp |= (1 << (15 - iopin->pin));
> + ushort __iomem *dirp = &immap->im_ioport.iop_padir;
> +
> + setbits_be16(dirp, 1 << (15 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTB) {
> - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
> - *dirp |= (1 << (31 - iopin->pin));
> + uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
> +
> + setbits_be32(dirp, 1 << (31 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
> - *dirp |= (1 << (15 - iopin->pin));
> + ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
> +
> + setbits_be16(dirp, 1 << (15 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTD) {
> - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
> - *dirp |= (1 << (15 - iopin->pin));
> + ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
> +
> + setbits_be16(dirp, 1 << (15 - iopin->pin));
> }
> }
>
> static __inline__ void
> iopin_set_in(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTA) {
> - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
> - *dirp &= ~(1 << (15 - iopin->pin));
> + ushort __iomem *dirp = &immap->im_ioport.iop_padir;
> +
> + clrbits_be16(dirp, 1 << (15 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTB) {
> - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
> - *dirp &= ~(1 << (31 - iopin->pin));
> + uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
> +
> + clrbits_be32(dirp, 1 << (31 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
> - *dirp &= ~(1 << (15 - iopin->pin));
> + ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
> +
> + clrbits_be16(dirp, 1 << (15 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTD) {
> - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
> - *dirp &= ~(1 << (15 - iopin->pin));
> + ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
> +
> + clrbits_be16(dirp, 1 << (15 - iopin->pin));
> }
> }
>
> static __inline__ uint
> iopin_is_out(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTA) {
> - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
> - return (*dirp >> (15 - iopin->pin)) & 1;
> + ushort __iomem *dirp = &immap->im_ioport.iop_padir;
> +
> + return (in_be16(dirp) >> (15 - iopin->pin)) & 1;
> } else if (iopin->port == IOPIN_PORTB) {
> - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
> - return (*dirp >> (31 - iopin->pin)) & 1;
> + uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
> +
> + return (in_be32(dirp) >> (31 - iopin->pin)) & 1;
> } else if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
> - return (*dirp >> (15 - iopin->pin)) & 1;
> + ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
> +
> + return (in_be16(dirp) >> (15 - iopin->pin)) & 1;
> } else if (iopin->port == IOPIN_PORTD) {
> - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
> - return (*dirp >> (15 - iopin->pin)) & 1;
> + ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
> +
> + return (in_be16(dirp) >> (15 - iopin->pin)) & 1;
> }
> return 0;
> }
> @@ -158,18 +201,24 @@ iopin_is_out(iopin_t *iopin)
> static __inline__ uint
> iopin_is_in(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTA) {
> - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
> - return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
> + ushort __iomem *dirp = &immap->im_ioport.iop_padir;
> +
> + return ((in_be16(dirp) >> (15 - iopin->pin)) & 1) ^ 1;
> } else if (iopin->port == IOPIN_PORTB) {
> - volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
> - return ((*dirp >> (31 - iopin->pin)) & 1) ^ 1;
> + uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
> +
> + return ((in_be32(dirp) >> (31 - iopin->pin)) & 1) ^ 1;
> } else if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
> - return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
> + ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
> +
> + return ((in_be16(dirp) >> (15 - iopin->pin)) & 1) ^ 1;
> } else if (iopin->port == IOPIN_PORTD) {
> - volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
> - return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
> + ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
> +
> + return ((in_be16(dirp) >> (15 - iopin->pin)) & 1) ^ 1;
> }
> return 0;
> }
> @@ -177,36 +226,48 @@ iopin_is_in(iopin_t *iopin)
> static __inline__ void
> iopin_set_odr(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTA) {
> - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
> - *odrp |= (1 << (15 - iopin->pin));
> + ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
> +
> + setbits_be16(odrp, 1 << (15 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTB) {
> - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
> - *odrp |= (1 << (31 - iopin->pin));
> + ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
> +
> + setbits_be16(odrp, 1 << (31 - iopin->pin));
> }
> }
>
> static __inline__ void
> iopin_set_act(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTA) {
> - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
> - *odrp &= ~(1 << (15 - iopin->pin));
> + ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
> +
> + clrbits_be16(odrp, 1 << (15 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTB) {
> - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
> - *odrp &= ~(1 << (31 - iopin->pin));
> + ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
> +
> + clrbits_be16(odrp, 1 << (31 - iopin->pin));
> }
> }
>
> static __inline__ uint
> iopin_is_odr(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTA) {
> - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
> - return (*odrp >> (15 - iopin->pin)) & 1;
> + ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
> +
> + return (in_be16(odrp) >> (15 - iopin->pin)) & 1;
> } else if (iopin->port == IOPIN_PORTB) {
> - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
> - return (*odrp >> (31 - iopin->pin)) & 1;
> + ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
> +
> + return (in_be16(odrp) >> (31 - iopin->pin)) & 1;
> }
> return 0;
> }
> @@ -214,12 +275,16 @@ iopin_is_odr(iopin_t *iopin)
> static __inline__ uint
> iopin_is_act(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTA) {
> - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
> - return ((*odrp >> (15 - iopin->pin)) & 1) ^ 1;
> + ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
> +
> + return ((in_be16(odrp) >> (15 - iopin->pin)) & 1) ^ 1;
> } else if (iopin->port == IOPIN_PORTB) {
> - volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
> - return ((*odrp >> (31 - iopin->pin)) & 1) ^ 1;
> + ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
> +
> + return ((in_be16(odrp) >> (31 - iopin->pin)) & 1) ^ 1;
> }
> return 0;
> }
> @@ -227,54 +292,72 @@ iopin_is_act(iopin_t *iopin)
> static __inline__ void
> iopin_set_ded(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTA) {
> - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
> - *parp |= (1 << (15 - iopin->pin));
> + ushort __iomem *parp = &immap->im_ioport.iop_papar;
> +
> + setbits_be16(parp, 1 << (15 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTB) {
> - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
> - *parp |= (1 << (31 - iopin->pin));
> + uint __iomem *parp = &immap->im_cpm.cp_pbpar;
> +
> + setbits_be32(parp, 1 << (31 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
> - *parp |= (1 << (15 - iopin->pin));
> + ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
> +
> + setbits_be16(parp, 1 << (15 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTD) {
> - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
> - *parp |= (1 << (15 - iopin->pin));
> + ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
> +
> + setbits_be16(parp, 1 << (15 - iopin->pin));
> }
> }
>
> static __inline__ void
> iopin_set_gen(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTA) {
> - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
> - *parp &= ~(1 << (15 - iopin->pin));
> + ushort __iomem *parp = &immap->im_ioport.iop_papar;
> +
> + clrbits_be16(parp, 1 << (15 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTB) {
> - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
> - *parp &= ~(1 << (31 - iopin->pin));
> + uint __iomem *parp = &immap->im_cpm.cp_pbpar;
> +
> + clrbits_be32(parp, 1 << (31 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
> - *parp &= ~(1 << (15 - iopin->pin));
> + ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
> +
> + clrbits_be16(parp, 1 << (15 - iopin->pin));
> } else if (iopin->port == IOPIN_PORTD) {
> - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
> - *parp &= ~(1 << (15 - iopin->pin));
> + ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
> +
> + clrbits_be16(parp, 1 << (15 - iopin->pin));
> }
> }
>
> static __inline__ uint
> iopin_is_ded(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTA) {
> - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
> - return (*parp >> (15 - iopin->pin)) & 1;
> + ushort __iomem *parp = &immap->im_ioport.iop_papar;
> +
> + return (in_be16(parp) >> (15 - iopin->pin)) & 1;
> } else if (iopin->port == IOPIN_PORTB) {
> - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
> - return (*parp >> (31 - iopin->pin)) & 1;
> + uint __iomem *parp = &immap->im_cpm.cp_pbpar;
> +
> + return (in_be32(parp) >> (31 - iopin->pin)) & 1;
> } else if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
> - return (*parp >> (15 - iopin->pin)) & 1;
> + ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
> +
> + return (in_be16(parp) >> (15 - iopin->pin)) & 1;
> } else if (iopin->port == IOPIN_PORTD) {
> - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
> - return (*parp >> (15 - iopin->pin)) & 1;
> + ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
> +
> + return (in_be16(parp) >> (15 - iopin->pin)) & 1;
> }
> return 0;
> }
> @@ -282,18 +365,24 @@ iopin_is_ded(iopin_t *iopin)
> static __inline__ uint
> iopin_is_gen(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTA) {
> - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
> - return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
> + ushort __iomem *parp = &immap->im_ioport.iop_papar;
> +
> + return ((in_be16(parp) >> (15 - iopin->pin)) & 1) ^ 1;
> } else if (iopin->port == IOPIN_PORTB) {
> - volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
> - return ((*parp >> (31 - iopin->pin)) & 1) ^ 1;
> + uint __iomem *parp = &immap->im_cpm.cp_pbpar;
> +
> + return ((in_be32(parp) >> (31 - iopin->pin)) & 1) ^ 1;
> } else if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
> - return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
> + ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
> +
> + return ((in_be16(parp) >> (15 - iopin->pin)) & 1) ^ 1;
> } else if (iopin->port == IOPIN_PORTD) {
> - volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
> - return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
> + ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
> +
> + return ((in_be16(parp) >> (15 - iopin->pin)) & 1) ^ 1;
> }
> return 0;
> }
> @@ -301,27 +390,36 @@ iopin_is_gen(iopin_t *iopin)
> static __inline__ void
> iopin_set_opt2(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
> - *sorp |= (1 << (15 - iopin->pin));
> + ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
> +
> + setbits_be16(sorp, 1 << (15 - iopin->pin));
> }
> }
>
> static __inline__ void
> iopin_set_opt1(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
> - *sorp &= ~(1 << (15 - iopin->pin));
> + ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
> +
> + clrbits_be16(sorp, 1 << (15 - iopin->pin));
> }
> }
>
> static __inline__ uint
> iopin_is_opt2(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
> - return (*sorp >> (15 - iopin->pin)) & 1;
> + ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
> +
> + return (in_be16(sorp) >> (15 - iopin->pin)) & 1;
> }
> return 0;
> }
> @@ -329,9 +427,12 @@ iopin_is_opt2(iopin_t *iopin)
> static __inline__ uint
> iopin_is_opt1(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
> - return ((*sorp >> (15 - iopin->pin)) & 1) ^ 1;
> + ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
> +
> + return ((in_be16(sorp) >> (15 - iopin->pin)) & 1) ^ 1;
> }
> return 0;
> }
> @@ -339,27 +440,36 @@ iopin_is_opt1(iopin_t *iopin)
> static __inline__ void
> iopin_set_falledge(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
> - *intp |= (1 << (15 - iopin->pin));
> + ushort __iomem *intp = &immap->im_ioport.iop_pcint;
> +
> + setbits_be16(intp, 1 << (15 - iopin->pin));
> }
> }
>
> static __inline__ void
> iopin_set_anyedge(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
> - *intp &= ~(1 << (15 - iopin->pin));
> + ushort __iomem *intp = &immap->im_ioport.iop_pcint;
> +
> + clrbits_be16(intp, 1 << (15 - iopin->pin));
> }
> }
>
> static __inline__ uint
> iopin_is_falledge(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
> - return (*intp >> (15 - iopin->pin)) & 1;
> + ushort __iomem *intp = &immap->im_ioport.iop_pcint;
> +
> + return (in_be16(intp) >> (15 - iopin->pin)) & 1;
> }
> return 0;
> }
> @@ -367,9 +477,12 @@ iopin_is_falledge(iopin_t *iopin)
> static __inline__ uint
> iopin_is_anyedge(iopin_t *iopin)
> {
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> +
> if (iopin->port == IOPIN_PORTC) {
> - volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
> - return ((*intp >> (15 - iopin->pin)) & 1) ^ 1;
> + ushort __iomem *intp = &immap->im_ioport.iop_pcint;
> +
> + return ((in_be16(intp) >> (15 - iopin->pin)) & 1) ^ 1;
> }
> return 0;
> }
> diff --git a/arch/powerpc/lib/time.c b/arch/powerpc/lib/time.c
> index 4cbb65eb68..41a271a42d 100644
> --- a/arch/powerpc/lib/time.c
> +++ b/arch/powerpc/lib/time.c
> @@ -6,6 +6,7 @@
> */
>
> #include <common.h>
> +#include <asm/io.h>
>
> /* ------------------------------------------------------------------------- */
>
> @@ -65,10 +66,10 @@ int timer_init(void)
> unsigned long temp;
>
> #if defined(CONFIG_8xx)
> - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
> + immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> /* unlock */
> - immap->im_sitk.sitk_tbk = KAPWR_KEY;
> + out_be32(&immap->im_sitk.sitk_tbk, KAPWR_KEY);
> #endif
>
> /* reset */
> @@ -77,7 +78,7 @@ int timer_init(void)
>
> #if defined(CONFIG_8xx)
> /* enable */
> - immap->im_sit.sit_tbscr |= TBSCR_TBE;
> + setbits_be16(&immap->im_sit.sit_tbscr, TBSCR_TBE);
> #endif
> return (0);
> }
> diff --git a/include/watchdog.h b/include/watchdog.h
> index a3a2eeaf1b..64b59f107a 100644
> --- a/include/watchdog.h
> +++ b/include/watchdog.h
> @@ -74,7 +74,7 @@ int init_func_watchdog_reset(void);
>
> /* MPC 8xx */
> #if defined(CONFIG_8xx) && !defined(__ASSEMBLY__)
> - void reset_8xx_watchdog(volatile immap_t *immr);
> + void reset_8xx_watchdog(immap_t __iomem *immr);
> #endif
>
> #if defined(CONFIG_HW_WATCHDOG) && !defined(__ASSEMBLY__)
>
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 35+ messages in thread* [U-Boot] [U-Boot, v2, 03/10] powerpc, 8xx: Use IO accessors to access IO memory
2017-07-06 8:33 ` [U-Boot] [PATCH v2 03/10] powerpc, 8xx: Use IO accessors to access IO memory Christophe Leroy
2017-07-06 9:41 ` Heiko Schocher
@ 2017-07-09 0:24 ` Tom Rini
1 sibling, 0 replies; 35+ messages in thread
From: Tom Rini @ 2017-07-09 0:24 UTC (permalink / raw)
To: u-boot
On Thu, Jul 06, 2017 at 10:33:13AM +0200, Christophe Leroy wrote:
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> Reviewed-by: Heiko Schocher <hs@denx.de>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [U-Boot] [PATCH v2 04/10] powerpc, 8xx: Implement GLL2 ERRATA
2017-07-06 8:33 [U-Boot] [PATCH v2 0/10] powerpc, 8xx: Modernise the 8xx Christophe Leroy
` (2 preceding siblings ...)
2017-07-06 8:33 ` [U-Boot] [PATCH v2 03/10] powerpc, 8xx: Use IO accessors to access IO memory Christophe Leroy
@ 2017-07-06 8:33 ` Christophe Leroy
2017-07-06 9:43 ` Heiko Schocher
2017-07-06 10:56 ` Wolfgang Denk
2017-07-06 8:33 ` [U-Boot] [PATCH v2 05/10] powerpc, 8xx: Handle checkpatch errors and some of the warnings/checks Christophe Leroy
` (5 subsequent siblings)
9 siblings, 2 replies; 35+ messages in thread
From: Christophe Leroy @ 2017-07-06 8:33 UTC (permalink / raw)
To: u-boot
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/cpu/mpc8xx/cpu_init.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index cf1280983a..52406e8483 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -51,6 +51,14 @@ void cpu_init_f(immap_t __iomem *immr)
clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK,
CONFIG_SYS_SCCR);
+ /* BUG MPC866 GLL2 consideration */
+ reg = in_be32(&immr->im_clkrst.car_sccr);
+ /* probably we use the mode 1:2:1 */
+ if ((reg & 0x00060000) == 0x00020000) {
+ clrbits_be32(&immr->im_clkrst.car_sccr, 0x00060000);
+ setbits_be32(&immr->im_clkrst.car_sccr, 0x00020000);
+ }
+
/* PLL (CPU clock) settings (15-30) */
out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
--
2.12.0
^ permalink raw reply related [flat|nested] 35+ messages in thread* [U-Boot] [PATCH v2 04/10] powerpc, 8xx: Implement GLL2 ERRATA
2017-07-06 8:33 ` [U-Boot] [PATCH v2 04/10] powerpc, 8xx: Implement GLL2 ERRATA Christophe Leroy
@ 2017-07-06 9:43 ` Heiko Schocher
2017-07-06 10:56 ` Wolfgang Denk
1 sibling, 0 replies; 35+ messages in thread
From: Heiko Schocher @ 2017-07-06 9:43 UTC (permalink / raw)
To: u-boot
Hello Christophe,
Am 06.07.2017 um 10:33 schrieb Christophe Leroy:
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
> arch/powerpc/cpu/mpc8xx/cpu_init.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
Reviewed-by: Heiko Schocher <hs@denx.de>
nitpick only
> diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
> index cf1280983a..52406e8483 100644
> --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
> +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
> @@ -51,6 +51,14 @@ void cpu_init_f(immap_t __iomem *immr)
> clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK,
> CONFIG_SYS_SCCR);
>
> + /* BUG MPC866 GLL2 consideration */
> + reg = in_be32(&immr->im_clkrst.car_sccr);
> + /* probably we use the mode 1:2:1 */
> + if ((reg & 0x00060000) == 0x00020000) {
> + clrbits_be32(&immr->im_clkrst.car_sccr, 0x00060000);
> + setbits_be32(&immr->im_clkrst.car_sccr, 0x00020000);
You may can introduce defines for the magic values here.
> + }
> +
> /* PLL (CPU clock) settings (15-30) */
>
> out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
>
bye,
Heiko
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 35+ messages in thread* [U-Boot] [PATCH v2 04/10] powerpc, 8xx: Implement GLL2 ERRATA
2017-07-06 8:33 ` [U-Boot] [PATCH v2 04/10] powerpc, 8xx: Implement GLL2 ERRATA Christophe Leroy
2017-07-06 9:43 ` Heiko Schocher
@ 2017-07-06 10:56 ` Wolfgang Denk
2017-07-06 11:12 ` Christophe LEROY
1 sibling, 1 reply; 35+ messages in thread
From: Wolfgang Denk @ 2017-07-06 10:56 UTC (permalink / raw)
To: u-boot
Dear Christophe,
In message <466a431b5430548a018c21222080ed4040596147.1499329461.git.christophe.leroy@c-s.fr> you wrote:
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
> arch/powerpc/cpu/mpc8xx/cpu_init.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
> index cf1280983a..52406e8483 100644
> --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
> +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
> @@ -51,6 +51,14 @@ void cpu_init_f(immap_t __iomem *immr)
> clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK,
> CONFIG_SYS_SCCR);
>
> + /* BUG MPC866 GLL2 consideration */
> + reg = in_be32(&immr->im_clkrst.car_sccr);
> + /* probably we use the mode 1:2:1 */
> + if ((reg & 0x00060000) == 0x00020000) {
> + clrbits_be32(&immr->im_clkrst.car_sccr, 0x00060000);
> + setbits_be32(&immr->im_clkrst.car_sccr, 0x00020000);
> + }
Like a few lines above, you could/should use a single call to
clrsetbits_be32() here. And as Heiko already commented, please use
readable names istead of the magic numbers.
Reviewed-by: Wolfgang Denk <wd@denx.de>
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"I haven't lost my mind - it's backed up on tape somewhere."
^ permalink raw reply [flat|nested] 35+ messages in thread* [U-Boot] [PATCH v2 04/10] powerpc, 8xx: Implement GLL2 ERRATA
2017-07-06 10:56 ` Wolfgang Denk
@ 2017-07-06 11:12 ` Christophe LEROY
2017-07-06 11:18 ` Christophe LEROY
2017-07-06 11:20 ` Wolfgang Denk
0 siblings, 2 replies; 35+ messages in thread
From: Christophe LEROY @ 2017-07-06 11:12 UTC (permalink / raw)
To: u-boot
Le 06/07/2017 à 12:56, Wolfgang Denk a écrit :
> Dear Christophe,
>
> In message <466a431b5430548a018c21222080ed4040596147.1499329461.git.christophe.leroy@c-s.fr> you wrote:
>> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
>> ---
>> arch/powerpc/cpu/mpc8xx/cpu_init.c | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
>> index cf1280983a..52406e8483 100644
>> --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
>> +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
>> @@ -51,6 +51,14 @@ void cpu_init_f(immap_t __iomem *immr)
>> clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK,
>> CONFIG_SYS_SCCR);
>>
>> + /* BUG MPC866 GLL2 consideration */
>> + reg = in_be32(&immr->im_clkrst.car_sccr);
>> + /* probably we use the mode 1:2:1 */
>> + if ((reg & 0x00060000) == 0x00020000) {
>> + clrbits_be32(&immr->im_clkrst.car_sccr, 0x00060000);
>> + setbits_be32(&immr->im_clkrst.car_sccr, 0x00020000);
>> + }
>
> Like a few lines above, you could/should use a single call to
> clrsetbits_be32() here. And as Heiko already commented, please use
> readable names istead of the magic numbers.
I shall not use clrsetbits_be32(), because the ERRATA says:
Program the PLPRCR such that the PLL clock will change, then reprogram
the PLPRCR value back to the desired value
Christophe
>
> Reviewed-by: Wolfgang Denk <wd@denx.de>
>
>
> Best regards,
>
> Wolfgang Denk
>
^ permalink raw reply [flat|nested] 35+ messages in thread* [U-Boot] [PATCH v2 04/10] powerpc, 8xx: Implement GLL2 ERRATA
2017-07-06 11:12 ` Christophe LEROY
@ 2017-07-06 11:18 ` Christophe LEROY
2017-07-06 11:20 ` Wolfgang Denk
1 sibling, 0 replies; 35+ messages in thread
From: Christophe LEROY @ 2017-07-06 11:18 UTC (permalink / raw)
To: u-boot
Oops, I copied wrong alternative of the ERRATA. Correct one this time.
Le 06/07/2017 à 13:12, Christophe LEROY a écrit :
>
>
> Le 06/07/2017 à 12:56, Wolfgang Denk a écrit :
>> Dear Christophe,
>>
>> In message
>> <466a431b5430548a018c21222080ed4040596147.1499329461.git.christophe.leroy@c-s.fr>
>> you wrote:
>>> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
>>> ---
>>> arch/powerpc/cpu/mpc8xx/cpu_init.c | 8 ++++++++
>>> 1 file changed, 8 insertions(+)
>>>
>>> diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c
>>> b/arch/powerpc/cpu/mpc8xx/cpu_init.c
>>> index cf1280983a..52406e8483 100644
>>> --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
>>> +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
>>> @@ -51,6 +51,14 @@ void cpu_init_f(immap_t __iomem *immr)
>>> clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK,
>>> CONFIG_SYS_SCCR);
>>> + /* BUG MPC866 GLL2 consideration */
>>> + reg = in_be32(&immr->im_clkrst.car_sccr);
>>> + /* probably we use the mode 1:2:1 */
>>> + if ((reg & 0x00060000) == 0x00020000) {
>>> + clrbits_be32(&immr->im_clkrst.car_sccr, 0x00060000);
>>> + setbits_be32(&immr->im_clkrst.car_sccr, 0x00020000);
>>> + }
>>
>> Like a few lines above, you could/should use a single call to
>> clrsetbits_be32() here. And as Heiko already commented, please use
>> readable names istead of the magic numbers.
>
> I shall not use clrsetbits_be32(), because the ERRATA says:
The ERRATA says:
Reprogram the SCCR:
1. Write 1'b00 to SCCR[EBDF].
2. Write 1'b01 to SCCR[EBDF].
3. Rewrite the desired value to the PLPRCR register
Christophe
>
> Program the PLPRCR such that the PLL clock will change, then reprogram
> the PLPRCR value back to the desired value
>
> Christophe
>
>>
>> Reviewed-by: Wolfgang Denk <wd@denx.de>
>>
>>
>> Best regards,
>>
>> Wolfgang Denk
>>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 35+ messages in thread* [U-Boot] [PATCH v2 04/10] powerpc, 8xx: Implement GLL2 ERRATA
2017-07-06 11:12 ` Christophe LEROY
2017-07-06 11:18 ` Christophe LEROY
@ 2017-07-06 11:20 ` Wolfgang Denk
1 sibling, 0 replies; 35+ messages in thread
From: Wolfgang Denk @ 2017-07-06 11:20 UTC (permalink / raw)
To: u-boot
Dear Christophe,
In message <1e6c1b5c-2e49-6784-6d6d-f4532aa20434@c-s.fr> you wrote:
>
> > Like a few lines above, you could/should use a single call to
> > clrsetbits_be32() here. And as Heiko already commented, please use
> > readable names istead of the magic numbers.
>
> I shall not use clrsetbits_be32(), because the ERRATA says:
>
> Program the PLPRCR such that the PLL clock will change, then reprogram
> the PLPRCR value back to the desired value
Ah! This is critical information, so please add a comment to explain
this. [Otherwise there is the risk some later "optimization" intro-
duces a bug.]
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
He had been eight years upon a project for extracting sunbeams out of
cucumbers, which were to be put in vials hermetically sealed, and let
out to warm the air in raw inclement summers. - Jonathan Swift
_Gulliver's Travels_ ``A Voyage to Laputa, etc.'' ch. 5
^ permalink raw reply [flat|nested] 35+ messages in thread
* [U-Boot] [PATCH v2 05/10] powerpc, 8xx: Handle checkpatch errors and some of the warnings/checks
2017-07-06 8:33 [U-Boot] [PATCH v2 0/10] powerpc, 8xx: Modernise the 8xx Christophe Leroy
` (3 preceding siblings ...)
2017-07-06 8:33 ` [U-Boot] [PATCH v2 04/10] powerpc, 8xx: Implement GLL2 ERRATA Christophe Leroy
@ 2017-07-06 8:33 ` Christophe Leroy
2017-07-06 9:43 ` Heiko Schocher
2017-07-09 0:24 ` [U-Boot] [U-Boot, v2, " Tom Rini
2017-07-06 8:33 ` [U-Boot] [PATCH v2 06/10] powerpc, 8xx: Properly set CPM frequency in the device tree Christophe Leroy
` (4 subsequent siblings)
9 siblings, 2 replies; 35+ messages in thread
From: Christophe Leroy @ 2017-07-06 8:33 UTC (permalink / raw)
To: u-boot
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/cpu/mpc8xx/cpu.c | 123 ++++++++++++++++++-----------------
arch/powerpc/cpu/mpc8xx/cpu_init.c | 6 +-
arch/powerpc/cpu/mpc8xx/fdt.c | 8 +--
arch/powerpc/cpu/mpc8xx/fec.c | 81 +++++++++++------------
arch/powerpc/cpu/mpc8xx/immap.c | 108 ++++++++++++++----------------
arch/powerpc/cpu/mpc8xx/interrupts.c | 56 +++++++---------
arch/powerpc/cpu/mpc8xx/reginfo.c | 2 +-
arch/powerpc/cpu/mpc8xx/serial.c | 42 +++++-------
arch/powerpc/cpu/mpc8xx/speed.c | 34 +++++-----
arch/powerpc/cpu/mpc8xx/spi.c | 43 +++++-------
arch/powerpc/cpu/mpc8xx/traps.c | 37 +++++------
arch/powerpc/include/asm/iopin_8xx.h | 72 +++++++-------------
include/commproc.h | 12 ++--
13 files changed, 283 insertions(+), 341 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c
index 28cc182957..5cfc8c189c 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu.c
@@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
static char *cpu_warning = "\n " \
"*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
-static int check_CPU (long clock, uint pvr, uint immr)
+static int check_CPU(long clock, uint pvr, uint immr)
{
char *id_str =
NULL;
@@ -73,22 +73,25 @@ static int check_CPU (long clock, uint pvr, uint immr)
id_str =
"PC866x"; /* Unknown chip from MPC866 family */
break;
- case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
+ case 0x09000000:
+ pre = 'M'; mid = suf = ""; m = 1;
if (id_str == NULL)
id_str = "PC885"; /* 870/875/880/885 */
break;
- default: suf = NULL; break;
+ default:
+ suf = NULL;
+ break;
}
if (id_str == NULL)
id_str = "PC86x"; /* Unknown 86x chip */
if (suf)
- printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
+ printf("%c%s%sZPnn%s", pre, id_str, mid, suf);
else
- printf ("unknown M%s (0x%08x)", id_str, k);
+ printf("unknown M%s (0x%08x)", id_str, k);
- printf (" at %s MHz: ", strmhz (buf, clock));
+ printf(" at %s MHz: ", strmhz(buf, clock));
print_size(checkicache(), " I-Cache ");
print_size(checkdcache(), " D-Cache");
@@ -97,64 +100,63 @@ static int check_CPU (long clock, uint pvr, uint immr)
out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678);
if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
- printf (" FEC present");
+ printf(" FEC present");
- if (!m) {
- puts (cpu_warning);
- }
+ if (!m)
+ puts(cpu_warning);
- putc ('\n');
+ putc('\n');
return 0;
}
/* ------------------------------------------------------------------------- */
-int checkcpu (void)
+int checkcpu(void)
{
ulong clock = gd->cpu_clk;
- uint immr = get_immr (0); /* Return full IMMR contents */
- uint pvr = get_pvr ();
+ uint immr = get_immr(0); /* Return full IMMR contents */
+ uint pvr = get_pvr();
- puts ("CPU: ");
+ puts("CPU: ");
- return check_CPU (clock, pvr, immr);
+ return check_CPU(clock, pvr, immr);
}
/* ------------------------------------------------------------------------- */
/* L1 i-cache */
-int checkicache (void)
+int checkicache(void)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
memctl8xx_t __iomem *memctl = &immap->im_memctl;
- u32 cacheon = rd_ic_cst () & IDC_ENABLED;
+ u32 cacheon = rd_ic_cst() & IDC_ENABLED;
/* probe in flash memoryarea */
u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
u32 m;
u32 lines = -1;
- wr_ic_cst (IDC_UNALL);
- wr_ic_cst (IDC_INVALL);
- wr_ic_cst (IDC_DISABLE);
+ wr_ic_cst(IDC_UNALL);
+ wr_ic_cst(IDC_INVALL);
+ wr_ic_cst(IDC_DISABLE);
__asm__ volatile ("isync");
- while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
- wr_ic_adr (k);
- wr_ic_cst (IDC_LDLCK);
+ while (!((m = rd_ic_cst()) & IDC_CERR2)) {
+ wr_ic_adr(k);
+ wr_ic_cst(IDC_LDLCK);
__asm__ volatile ("isync");
lines++;
- k += 0x10; /* the number of bytes in a cacheline */
+ k += 0x10; /* the number of bytes in a cacheline */
}
- wr_ic_cst (IDC_UNALL);
- wr_ic_cst (IDC_INVALL);
+ wr_ic_cst(IDC_UNALL);
+ wr_ic_cst(IDC_INVALL);
if (cacheon)
- wr_ic_cst (IDC_ENABLE);
+ wr_ic_cst(IDC_ENABLE);
else
- wr_ic_cst (IDC_DISABLE);
+ wr_ic_cst(IDC_DISABLE);
__asm__ volatile ("isync");
@@ -165,41 +167,41 @@ int checkicache (void)
/* L1 d-cache */
/* call with cache disabled */
-int checkdcache (void)
+int checkdcache(void)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
memctl8xx_t __iomem *memctl = &immap->im_memctl;
- u32 cacheon = rd_dc_cst () & IDC_ENABLED;
+ u32 cacheon = rd_dc_cst() & IDC_ENABLED;
/* probe in flash memoryarea */
u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
u32 m;
u32 lines = -1;
- wr_dc_cst (IDC_UNALL);
- wr_dc_cst (IDC_INVALL);
- wr_dc_cst (IDC_DISABLE);
+ wr_dc_cst(IDC_UNALL);
+ wr_dc_cst(IDC_INVALL);
+ wr_dc_cst(IDC_DISABLE);
- while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
- wr_dc_adr (k);
- wr_dc_cst (IDC_LDLCK);
+ while (!((m = rd_dc_cst()) & IDC_CERR2)) {
+ wr_dc_adr(k);
+ wr_dc_cst(IDC_LDLCK);
lines++;
k += 0x10; /* the number of bytes in a cacheline */
}
- wr_dc_cst (IDC_UNALL);
- wr_dc_cst (IDC_INVALL);
+ wr_dc_cst(IDC_UNALL);
+ wr_dc_cst(IDC_INVALL);
if (cacheon)
- wr_dc_cst (IDC_ENABLE);
+ wr_dc_cst(IDC_ENABLE);
else
- wr_dc_cst (IDC_DISABLE);
+ wr_dc_cst(IDC_DISABLE);
return lines << 4;
};
/* ------------------------------------------------------------------------- */
-void upmconfig (uint upm, uint * table, uint size)
+void upmconfig(uint upm, uint *table, uint size)
{
uint i;
uint addr = 0;
@@ -215,7 +217,7 @@ void upmconfig (uint upm, uint * table, uint size)
/* ------------------------------------------------------------------------- */
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong msr, addr;
@@ -226,10 +228,10 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
/* Interrupts and MMU off */
__asm__ volatile ("mtspr 81, 0");
- __asm__ volatile ("mfmsr %0":"=r" (msr));
+ __asm__ volatile ("mfmsr %0" : "=r" (msr));
msr &= ~0x1030;
- __asm__ volatile ("mtmsr %0"::"r" (msr));
+ __asm__ volatile ("mtmsr %0" : : "r" (msr));
/*
* Trying to execute the next instruction@a non-existing address
@@ -239,14 +241,15 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
addr = CONFIG_SYS_RESET_ADDRESS;
#else
/*
- * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
- * - sizeof (ulong) is usually a valid address. Better pick an address
- * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
+ * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
+ * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address.
+ * Better pick an address known to be invalid on your system and assign
+ * it to CONFIG_SYS_RESET_ADDRESS.
* "(ulong)-1" used to be a good choice for many systems...
*/
- addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
+ addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
#endif
- ((void (*)(void)) addr) ();
+ ((void (*)(void)) addr)();
return 1;
}
@@ -257,14 +260,14 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
*
* See sections 14.2 and 14.6 of the User's Manual
*/
-unsigned long get_tbclk (void)
+unsigned long get_tbclk(void)
{
- uint immr = get_immr (0); /* Return full IMMR contents */
+ uint immr = get_immr(0); /* Return full IMMR contents */
immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
ulong oscclk, factor, pll;
if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
- return (gd->cpu_clk / 16);
+ return gd->cpu_clk / 16;
pll = in_be32(&immap->im_clkrst.car_plprcr);
@@ -281,28 +284,28 @@ unsigned long get_tbclk (void)
* (PDF + 1) * 2^S
*
*/
- factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
- (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
+ factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD) + 1)) /
+ (PLPRCR_val(PDF) + 1) / (1 << PLPRCR_val(S));
oscclk = gd->cpu_clk / factor;
if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
factor > 2)
- return (oscclk / 4);
+ return oscclk / 4;
- return (oscclk / 16);
+ return oscclk / 16;
}
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_WATCHDOG)
-void watchdog_reset (void)
+void watchdog_reset(void)
{
- int re_enable = disable_interrupts ();
+ int re_enable = disable_interrupts();
reset_8xx_watchdog((immap_t __iomem *)CONFIG_SYS_IMMR);
if (re_enable)
- enable_interrupts ();
+ enable_interrupts();
}
#endif /* CONFIG_WATCHDOG */
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index 52406e8483..79b12b2408 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -29,7 +29,7 @@ void cpu_init_f(immap_t __iomem *immr)
out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR);
#if defined(CONFIG_WATCHDOG)
- reset_8xx_watchdog (immr);
+ reset_8xx_watchdog(immr);
#endif /* CONFIG_WATCHDOG */
/* SIUMCR - contains debug pin configuration (11-6) */
@@ -170,7 +170,7 @@ void cpu_init_f(immap_t __iomem *immr)
/*
* initialize higher level parts of CPU like timers
*/
-int cpu_init_r (void)
+int cpu_init_r(void)
{
- return (0);
+ return 0;
}
diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c
index 34d36478d3..88ee1c502c 100644
--- a/arch/powerpc/cpu/mpc8xx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xx/fdt.c
@@ -15,13 +15,13 @@ DECLARE_GLOBAL_DATA_PTR;
void ft_cpu_setup(void *blob, bd_t *bd)
{
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "timebase-frequency", get_tbclk(), 1);
+ "timebase-frequency", get_tbclk(), 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "bus-frequency", bd->bi_busfreq, 1);
+ "bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "clock-frequency", bd->bi_intfreq, 1);
+ "clock-frequency", bd->bi_intfreq, 1);
do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
- gd->arch.brg_clk, 1);
+ gd->arch.brg_clk, 1);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index eaaea2d4e8..f2ea0d1b8a 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -102,7 +102,7 @@ static struct ether_fcc_info_s
#define PKT_MAXBLR_SIZE 1520
#ifdef __GNUC__
-static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8)));
+static char txbuf[DBUF_LENGTH] __aligned(8);
#else
#error txbuf must be aligned.
#endif
@@ -117,28 +117,27 @@ static uint txIdx; /* index of the current TX buffer */
*/
struct common_buf_desc {
- cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
- cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
+ cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
+ cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
};
static struct common_buf_desc __iomem *rtx;
static int fec_send(struct eth_device *dev, void *packet, int length);
-static int fec_recv(struct eth_device* dev);
-static int fec_init(struct eth_device* dev, bd_t * bd);
-static void fec_halt(struct eth_device* dev);
+static int fec_recv(struct eth_device *dev);
+static int fec_init(struct eth_device *dev, bd_t *bd);
+static void fec_halt(struct eth_device *dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
static void __mii_init(void);
#endif
int fec_initialize(bd_t *bis)
{
- struct eth_device* dev;
+ struct eth_device *dev;
struct ether_fcc_info_s *efis;
int i;
for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {
-
dev = malloc(sizeof(*dev));
if (dev == NULL)
hang();
@@ -147,12 +146,11 @@ int fec_initialize(bd_t *bis)
/* for FEC1 make sure that the name of the interface is the same
as the old one for compatibility reasons */
- if (i == 0) {
+ if (i == 0)
strcpy(dev->name, "FEC");
- } else {
- sprintf (dev->name, "FEC%d",
+ else
+ sprintf(dev->name, "FEC%d",
ether_fcc_info[i].ether_index + 1);
- }
efis = ðer_fcc_info[i];
@@ -202,9 +200,8 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
udelay(1);
j++;
}
- if (j>=TOUT_LOOP) {
+ if (j >= TOUT_LOOP)
printf("TX not ready\n");
- }
out_be32(&rtx->txbd[txIdx].cbd_bufaddr, (uint)packet);
out_be16(&rtx->txbd[txIdx].cbd_datlen, length);
@@ -221,9 +218,9 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
udelay(1);
j++;
}
- if (j>=TOUT_LOOP) {
+ if (j >= TOUT_LOOP)
printf("TX timeout\n");
- }
+
/* return only status bits */;
rc = in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_STATS;
@@ -232,7 +229,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
return rc;
}
-static int fec_recv (struct eth_device *dev)
+static int fec_recv(struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
fec_t __iomem *fecp =
@@ -436,7 +433,6 @@ static void fec_pin_init(int fecidx)
#endif /* CONFIG_ETHER_ON_FEC1 */
} else if (fecidx == 1) {
-
#if defined(CONFIG_ETHER_ON_FEC2)
#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
@@ -467,7 +463,6 @@ static void fec_pin_init(int fecidx)
#endif /* CONFIG_MPC885_FAMILY */
#endif /* CONFIG_ETHER_ON_FEC2 */
-
}
}
@@ -486,7 +481,7 @@ static int fec_reset(fec_t __iomem *fecp)
out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
(i < FEC_RESET_DELAY); ++i)
- udelay (1);
+ udelay(1);
if (i == FEC_RESET_DELAY)
return -1;
@@ -494,7 +489,7 @@ static int fec_reset(fec_t __iomem *fecp)
return 0;
}
-static int fec_init (struct eth_device *dev, bd_t * bd)
+static int fec_init(struct eth_device *dev, bd_t *bd)
{
struct ether_fcc_info_s *efis = dev->priv;
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -512,7 +507,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
#endif
if (fec_reset(fecp) < 0)
- printf ("FEC_RESET_DELAY timeout\n");
+ printf("FEC_RESET_DELAY timeout\n");
/* We use strictly polling mode only
*/
@@ -554,7 +549,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
out_be32(&fecp->fec_r_hash, PKT_MAXBUF_SIZE);
/*
- * Setup Buffers and Buffer Desriptors
+ * Setup Buffers and Buffer Descriptors
*/
rxIdx = 0;
txIdx = 0;
@@ -604,7 +599,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
/*
* Setup the pin configuration of the FEC
*/
- fec_pin_init (efis->ether_index);
+ fec_pin_init(efis->ether_index);
rxIdx = 0;
txIdx = 0;
@@ -619,10 +614,10 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
/*
* wait for the PHY to wake up after reset
*/
- efis->actual_phy_addr = mii_discover_phy (dev);
+ efis->actual_phy_addr = mii_discover_phy(dev);
if (efis->actual_phy_addr == -1) {
- printf ("Unable to discover phy!\n");
+ printf("Unable to discover phy!\n");
return -1;
}
#else
@@ -636,22 +631,20 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
/*
* adapt the RMII speed to the speed of the phy
*/
- if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
- fec_100Mbps (dev);
- } else {
- fec_10Mbps (dev);
- }
+ if (miiphy_speed(dev->name, efis->actual_phy_addr) == _100BASET)
+ fec_100Mbps(dev);
+ else
+ fec_10Mbps(dev);
#endif
#if defined(CONFIG_MII)
/*
* adapt to the half/full speed settings
*/
- if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
- fec_full_duplex (dev);
- } else {
- fec_half_duplex (dev);
- }
+ if (miiphy_duplex(dev->name, efis->actual_phy_addr) == FULL)
+ fec_full_duplex(dev);
+ else
+ fec_half_duplex(dev);
#endif
/* And last, try to fill Rx Buffer Descriptors */
@@ -664,7 +657,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
}
-static void fec_halt(struct eth_device* dev)
+static void fec_halt(struct eth_device *dev)
{
struct ether_fcc_info_s *efis = dev->priv;
fec_t __iomem *fecp =
@@ -686,10 +679,10 @@ static void fec_halt(struct eth_device* dev)
out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
(i < FEC_RESET_DELAY); ++i)
- udelay (1);
+ udelay(1);
if (i == FEC_RESET_DELAY) {
- printf ("FEC_RESET_DELAY timeout\n");
+ printf("FEC_RESET_DELAY timeout\n");
return;
}
@@ -744,7 +737,7 @@ mii_send(uint mii_cmd)
}
mii_reply = in_be32(&ep->fec_mii_data); /* result from phy */
out_be32(&ep->fec_ievent, FEC_ENET_MII); /* clear MII complete */
- return (mii_reply & 0xffff); /* data read from phy */
+ return mii_reply & 0xffff; /* data read from phy */
}
#endif
@@ -776,9 +769,9 @@ static int mii_discover_phy(struct eth_device *dev)
}
}
}
- if (phyaddr < 0) {
+ if (phyaddr < 0)
printf("No PHY device found.\n");
- }
+
return phyaddr;
}
#endif /* CONFIG_SYS_DISCOVER_PHY */
@@ -796,7 +789,7 @@ static void __mii_init(void)
fec_t __iomem *fecp = &immr->im_cpm.cp_fec;
if (fec_reset(fecp) < 0)
- printf ("FEC_RESET_DELAY timeout\n");
+ printf("FEC_RESET_DELAY timeout\n");
/* We use strictly polling mode only
*/
@@ -811,7 +804,7 @@ static void __mii_init(void)
out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
}
-void mii_init (void)
+void mii_init(void)
{
int i;
diff --git a/arch/powerpc/cpu/mpc8xx/immap.c b/arch/powerpc/cpu/mpc8xx/immap.c
index 63cc664e92..6da085325d 100644
--- a/arch/powerpc/cpu/mpc8xx/immap.c
+++ b/arch/powerpc/cpu/mpc8xx/immap.c
@@ -19,8 +19,7 @@
DECLARE_GLOBAL_DATA_PTR;
-int
-do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_siuinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
sysconf8xx_t __iomem *sc = &immap->im_siu_conf;
@@ -37,8 +36,7 @@ do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
-int
-do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_memcinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
memctl8xx_t __iomem *memctl = &immap->im_memctl;
@@ -60,8 +58,7 @@ do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
-int
-do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_carinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
car8xx_t __iomem *car = &immap->im_clkrst;
@@ -74,8 +71,7 @@ do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
static int counter;
-static void
-header(void)
+static void header(void)
{
char *data = "\
-------------------------------- --------------------------------\
@@ -93,27 +89,27 @@ header(void)
printf("%.79s\n", data);
}
-static void binary (char *label, uint value, int nbits)
+static void binary(char *label, uint value, int nbits)
{
uint mask = 1 << (nbits - 1);
int i, second = (counter++ % 2);
if (second)
- putc (' ');
- puts (label);
+ putc(' ');
+ puts(label);
for (i = 32 + 1; i != nbits; i--)
- putc (' ');
+ putc(' ');
while (mask != 0) {
if (value & mask)
- putc ('1');
+ putc('1');
else
- putc ('0');
+ putc('0');
mask >>= 1;
}
if (second)
- putc ('\n');
+ putc('\n');
}
#define PA_NBITS 16
@@ -123,8 +119,7 @@ static void binary (char *label, uint value, int nbits)
#define PC_NBITS 12
#define PD_NBITS 13
-int
-do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_iopinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
iop8xx_t __iomem *iop = &immap->im_ioport;
@@ -132,7 +127,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
uint __iomem *R;
counter = 0;
- header ();
+ header();
/*
* Ports A & B
@@ -149,7 +144,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
binary("PA_DAT", in_be16(l++), PA_NBITS);
binary("PB_DAT", in_be32(R++), PB_NBITS);
- header ();
+ header();
/*
* Ports C & D
@@ -168,7 +163,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
binary("PD_DAT", in_be16(r++), PD_NBITS);
binary("PC_INT", in_be16(l++), PC_NBITS);
- header ();
+ header();
return 0;
}
@@ -177,14 +172,13 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
* this needs a clean up for smaller tighter code
* use *uint and set the address based on cmd + port
*/
-int
-do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_iopset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
uint rcode = 0;
iopin_t iopin;
- static uint port = 0;
- static uint pin = 0;
- static uint value = 0;
+ static uint port;
+ static uint pin;
+ static uint value;
static enum {
DIR,
PAR,
@@ -195,7 +189,7 @@ do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
} cmd = DAT;
if (argc != 5) {
- puts ("iopset PORT PIN CMD VALUE\n");
+ puts("iopset PORT PIN CMD VALUE\n");
return 1;
}
port = argv[1][0] - 'A';
@@ -203,7 +197,7 @@ do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
port -= 0x20;
if (port > 3)
rcode = 1;
- pin = simple_strtol (argv[2], NULL, 10);
+ pin = simple_strtol(argv[2], NULL, 10);
if (pin > 31)
rcode = 1;
@@ -230,7 +224,7 @@ do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
cmd = INT;
break;
default:
- printf ("iopset: unknown command %s\n", argv[3]);
+ printf("iopset: unknown command %s\n", argv[3]);
rcode = 1;
}
if (argv[4][0] == '1')
@@ -246,47 +240,46 @@ do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
switch (cmd) {
case DIR:
if (value)
- iopin_set_out (&iopin);
+ iopin_set_out(&iopin);
else
- iopin_set_in (&iopin);
+ iopin_set_in(&iopin);
break;
case PAR:
if (value)
- iopin_set_ded (&iopin);
+ iopin_set_ded(&iopin);
else
- iopin_set_gen (&iopin);
+ iopin_set_gen(&iopin);
break;
case SOR:
if (value)
- iopin_set_opt2 (&iopin);
+ iopin_set_opt2(&iopin);
else
- iopin_set_opt1 (&iopin);
+ iopin_set_opt1(&iopin);
break;
case ODR:
if (value)
- iopin_set_odr (&iopin);
+ iopin_set_odr(&iopin);
else
- iopin_set_act (&iopin);
+ iopin_set_act(&iopin);
break;
case DAT:
if (value)
- iopin_set_high (&iopin);
+ iopin_set_high(&iopin);
else
- iopin_set_low (&iopin);
+ iopin_set_low(&iopin);
break;
case INT:
if (value)
- iopin_set_falledge (&iopin);
+ iopin_set_falledge(&iopin);
else
- iopin_set_anyedge (&iopin);
+ iopin_set_anyedge(&iopin);
break;
}
-
}
return rcode;
}
-static void prbrg (int n, uint val)
+static void prbrg(int n, uint val)
{
uint extc = (val >> 14) & 3;
uint cd = (val & CPM_BRG_CD_MASK) >> 1;
@@ -294,26 +287,26 @@ static void prbrg (int n, uint val)
ulong clock = gd->cpu_clk;
- printf ("BRG%d:", n);
+ printf("BRG%d:", n);
if (val & CPM_BRG_RST)
- puts (" RESET");
+ puts(" RESET");
else
- puts (" ");
+ puts(" ");
if (val & CPM_BRG_EN)
- puts (" ENABLED");
+ puts(" ENABLED");
else
- puts (" DISABLED");
+ puts(" DISABLED");
- printf (" EXTC=%d", extc);
+ printf(" EXTC=%d", extc);
if (val & CPM_BRG_ATB)
- puts (" ATB");
+ puts(" ATB");
else
- puts (" ");
+ puts(" ");
- printf (" DIVIDER=%4d", cd);
+ printf(" DIVIDER=%4d", cd);
if (extc == 0 && cd != 0) {
uint baudrate;
@@ -322,21 +315,20 @@ static void prbrg (int n, uint val)
else
baudrate = clock / (cd + 1);
- printf ("=%6d bps", baudrate);
+ printf("=%6d bps", baudrate);
} else {
- puts (" ");
+ puts(" ");
}
if (val & CPM_BRG_DIV16)
- puts (" DIV16");
+ puts(" DIV16");
else
- puts (" ");
+ puts(" ");
- putc ('\n');
+ putc('\n');
}
-int
-do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_brginfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cp = &immap->im_cpm;
diff --git a/arch/powerpc/cpu/mpc8xx/interrupts.c b/arch/powerpc/cpu/mpc8xx/interrupts.c
index db6df74b5e..e8e287a13f 100644
--- a/arch/powerpc/cpu/mpc8xx/interrupts.c
+++ b/arch/powerpc/cpu/mpc8xx/interrupts.c
@@ -25,24 +25,24 @@ struct interrupt_action {
static struct interrupt_action cpm_vecs[CPMVEC_NR];
static struct interrupt_action irq_vecs[NR_IRQS];
-static void cpm_interrupt_init (void);
-static void cpm_interrupt (void *regs);
+static void cpm_interrupt_init(void);
+static void cpm_interrupt(void *regs);
/************************************************************************/
-int interrupt_init_cpu (unsigned *decrementer_count)
+int interrupt_init_cpu(unsigned *decrementer_count)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
- *decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
+ *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
/* disable all interrupts */
out_be32(&immr->im_siu_conf.sc_simask, 0);
/* Configure CPM interrupts */
- cpm_interrupt_init ();
+ cpm_interrupt_init();
- return (0);
+ return 0;
}
/************************************************************************/
@@ -50,7 +50,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
/*
* Handle external interrupts
*/
-void external_interrupt (struct pt_regs *regs)
+void external_interrupt(struct pt_regs *regs)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
int irq;
@@ -88,10 +88,10 @@ void external_interrupt (struct pt_regs *regs)
}
if (irq_vecs[irq].handler != NULL) {
- irq_vecs[irq].handler (irq_vecs[irq].arg);
+ irq_vecs[irq].handler(irq_vecs[irq].arg);
} else {
- printf ("\nBogus External Interrupt IRQ %d Vector %ld\n",
- irq, vec);
+ printf("\nBogus External Interrupt IRQ %d Vector %ld\n",
+ irq, vec);
/* turn off the bogus interrupt to avoid it from now */
simask &= ~v_bit;
}
@@ -106,7 +106,7 @@ void external_interrupt (struct pt_regs *regs)
/*
* CPM interrupt handler
*/
-static void cpm_interrupt (void *regs)
+static void cpm_interrupt(void *regs)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
uint vec;
@@ -123,7 +123,7 @@ static void cpm_interrupt (void *regs)
(*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
} else {
clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
- printf ("Masking bogus CPM interrupt vector 0x%x\n", vec);
+ printf("Masking bogus CPM interrupt vector 0x%x\n", vec);
}
/*
* After servicing the interrupt,
@@ -138,7 +138,7 @@ static void cpm_interrupt (void *regs)
* to do is ACK it and return. This is a no-op function so we don't
* need any special tests in the interrupt handler.
*/
-static void cpm_error_interrupt (void *dummy)
+static void cpm_error_interrupt(void *dummy)
{
}
@@ -146,37 +146,31 @@ static void cpm_error_interrupt (void *dummy)
/*
* Install and free an interrupt handler
*/
-void irq_install_handler (int vec, interrupt_handler_t * handler,
- void *arg)
+void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
if ((vec & CPMVEC_OFFSET) != 0) {
/* CPM interrupt */
vec &= 0xffff;
- if (cpm_vecs[vec].handler != NULL) {
- printf ("CPM interrupt 0x%x replacing 0x%x\n",
- (uint) handler,
- (uint) cpm_vecs[vec].handler);
- }
+ if (cpm_vecs[vec].handler != NULL)
+ printf("CPM interrupt 0x%x replacing 0x%x\n",
+ (uint)handler, (uint)cpm_vecs[vec].handler);
cpm_vecs[vec].handler = handler;
cpm_vecs[vec].arg = arg;
setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
} else {
/* SIU interrupt */
- if (irq_vecs[vec].handler != NULL) {
- printf ("SIU interrupt %d 0x%x replacing 0x%x\n",
- vec,
- (uint) handler,
- (uint) cpm_vecs[vec].handler);
- }
+ if (irq_vecs[vec].handler != NULL)
+ printf("SIU interrupt %d 0x%x replacing 0x%x\n",
+ vec, (uint)handler, (uint)cpm_vecs[vec].handler);
irq_vecs[vec].handler = handler;
irq_vecs[vec].arg = arg;
setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
}
}
-void irq_free_handler (int vec)
+void irq_free_handler(int vec)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -196,7 +190,7 @@ void irq_free_handler (int vec)
/************************************************************************/
-static void cpm_interrupt_init (void)
+static void cpm_interrupt_init(void)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
uint cicr;
@@ -214,14 +208,14 @@ static void cpm_interrupt_init (void)
/*
* Install the error handler.
*/
- irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL);
+ irq_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL);
setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN);
/*
* Install the cpm interrupt handler
*/
- irq_install_handler (CPM_INTERRUPT, cpm_interrupt, NULL);
+ irq_install_handler(CPM_INTERRUPT, cpm_interrupt, NULL);
}
/************************************************************************/
@@ -231,7 +225,7 @@ static void cpm_interrupt_init (void)
* with interrupts disabled.
* Trivial implementation - no need to be really accurate.
*/
-void timer_interrupt_cpu (struct pt_regs *regs)
+void timer_interrupt_cpu(struct pt_regs *regs)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
diff --git a/arch/powerpc/cpu/mpc8xx/reginfo.c b/arch/powerpc/cpu/mpc8xx/reginfo.c
index 48615cad01..1ba4d22bdd 100644
--- a/arch/powerpc/cpu/mpc8xx/reginfo.c
+++ b/arch/powerpc/cpu/mpc8xx/reginfo.c
@@ -20,7 +20,7 @@ void mpc8xx_reginfo(void)
* other useful registers
*/
- printf ("\nSystem Configuration registers\n"
+ printf("\nSystem Configuration registers\n"
"\tIMMR\t0x%08X\n", get_immr(0));
printf("\tSIUMCR\t0x%08X", in_be32(&sysconf->sc_siumcr));
diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c
index 598ca2a7b0..114dfe9b4b 100644
--- a/arch/powerpc/cpu/mpc8xx/serial.c
+++ b/arch/powerpc/cpu/mpc8xx/serial.c
@@ -49,11 +49,11 @@ struct serialbuffer {
static void serial_setdivisor(cpm8xx_t __iomem *cp)
{
- int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
+ int divisor = (gd->cpu_clk + 8 * gd->baudrate) / 16 / gd->baudrate;
- if(divisor/16>0x1000) {
+ if (divisor / 16 > 0x1000) {
/* bad divisor, assume 50MHz clock and 9600 baud */
- divisor=(50*1000*1000 + 8*9600)/16/9600;
+ divisor = (50 * 1000 * 1000 + 8 * 9600) / 16 / 9600;
}
#ifdef CONFIG_SYS_BRGCLK_PRESCALE
@@ -72,7 +72,7 @@ static void serial_setdivisor(cpm8xx_t __iomem *cp)
* as serial console interface.
*/
-static void smc_setbrg (void)
+static void smc_setbrg(void)
{
immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cp = &(im->im_cpm);
@@ -88,7 +88,7 @@ static void smc_setbrg (void)
serial_setdivisor(cp);
}
-static int smc_init (void)
+static int smc_init(void)
{
immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
smc_t __iomem *sp;
@@ -161,7 +161,7 @@ static int smc_init (void)
out_8(&sp->smc_smce, 0xff);
/* Set up the baud rate generator */
- smc_setbrg ();
+ smc_setbrg();
/* Make the first buffer the only buffer. */
setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP);
@@ -185,18 +185,17 @@ static int smc_init (void)
/* Enable transmitter/receiver. */
setbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
- return (0);
+ return 0;
}
-static void
-smc_putc(const char c)
+static void smc_putc(const char c)
{
immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cpmp = &(im->im_cpm);
struct serialbuffer __iomem *rtx;
if (c == '\n')
- smc_putc ('\r');
+ smc_putc('\r');
rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
@@ -206,19 +205,16 @@ smc_putc(const char c)
setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);
while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
}
-static void
-smc_puts (const char *s)
+static void smc_puts(const char *s)
{
- while (*s) {
- smc_putc (*s++);
- }
+ while (*s)
+ smc_putc(*s++);
}
-static int
-smc_getc(void)
+static int smc_getc(void)
{
immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cpmp = &(im->im_cpm);
@@ -230,7 +226,7 @@ smc_getc(void)
/* Wait for character to show up. */
while (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
/* the characters are read one by one,
* use the rxindex to know the next char to deliver
@@ -245,11 +241,10 @@ smc_getc(void)
setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY);
}
out_be32(&rtx->rxindex, rxindex);
- return(c);
+ return c;
}
-static int
-smc_tstc(void)
+static int smc_tstc(void)
{
immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cpmp = &(im->im_cpm);
@@ -260,8 +255,7 @@ smc_tstc(void)
return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY);
}
-struct serial_device serial_smc_device =
-{
+struct serial_device serial_smc_device = {
.name = "serial_smc",
.start = smc_init,
.stop = NULL,
diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c
index c91427e904..8d43efff6c 100644
--- a/arch/powerpc/cpu/mpc8xx/speed.c
+++ b/arch/powerpc/cpu/mpc8xx/speed.c
@@ -16,29 +16,29 @@ void get_brgclk(uint sccr)
{
uint divider = 0;
- switch((sccr&SCCR_DFBRG11)>>11){
- case 0:
- divider = 1;
- break;
- case 1:
- divider = 4;
- break;
- case 2:
- divider = 16;
- break;
- case 3:
- divider = 64;
- break;
+ switch ((sccr & SCCR_DFBRG11) >> 11) {
+ case 0:
+ divider = 1;
+ break;
+ case 1:
+ divider = 4;
+ break;
+ case 2:
+ divider = 16;
+ break;
+ case 3:
+ divider = 64;
+ break;
}
- gd->arch.brg_clk = gd->cpu_clk/divider;
+ gd->arch.brg_clk = gd->cpu_clk / divider;
}
/*
* get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
*/
-int get_clocks (void)
+int get_clocks(void)
{
- uint immr = get_immr (0); /* Return full IMMR contents */
+ uint immr = get_immr(0); /* Return full IMMR contents */
immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
uint sccr = in_be32(&immap->im_clkrst.car_sccr);
/*
@@ -59,5 +59,5 @@ int get_clocks (void)
get_brgclk(sccr);
- return (0);
+ return 0;
}
diff --git a/arch/powerpc/cpu/mpc8xx/spi.c b/arch/powerpc/cpu/mpc8xx/spi.c
index e7d197f968..6e3e86fb0f 100644
--- a/arch/powerpc/cpu/mpc8xx/spi.c
+++ b/arch/powerpc/cpu/mpc8xx/spi.c
@@ -50,11 +50,7 @@
/* -------------------
* Function prototypes
* ------------------- */
-void spi_init (void);
-
-ssize_t spi_read (uchar *, int, uchar *, int);
-ssize_t spi_write (uchar *, int, uchar *, int);
-ssize_t spi_xfer (size_t);
+ssize_t spi_xfer(size_t);
/* -------------------
* Variables
@@ -66,10 +62,10 @@ ssize_t spi_xfer (size_t);
* Initially we place the RX and TX buffers at a fixed location in DPRAM!
* ---------------------------------------------------------------------- */
static uchar *rxbuf =
- (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
+ (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
[CONFIG_SYS_SPI_INIT_OFFSET];
static uchar *txbuf =
- (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
+ (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
[CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER];
/* **************************************************************************
@@ -81,7 +77,7 @@ static uchar *txbuf =
* return: ---
*
* *********************************************************************** */
-void spi_init_f (void)
+void spi_init_f(void)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cp = &immr->im_cpm;
@@ -120,7 +116,7 @@ void spi_init_f (void)
* PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
* PBODR[29] = 0 [0x00000004] -> active output SPIMOSI
* PBODR[30] = 0 [0x00000002] -> active output: SPICLK
- * PBODR[31] = 0 [0x00000001] -> active output: GPIO OUT: CS for PCUE/CCM
+ * PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM
* ---------------------------------------------- */
clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008);
@@ -209,7 +205,7 @@ void spi_init_f (void)
* return: ---
*
* *********************************************************************** */
-void spi_init_r (void)
+void spi_init_r(void)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cp = &immr->im_cpm;
@@ -224,8 +220,8 @@ void spi_init_r (void)
rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
/* Allocate memory for RX and TX buffers */
- rxbuf = (uchar *) malloc (MAX_BUFFER);
- txbuf = (uchar *) malloc (MAX_BUFFER);
+ rxbuf = (uchar *)malloc(MAX_BUFFER);
+ txbuf = (uchar *)malloc(MAX_BUFFER);
out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf);
out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf);
@@ -236,7 +232,7 @@ void spi_init_r (void)
/****************************************************************************
* Function: spi_write
**************************************************************************** */
-ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
+ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
{
int i;
@@ -253,14 +249,12 @@ ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
*txbuf = SPI_EEPROM_RDSR; /* read status */
txbuf[1] = 0;
spi_xfer(2);
- if (!(rxbuf[1] & 1)) {
+ if (!(rxbuf[1] & 1))
break;
- }
udelay(1000);
}
- if (i >= 1000) {
- printf ("*** spi_write: Time out while writing!\n");
- }
+ if (i >= 1000)
+ printf("*** spi_write: Time out while writing!\n");
return len;
}
@@ -268,7 +262,7 @@ ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
/****************************************************************************
* Function: spi_read
**************************************************************************** */
-ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
+ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
{
memset(rxbuf, 0, MAX_BUFFER);
memset(txbuf, 0, MAX_BUFFER);
@@ -290,7 +284,7 @@ ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
/****************************************************************************
* Function: spi_xfer
**************************************************************************** */
-ssize_t spi_xfer (size_t count)
+ssize_t spi_xfer(size_t count)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
cpm8xx_t __iomem *cp = &immr->im_cpm;
@@ -327,16 +321,15 @@ ssize_t spi_xfer (size_t count)
* Wait for SPI transmit to get out
* or time out (1 second = 1000 ms)
* -------------------------------- */
- for (tm=0; tm<1000; ++tm) {
+ for (tm = 0; tm < 1000; ++tm) {
if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */
break;
if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0)
break;
- udelay (1000);
- }
- if (tm >= 1000) {
- printf ("*** spi_xfer: Time out while xferring to/from SPI!\n");
+ udelay(1000);
}
+ if (tm >= 1000)
+ printf("*** spi_xfer: Time out while xferring to/from SPI!\n");
/* Clear CS for device */
setbits_be32(&cp->cp_pbdat, 0x0001);
diff --git a/arch/powerpc/cpu/mpc8xx/traps.c b/arch/powerpc/cpu/mpc8xx/traps.c
index ec283d83fa..8b8d617eed 100644
--- a/arch/powerpc/cpu/mpc8xx/traps.c
+++ b/arch/powerpc/cpu/mpc8xx/traps.c
@@ -45,7 +45,8 @@ static void print_backtrace(unsigned long *sp)
if (cnt++ % 7 == 0)
printf("\n");
printf("%08lX ", i);
- if (cnt > 32) break;
+ if (cnt > 32)
+ break;
sp = (unsigned long *)*sp;
}
printf("\n");
@@ -58,23 +59,19 @@ void show_regs(struct pt_regs *regs)
printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
- regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
- regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
- regs->msr&MSR_IR ? 1 : 0,
- regs->msr&MSR_DR ? 1 : 0);
+ regs->msr, regs->msr & MSR_EE ? 1 : 0,
+ regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0,
+ regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0,
+ regs->msr & MSR_DR ? 1 : 0);
printf("\n");
for (i = 0; i < 32; i++) {
if ((i % 8) == 0)
- {
printf("GPR%02d: ", i);
- }
printf("%08lX ", regs->gpr[i]);
if ((i % 8) == 7)
- {
printf("\n");
- }
}
}
@@ -83,37 +80,37 @@ static void _exception(int signr, struct pt_regs *regs)
{
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
+ panic("Exception in kernel pc %lx signal %d", regs->nip, signr);
}
void MachineCheckException(struct pt_regs *regs)
{
- unsigned long fixup;
+ unsigned long fixup = search_exception_table(regs->nip);
/* Probing PCI using config cycles cause this exception
* when a device is not present. Catch it and return to
* the PCI exception handler.
*/
- if ((fixup = search_exception_table(regs->nip)) != 0) {
+ if (fixup != 0) {
regs->nip = fixup;
return;
}
printf("Machine check in kernel mode.\n");
printf("Caused by (from msr): ");
- printf("regs %p ",regs);
- switch( regs->msr & 0x000F0000) {
- case (0x80000000>>12):
+ printf("regs %p ", regs);
+ switch (regs->msr & 0x000F0000) {
+ case (0x80000000 >> 12):
printf("Machine check signal - probably due to mm fault\n"
"with mmu off\n");
break;
- case (0x80000000>>13):
+ case (0x80000000 >> 13):
printf("Transfer error ack signal\n");
break;
- case (0x80000000>>14):
+ case (0x80000000 >> 14):
printf("Data parity signal\n");
break;
- case (0x80000000>>15):
+ case (0x80000000 >> 15):
printf("Address parity signal\n");
break;
default:
@@ -155,8 +152,8 @@ void UnknownException(struct pt_regs *regs)
void DebugException(struct pt_regs *regs)
{
- printf("Debugger trap at @ %lx\n", regs->nip );
- show_regs(regs);
+ printf("Debugger trap at @ %lx\n", regs->nip);
+ show_regs(regs);
}
/* Probe an address by reading. If not present, return -1, otherwise
diff --git a/arch/powerpc/include/asm/iopin_8xx.h b/arch/powerpc/include/asm/iopin_8xx.h
index beca988d77..15679a2db5 100644
--- a/arch/powerpc/include/asm/iopin_8xx.h
+++ b/arch/powerpc/include/asm/iopin_8xx.h
@@ -27,8 +27,7 @@ typedef struct {
#define IOPIN_PORTC 2
#define IOPIN_PORTD 3
-static __inline__ void
-iopin_set_high(iopin_t *iopin)
+static inline void iopin_set_high(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -51,8 +50,7 @@ iopin_set_high(iopin_t *iopin)
}
}
-static __inline__ void
-iopin_set_low(iopin_t *iopin)
+static inline void iopin_set_low(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -75,8 +73,7 @@ iopin_set_low(iopin_t *iopin)
}
}
-static __inline__ uint
-iopin_is_high(iopin_t *iopin)
+static inline uint iopin_is_high(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -100,8 +97,7 @@ iopin_is_high(iopin_t *iopin)
return 0;
}
-static __inline__ uint
-iopin_is_low(iopin_t *iopin)
+static inline uint iopin_is_low(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -125,8 +121,7 @@ iopin_is_low(iopin_t *iopin)
return 0;
}
-static __inline__ void
-iopin_set_out(iopin_t *iopin)
+static inline void iopin_set_out(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -149,8 +144,7 @@ iopin_set_out(iopin_t *iopin)
}
}
-static __inline__ void
-iopin_set_in(iopin_t *iopin)
+static inline void iopin_set_in(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -173,8 +167,7 @@ iopin_set_in(iopin_t *iopin)
}
}
-static __inline__ uint
-iopin_is_out(iopin_t *iopin)
+static inline uint iopin_is_out(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -198,8 +191,7 @@ iopin_is_out(iopin_t *iopin)
return 0;
}
-static __inline__ uint
-iopin_is_in(iopin_t *iopin)
+static inline uint iopin_is_in(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -223,8 +215,7 @@ iopin_is_in(iopin_t *iopin)
return 0;
}
-static __inline__ void
-iopin_set_odr(iopin_t *iopin)
+static inline void iopin_set_odr(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -239,8 +230,7 @@ iopin_set_odr(iopin_t *iopin)
}
}
-static __inline__ void
-iopin_set_act(iopin_t *iopin)
+static inline void iopin_set_act(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -255,8 +245,7 @@ iopin_set_act(iopin_t *iopin)
}
}
-static __inline__ uint
-iopin_is_odr(iopin_t *iopin)
+static inline uint iopin_is_odr(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -272,8 +261,7 @@ iopin_is_odr(iopin_t *iopin)
return 0;
}
-static __inline__ uint
-iopin_is_act(iopin_t *iopin)
+static inline uint iopin_is_act(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -289,8 +277,7 @@ iopin_is_act(iopin_t *iopin)
return 0;
}
-static __inline__ void
-iopin_set_ded(iopin_t *iopin)
+static inline void iopin_set_ded(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -313,8 +300,7 @@ iopin_set_ded(iopin_t *iopin)
}
}
-static __inline__ void
-iopin_set_gen(iopin_t *iopin)
+static inline void iopin_set_gen(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -337,8 +323,7 @@ iopin_set_gen(iopin_t *iopin)
}
}
-static __inline__ uint
-iopin_is_ded(iopin_t *iopin)
+static inline uint iopin_is_ded(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -362,8 +347,7 @@ iopin_is_ded(iopin_t *iopin)
return 0;
}
-static __inline__ uint
-iopin_is_gen(iopin_t *iopin)
+static inline uint iopin_is_gen(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -387,8 +371,7 @@ iopin_is_gen(iopin_t *iopin)
return 0;
}
-static __inline__ void
-iopin_set_opt2(iopin_t *iopin)
+static inline void iopin_set_opt2(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -399,8 +382,7 @@ iopin_set_opt2(iopin_t *iopin)
}
}
-static __inline__ void
-iopin_set_opt1(iopin_t *iopin)
+static inline void iopin_set_opt1(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -411,8 +393,7 @@ iopin_set_opt1(iopin_t *iopin)
}
}
-static __inline__ uint
-iopin_is_opt2(iopin_t *iopin)
+static inline uint iopin_is_opt2(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -424,8 +405,7 @@ iopin_is_opt2(iopin_t *iopin)
return 0;
}
-static __inline__ uint
-iopin_is_opt1(iopin_t *iopin)
+static inline uint iopin_is_opt1(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -437,8 +417,7 @@ iopin_is_opt1(iopin_t *iopin)
return 0;
}
-static __inline__ void
-iopin_set_falledge(iopin_t *iopin)
+static inline void iopin_set_falledge(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -449,8 +428,7 @@ iopin_set_falledge(iopin_t *iopin)
}
}
-static __inline__ void
-iopin_set_anyedge(iopin_t *iopin)
+static inline void iopin_set_anyedge(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -461,8 +439,7 @@ iopin_set_anyedge(iopin_t *iopin)
}
}
-static __inline__ uint
-iopin_is_falledge(iopin_t *iopin)
+static inline uint iopin_is_falledge(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@@ -474,8 +451,7 @@ iopin_is_falledge(iopin_t *iopin)
return 0;
}
-static __inline__ uint
-iopin_is_anyedge(iopin_t *iopin)
+static inline uint iopin_is_anyedge(iopin_t *iopin)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
diff --git a/include/commproc.h b/include/commproc.h
index 5518cb325d..9536b135dc 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -7,7 +7,7 @@
*
* This file contains structures and information for the communication
* processor channels. Some CPM control and status is available
- * throught the MPC8xx internal memory map. See immap.h for details.
+ * through the MPC8xx internal memory map. See immap.h for details.
* This file only contains what I need for the moment, not the total
* CPM capabilities. I (or someone else) will add definitions as they
* are needed. -- Dan
@@ -81,7 +81,7 @@ typedef struct cpm_buf_desc {
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
-#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
+#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
#define BD_SC_BR ((ushort)0x0020) /* Break received */
@@ -582,8 +582,8 @@ typedef struct spi {
#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
-#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
-#define SPMODE_PM(x) ((x) &0xF)
+#define SPMODE_LEN(x) ((((x) - 1) & 0xF) << 4)
+#define SPMODE_PM(x) ((x) & 0xF)
/* HDLC parameter RAM.
*/
@@ -672,7 +672,7 @@ typedef struct hdlc_pram_s {
#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
-extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
+void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
/* CPM interrupt configuration vector.
*/
@@ -680,7 +680,7 @@ extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
-#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
+#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
#define CICR_IEN ((uint)0x00000080) /* Int. enable */
#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
--
2.12.0
^ permalink raw reply related [flat|nested] 35+ messages in thread* [U-Boot] [PATCH v2 05/10] powerpc, 8xx: Handle checkpatch errors and some of the warnings/checks
2017-07-06 8:33 ` [U-Boot] [PATCH v2 05/10] powerpc, 8xx: Handle checkpatch errors and some of the warnings/checks Christophe Leroy
@ 2017-07-06 9:43 ` Heiko Schocher
2017-07-09 0:24 ` [U-Boot] [U-Boot, v2, " Tom Rini
1 sibling, 0 replies; 35+ messages in thread
From: Heiko Schocher @ 2017-07-06 9:43 UTC (permalink / raw)
To: u-boot
Hello Christophe,
Am 06.07.2017 um 10:33 schrieb Christophe Leroy:
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
> arch/powerpc/cpu/mpc8xx/cpu.c | 123 ++++++++++++++++++-----------------
> arch/powerpc/cpu/mpc8xx/cpu_init.c | 6 +-
> arch/powerpc/cpu/mpc8xx/fdt.c | 8 +--
> arch/powerpc/cpu/mpc8xx/fec.c | 81 +++++++++++------------
> arch/powerpc/cpu/mpc8xx/immap.c | 108 ++++++++++++++----------------
> arch/powerpc/cpu/mpc8xx/interrupts.c | 56 +++++++---------
> arch/powerpc/cpu/mpc8xx/reginfo.c | 2 +-
> arch/powerpc/cpu/mpc8xx/serial.c | 42 +++++-------
> arch/powerpc/cpu/mpc8xx/speed.c | 34 +++++-----
> arch/powerpc/cpu/mpc8xx/spi.c | 43 +++++-------
> arch/powerpc/cpu/mpc8xx/traps.c | 37 +++++------
> arch/powerpc/include/asm/iopin_8xx.h | 72 +++++++-------------
> include/commproc.h | 12 ++--
> 13 files changed, 283 insertions(+), 341 deletions(-)
Reviewed-by: Heiko Schocher <hs@denx.de>
bye,
Heiko
>
> diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c
> index 28cc182957..5cfc8c189c 100644
> --- a/arch/powerpc/cpu/mpc8xx/cpu.c
> +++ b/arch/powerpc/cpu/mpc8xx/cpu.c
> @@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
> static char *cpu_warning = "\n " \
> "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
>
> -static int check_CPU (long clock, uint pvr, uint immr)
> +static int check_CPU(long clock, uint pvr, uint immr)
> {
> char *id_str =
> NULL;
> @@ -73,22 +73,25 @@ static int check_CPU (long clock, uint pvr, uint immr)
> id_str =
> "PC866x"; /* Unknown chip from MPC866 family */
> break;
> - case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
> + case 0x09000000:
> + pre = 'M'; mid = suf = ""; m = 1;
> if (id_str == NULL)
> id_str = "PC885"; /* 870/875/880/885 */
> break;
>
> - default: suf = NULL; break;
> + default:
> + suf = NULL;
> + break;
> }
>
> if (id_str == NULL)
> id_str = "PC86x"; /* Unknown 86x chip */
> if (suf)
> - printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
> + printf("%c%s%sZPnn%s", pre, id_str, mid, suf);
> else
> - printf ("unknown M%s (0x%08x)", id_str, k);
> + printf("unknown M%s (0x%08x)", id_str, k);
>
> - printf (" at %s MHz: ", strmhz (buf, clock));
> + printf(" at %s MHz: ", strmhz(buf, clock));
>
> print_size(checkicache(), " I-Cache ");
> print_size(checkdcache(), " D-Cache");
> @@ -97,64 +100,63 @@ static int check_CPU (long clock, uint pvr, uint immr)
>
> out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678);
> if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
> - printf (" FEC present");
> + printf(" FEC present");
>
> - if (!m) {
> - puts (cpu_warning);
> - }
> + if (!m)
> + puts(cpu_warning);
>
> - putc ('\n');
> + putc('\n');
>
> return 0;
> }
>
> /* ------------------------------------------------------------------------- */
>
> -int checkcpu (void)
> +int checkcpu(void)
> {
> ulong clock = gd->cpu_clk;
> - uint immr = get_immr (0); /* Return full IMMR contents */
> - uint pvr = get_pvr ();
> + uint immr = get_immr(0); /* Return full IMMR contents */
> + uint pvr = get_pvr();
>
> - puts ("CPU: ");
> + puts("CPU: ");
>
> - return check_CPU (clock, pvr, immr);
> + return check_CPU(clock, pvr, immr);
> }
>
> /* ------------------------------------------------------------------------- */
> /* L1 i-cache */
>
> -int checkicache (void)
> +int checkicache(void)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> memctl8xx_t __iomem *memctl = &immap->im_memctl;
> - u32 cacheon = rd_ic_cst () & IDC_ENABLED;
> + u32 cacheon = rd_ic_cst() & IDC_ENABLED;
> /* probe in flash memoryarea */
> u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
> u32 m;
> u32 lines = -1;
>
> - wr_ic_cst (IDC_UNALL);
> - wr_ic_cst (IDC_INVALL);
> - wr_ic_cst (IDC_DISABLE);
> + wr_ic_cst(IDC_UNALL);
> + wr_ic_cst(IDC_INVALL);
> + wr_ic_cst(IDC_DISABLE);
> __asm__ volatile ("isync");
>
> - while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
> - wr_ic_adr (k);
> - wr_ic_cst (IDC_LDLCK);
> + while (!((m = rd_ic_cst()) & IDC_CERR2)) {
> + wr_ic_adr(k);
> + wr_ic_cst(IDC_LDLCK);
> __asm__ volatile ("isync");
>
> lines++;
> - k += 0x10; /* the number of bytes in a cacheline */
> + k += 0x10; /* the number of bytes in a cacheline */
> }
>
> - wr_ic_cst (IDC_UNALL);
> - wr_ic_cst (IDC_INVALL);
> + wr_ic_cst(IDC_UNALL);
> + wr_ic_cst(IDC_INVALL);
>
> if (cacheon)
> - wr_ic_cst (IDC_ENABLE);
> + wr_ic_cst(IDC_ENABLE);
> else
> - wr_ic_cst (IDC_DISABLE);
> + wr_ic_cst(IDC_DISABLE);
>
> __asm__ volatile ("isync");
>
> @@ -165,41 +167,41 @@ int checkicache (void)
> /* L1 d-cache */
> /* call with cache disabled */
>
> -int checkdcache (void)
> +int checkdcache(void)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> memctl8xx_t __iomem *memctl = &immap->im_memctl;
> - u32 cacheon = rd_dc_cst () & IDC_ENABLED;
> + u32 cacheon = rd_dc_cst() & IDC_ENABLED;
> /* probe in flash memoryarea */
> u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
> u32 m;
> u32 lines = -1;
>
> - wr_dc_cst (IDC_UNALL);
> - wr_dc_cst (IDC_INVALL);
> - wr_dc_cst (IDC_DISABLE);
> + wr_dc_cst(IDC_UNALL);
> + wr_dc_cst(IDC_INVALL);
> + wr_dc_cst(IDC_DISABLE);
>
> - while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
> - wr_dc_adr (k);
> - wr_dc_cst (IDC_LDLCK);
> + while (!((m = rd_dc_cst()) & IDC_CERR2)) {
> + wr_dc_adr(k);
> + wr_dc_cst(IDC_LDLCK);
> lines++;
> k += 0x10; /* the number of bytes in a cacheline */
> }
>
> - wr_dc_cst (IDC_UNALL);
> - wr_dc_cst (IDC_INVALL);
> + wr_dc_cst(IDC_UNALL);
> + wr_dc_cst(IDC_INVALL);
>
> if (cacheon)
> - wr_dc_cst (IDC_ENABLE);
> + wr_dc_cst(IDC_ENABLE);
> else
> - wr_dc_cst (IDC_DISABLE);
> + wr_dc_cst(IDC_DISABLE);
>
> return lines << 4;
> };
>
> /* ------------------------------------------------------------------------- */
>
> -void upmconfig (uint upm, uint * table, uint size)
> +void upmconfig(uint upm, uint *table, uint size)
> {
> uint i;
> uint addr = 0;
> @@ -215,7 +217,7 @@ void upmconfig (uint upm, uint * table, uint size)
>
> /* ------------------------------------------------------------------------- */
>
> -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> {
> ulong msr, addr;
>
> @@ -226,10 +228,10 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>
> /* Interrupts and MMU off */
> __asm__ volatile ("mtspr 81, 0");
> - __asm__ volatile ("mfmsr %0":"=r" (msr));
> + __asm__ volatile ("mfmsr %0" : "=r" (msr));
>
> msr &= ~0x1030;
> - __asm__ volatile ("mtmsr %0"::"r" (msr));
> + __asm__ volatile ("mtmsr %0" : : "r" (msr));
>
> /*
> * Trying to execute the next instruction at a non-existing address
> @@ -239,14 +241,15 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> addr = CONFIG_SYS_RESET_ADDRESS;
> #else
> /*
> - * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
> - * - sizeof (ulong) is usually a valid address. Better pick an address
> - * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
> + * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
> + * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address.
> + * Better pick an address known to be invalid on your system and assign
> + * it to CONFIG_SYS_RESET_ADDRESS.
> * "(ulong)-1" used to be a good choice for many systems...
> */
> - addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
> + addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
> #endif
> - ((void (*)(void)) addr) ();
> + ((void (*)(void)) addr)();
> return 1;
> }
>
> @@ -257,14 +260,14 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> *
> * See sections 14.2 and 14.6 of the User's Manual
> */
> -unsigned long get_tbclk (void)
> +unsigned long get_tbclk(void)
> {
> - uint immr = get_immr (0); /* Return full IMMR contents */
> + uint immr = get_immr(0); /* Return full IMMR contents */
> immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
> ulong oscclk, factor, pll;
>
> if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
> - return (gd->cpu_clk / 16);
> + return gd->cpu_clk / 16;
>
> pll = in_be32(&immap->im_clkrst.car_plprcr);
>
> @@ -281,28 +284,28 @@ unsigned long get_tbclk (void)
> * (PDF + 1) * 2^S
> *
> */
> - factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
> - (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
> + factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD) + 1)) /
> + (PLPRCR_val(PDF) + 1) / (1 << PLPRCR_val(S));
>
> oscclk = gd->cpu_clk / factor;
>
> if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
> factor > 2)
> - return (oscclk / 4);
> + return oscclk / 4;
>
> - return (oscclk / 16);
> + return oscclk / 16;
> }
>
> /* ------------------------------------------------------------------------- */
>
> #if defined(CONFIG_WATCHDOG)
> -void watchdog_reset (void)
> +void watchdog_reset(void)
> {
> - int re_enable = disable_interrupts ();
> + int re_enable = disable_interrupts();
>
> reset_8xx_watchdog((immap_t __iomem *)CONFIG_SYS_IMMR);
> if (re_enable)
> - enable_interrupts ();
> + enable_interrupts();
> }
> #endif /* CONFIG_WATCHDOG */
>
> diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
> index 52406e8483..79b12b2408 100644
> --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
> +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
> @@ -29,7 +29,7 @@ void cpu_init_f(immap_t __iomem *immr)
> out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR);
>
> #if defined(CONFIG_WATCHDOG)
> - reset_8xx_watchdog (immr);
> + reset_8xx_watchdog(immr);
> #endif /* CONFIG_WATCHDOG */
>
> /* SIUMCR - contains debug pin configuration (11-6) */
> @@ -170,7 +170,7 @@ void cpu_init_f(immap_t __iomem *immr)
> /*
> * initialize higher level parts of CPU like timers
> */
> -int cpu_init_r (void)
> +int cpu_init_r(void)
> {
> - return (0);
> + return 0;
> }
> diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c
> index 34d36478d3..88ee1c502c 100644
> --- a/arch/powerpc/cpu/mpc8xx/fdt.c
> +++ b/arch/powerpc/cpu/mpc8xx/fdt.c
> @@ -15,13 +15,13 @@ DECLARE_GLOBAL_DATA_PTR;
> void ft_cpu_setup(void *blob, bd_t *bd)
> {
> do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
> - "timebase-frequency", get_tbclk(), 1);
> + "timebase-frequency", get_tbclk(), 1);
> do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
> - "bus-frequency", bd->bi_busfreq, 1);
> + "bus-frequency", bd->bi_busfreq, 1);
> do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
> - "clock-frequency", bd->bi_intfreq, 1);
> + "clock-frequency", bd->bi_intfreq, 1);
> do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
> - gd->arch.brg_clk, 1);
> + gd->arch.brg_clk, 1);
>
> fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
> }
> diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
> index eaaea2d4e8..f2ea0d1b8a 100644
> --- a/arch/powerpc/cpu/mpc8xx/fec.c
> +++ b/arch/powerpc/cpu/mpc8xx/fec.c
> @@ -102,7 +102,7 @@ static struct ether_fcc_info_s
> #define PKT_MAXBLR_SIZE 1520
>
> #ifdef __GNUC__
> -static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8)));
> +static char txbuf[DBUF_LENGTH] __aligned(8);
> #else
> #error txbuf must be aligned.
> #endif
> @@ -117,28 +117,27 @@ static uint txIdx; /* index of the current TX buffer */
> */
>
> struct common_buf_desc {
> - cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
> - cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
> + cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
> + cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
> };
>
> static struct common_buf_desc __iomem *rtx;
>
> static int fec_send(struct eth_device *dev, void *packet, int length);
> -static int fec_recv(struct eth_device* dev);
> -static int fec_init(struct eth_device* dev, bd_t * bd);
> -static void fec_halt(struct eth_device* dev);
> +static int fec_recv(struct eth_device *dev);
> +static int fec_init(struct eth_device *dev, bd_t *bd);
> +static void fec_halt(struct eth_device *dev);
> #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
> static void __mii_init(void);
> #endif
>
> int fec_initialize(bd_t *bis)
> {
> - struct eth_device* dev;
> + struct eth_device *dev;
> struct ether_fcc_info_s *efis;
> int i;
>
> for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {
> -
> dev = malloc(sizeof(*dev));
> if (dev == NULL)
> hang();
> @@ -147,12 +146,11 @@ int fec_initialize(bd_t *bis)
>
> /* for FEC1 make sure that the name of the interface is the same
> as the old one for compatibility reasons */
> - if (i == 0) {
> + if (i == 0)
> strcpy(dev->name, "FEC");
> - } else {
> - sprintf (dev->name, "FEC%d",
> + else
> + sprintf(dev->name, "FEC%d",
> ether_fcc_info[i].ether_index + 1);
> - }
>
> efis = ðer_fcc_info[i];
>
> @@ -202,9 +200,8 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
> udelay(1);
> j++;
> }
> - if (j>=TOUT_LOOP) {
> + if (j >= TOUT_LOOP)
> printf("TX not ready\n");
> - }
>
> out_be32(&rtx->txbd[txIdx].cbd_bufaddr, (uint)packet);
> out_be16(&rtx->txbd[txIdx].cbd_datlen, length);
> @@ -221,9 +218,9 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
> udelay(1);
> j++;
> }
> - if (j>=TOUT_LOOP) {
> + if (j >= TOUT_LOOP)
> printf("TX timeout\n");
> - }
> +
> /* return only status bits */;
> rc = in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_STATS;
>
> @@ -232,7 +229,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
> return rc;
> }
>
> -static int fec_recv (struct eth_device *dev)
> +static int fec_recv(struct eth_device *dev)
> {
> struct ether_fcc_info_s *efis = dev->priv;
> fec_t __iomem *fecp =
> @@ -436,7 +433,6 @@ static void fec_pin_init(int fecidx)
>
> #endif /* CONFIG_ETHER_ON_FEC1 */
> } else if (fecidx == 1) {
> -
> #if defined(CONFIG_ETHER_ON_FEC2)
>
> #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
> @@ -467,7 +463,6 @@ static void fec_pin_init(int fecidx)
> #endif /* CONFIG_MPC885_FAMILY */
>
> #endif /* CONFIG_ETHER_ON_FEC2 */
> -
> }
> }
>
> @@ -486,7 +481,7 @@ static int fec_reset(fec_t __iomem *fecp)
> out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
> for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
> (i < FEC_RESET_DELAY); ++i)
> - udelay (1);
> + udelay(1);
>
> if (i == FEC_RESET_DELAY)
> return -1;
> @@ -494,7 +489,7 @@ static int fec_reset(fec_t __iomem *fecp)
> return 0;
> }
>
> -static int fec_init (struct eth_device *dev, bd_t * bd)
> +static int fec_init(struct eth_device *dev, bd_t *bd)
> {
> struct ether_fcc_info_s *efis = dev->priv;
> immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
> @@ -512,7 +507,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
> #endif
>
> if (fec_reset(fecp) < 0)
> - printf ("FEC_RESET_DELAY timeout\n");
> + printf("FEC_RESET_DELAY timeout\n");
>
> /* We use strictly polling mode only
> */
> @@ -554,7 +549,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
> out_be32(&fecp->fec_r_hash, PKT_MAXBUF_SIZE);
>
> /*
> - * Setup Buffers and Buffer Desriptors
> + * Setup Buffers and Buffer Descriptors
> */
> rxIdx = 0;
> txIdx = 0;
> @@ -604,7 +599,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
> /*
> * Setup the pin configuration of the FEC
> */
> - fec_pin_init (efis->ether_index);
> + fec_pin_init(efis->ether_index);
>
> rxIdx = 0;
> txIdx = 0;
> @@ -619,10 +614,10 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
> /*
> * wait for the PHY to wake up after reset
> */
> - efis->actual_phy_addr = mii_discover_phy (dev);
> + efis->actual_phy_addr = mii_discover_phy(dev);
>
> if (efis->actual_phy_addr == -1) {
> - printf ("Unable to discover phy!\n");
> + printf("Unable to discover phy!\n");
> return -1;
> }
> #else
> @@ -636,22 +631,20 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
> /*
> * adapt the RMII speed to the speed of the phy
> */
> - if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
> - fec_100Mbps (dev);
> - } else {
> - fec_10Mbps (dev);
> - }
> + if (miiphy_speed(dev->name, efis->actual_phy_addr) == _100BASET)
> + fec_100Mbps(dev);
> + else
> + fec_10Mbps(dev);
> #endif
>
> #if defined(CONFIG_MII)
> /*
> * adapt to the half/full speed settings
> */
> - if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
> - fec_full_duplex (dev);
> - } else {
> - fec_half_duplex (dev);
> - }
> + if (miiphy_duplex(dev->name, efis->actual_phy_addr) == FULL)
> + fec_full_duplex(dev);
> + else
> + fec_half_duplex(dev);
> #endif
>
> /* And last, try to fill Rx Buffer Descriptors */
> @@ -664,7 +657,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
> }
>
>
> -static void fec_halt(struct eth_device* dev)
> +static void fec_halt(struct eth_device *dev)
> {
> struct ether_fcc_info_s *efis = dev->priv;
> fec_t __iomem *fecp =
> @@ -686,10 +679,10 @@ static void fec_halt(struct eth_device* dev)
> out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
> for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
> (i < FEC_RESET_DELAY); ++i)
> - udelay (1);
> + udelay(1);
>
> if (i == FEC_RESET_DELAY) {
> - printf ("FEC_RESET_DELAY timeout\n");
> + printf("FEC_RESET_DELAY timeout\n");
> return;
> }
>
> @@ -744,7 +737,7 @@ mii_send(uint mii_cmd)
> }
> mii_reply = in_be32(&ep->fec_mii_data); /* result from phy */
> out_be32(&ep->fec_ievent, FEC_ENET_MII); /* clear MII complete */
> - return (mii_reply & 0xffff); /* data read from phy */
> + return mii_reply & 0xffff; /* data read from phy */
> }
> #endif
>
> @@ -776,9 +769,9 @@ static int mii_discover_phy(struct eth_device *dev)
> }
> }
> }
> - if (phyaddr < 0) {
> + if (phyaddr < 0)
> printf("No PHY device found.\n");
> - }
> +
> return phyaddr;
> }
> #endif /* CONFIG_SYS_DISCOVER_PHY */
> @@ -796,7 +789,7 @@ static void __mii_init(void)
> fec_t __iomem *fecp = &immr->im_cpm.cp_fec;
>
> if (fec_reset(fecp) < 0)
> - printf ("FEC_RESET_DELAY timeout\n");
> + printf("FEC_RESET_DELAY timeout\n");
>
> /* We use strictly polling mode only
> */
> @@ -811,7 +804,7 @@ static void __mii_init(void)
> out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
> }
>
> -void mii_init (void)
> +void mii_init(void)
> {
> int i;
>
> diff --git a/arch/powerpc/cpu/mpc8xx/immap.c b/arch/powerpc/cpu/mpc8xx/immap.c
> index 63cc664e92..6da085325d 100644
> --- a/arch/powerpc/cpu/mpc8xx/immap.c
> +++ b/arch/powerpc/cpu/mpc8xx/immap.c
> @@ -19,8 +19,7 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -int
> -do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +int do_siuinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> sysconf8xx_t __iomem *sc = &immap->im_siu_conf;
> @@ -37,8 +36,7 @@ do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> return 0;
> }
>
> -int
> -do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +int do_memcinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> memctl8xx_t __iomem *memctl = &immap->im_memctl;
> @@ -60,8 +58,7 @@ do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> return 0;
> }
>
> -int
> -do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +int do_carinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> car8xx_t __iomem *car = &immap->im_clkrst;
> @@ -74,8 +71,7 @@ do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>
> static int counter;
>
> -static void
> -header(void)
> +static void header(void)
> {
> char *data = "\
> -------------------------------- --------------------------------\
> @@ -93,27 +89,27 @@ header(void)
> printf("%.79s\n", data);
> }
>
> -static void binary (char *label, uint value, int nbits)
> +static void binary(char *label, uint value, int nbits)
> {
> uint mask = 1 << (nbits - 1);
> int i, second = (counter++ % 2);
>
> if (second)
> - putc (' ');
> - puts (label);
> + putc(' ');
> + puts(label);
> for (i = 32 + 1; i != nbits; i--)
> - putc (' ');
> + putc(' ');
>
> while (mask != 0) {
> if (value & mask)
> - putc ('1');
> + putc('1');
> else
> - putc ('0');
> + putc('0');
> mask >>= 1;
> }
>
> if (second)
> - putc ('\n');
> + putc('\n');
> }
>
> #define PA_NBITS 16
> @@ -123,8 +119,7 @@ static void binary (char *label, uint value, int nbits)
> #define PC_NBITS 12
> #define PD_NBITS 13
>
> -int
> -do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +int do_iopinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> iop8xx_t __iomem *iop = &immap->im_ioport;
> @@ -132,7 +127,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> uint __iomem *R;
>
> counter = 0;
> - header ();
> + header();
>
> /*
> * Ports A & B
> @@ -149,7 +144,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> binary("PA_DAT", in_be16(l++), PA_NBITS);
> binary("PB_DAT", in_be32(R++), PB_NBITS);
>
> - header ();
> + header();
>
> /*
> * Ports C & D
> @@ -168,7 +163,7 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> binary("PD_DAT", in_be16(r++), PD_NBITS);
> binary("PC_INT", in_be16(l++), PC_NBITS);
>
> - header ();
> + header();
> return 0;
> }
>
> @@ -177,14 +172,13 @@ do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> * this needs a clean up for smaller tighter code
> * use *uint and set the address based on cmd + port
> */
> -int
> -do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +int do_iopset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> {
> uint rcode = 0;
> iopin_t iopin;
> - static uint port = 0;
> - static uint pin = 0;
> - static uint value = 0;
> + static uint port;
> + static uint pin;
> + static uint value;
> static enum {
> DIR,
> PAR,
> @@ -195,7 +189,7 @@ do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> } cmd = DAT;
>
> if (argc != 5) {
> - puts ("iopset PORT PIN CMD VALUE\n");
> + puts("iopset PORT PIN CMD VALUE\n");
> return 1;
> }
> port = argv[1][0] - 'A';
> @@ -203,7 +197,7 @@ do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> port -= 0x20;
> if (port > 3)
> rcode = 1;
> - pin = simple_strtol (argv[2], NULL, 10);
> + pin = simple_strtol(argv[2], NULL, 10);
> if (pin > 31)
> rcode = 1;
>
> @@ -230,7 +224,7 @@ do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> cmd = INT;
> break;
> default:
> - printf ("iopset: unknown command %s\n", argv[3]);
> + printf("iopset: unknown command %s\n", argv[3]);
> rcode = 1;
> }
> if (argv[4][0] == '1')
> @@ -246,47 +240,46 @@ do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> switch (cmd) {
> case DIR:
> if (value)
> - iopin_set_out (&iopin);
> + iopin_set_out(&iopin);
> else
> - iopin_set_in (&iopin);
> + iopin_set_in(&iopin);
> break;
> case PAR:
> if (value)
> - iopin_set_ded (&iopin);
> + iopin_set_ded(&iopin);
> else
> - iopin_set_gen (&iopin);
> + iopin_set_gen(&iopin);
> break;
> case SOR:
> if (value)
> - iopin_set_opt2 (&iopin);
> + iopin_set_opt2(&iopin);
> else
> - iopin_set_opt1 (&iopin);
> + iopin_set_opt1(&iopin);
> break;
> case ODR:
> if (value)
> - iopin_set_odr (&iopin);
> + iopin_set_odr(&iopin);
> else
> - iopin_set_act (&iopin);
> + iopin_set_act(&iopin);
> break;
> case DAT:
> if (value)
> - iopin_set_high (&iopin);
> + iopin_set_high(&iopin);
> else
> - iopin_set_low (&iopin);
> + iopin_set_low(&iopin);
> break;
> case INT:
> if (value)
> - iopin_set_falledge (&iopin);
> + iopin_set_falledge(&iopin);
> else
> - iopin_set_anyedge (&iopin);
> + iopin_set_anyedge(&iopin);
> break;
> }
> -
> }
> return rcode;
> }
>
> -static void prbrg (int n, uint val)
> +static void prbrg(int n, uint val)
> {
> uint extc = (val >> 14) & 3;
> uint cd = (val & CPM_BRG_CD_MASK) >> 1;
> @@ -294,26 +287,26 @@ static void prbrg (int n, uint val)
>
> ulong clock = gd->cpu_clk;
>
> - printf ("BRG%d:", n);
> + printf("BRG%d:", n);
>
> if (val & CPM_BRG_RST)
> - puts (" RESET");
> + puts(" RESET");
> else
> - puts (" ");
> + puts(" ");
>
> if (val & CPM_BRG_EN)
> - puts (" ENABLED");
> + puts(" ENABLED");
> else
> - puts (" DISABLED");
> + puts(" DISABLED");
>
> - printf (" EXTC=%d", extc);
> + printf(" EXTC=%d", extc);
>
> if (val & CPM_BRG_ATB)
> - puts (" ATB");
> + puts(" ATB");
> else
> - puts (" ");
> + puts(" ");
>
> - printf (" DIVIDER=%4d", cd);
> + printf(" DIVIDER=%4d", cd);
> if (extc == 0 && cd != 0) {
> uint baudrate;
>
> @@ -322,21 +315,20 @@ static void prbrg (int n, uint val)
> else
> baudrate = clock / (cd + 1);
>
> - printf ("=%6d bps", baudrate);
> + printf("=%6d bps", baudrate);
> } else {
> - puts (" ");
> + puts(" ");
> }
>
> if (val & CPM_BRG_DIV16)
> - puts (" DIV16");
> + puts(" DIV16");
> else
> - puts (" ");
> + puts(" ");
>
> - putc ('\n');
> + putc('\n');
> }
>
> -int
> -do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +int do_brginfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
> cpm8xx_t __iomem *cp = &immap->im_cpm;
> diff --git a/arch/powerpc/cpu/mpc8xx/interrupts.c b/arch/powerpc/cpu/mpc8xx/interrupts.c
> index db6df74b5e..e8e287a13f 100644
> --- a/arch/powerpc/cpu/mpc8xx/interrupts.c
> +++ b/arch/powerpc/cpu/mpc8xx/interrupts.c
> @@ -25,24 +25,24 @@ struct interrupt_action {
> static struct interrupt_action cpm_vecs[CPMVEC_NR];
> static struct interrupt_action irq_vecs[NR_IRQS];
>
> -static void cpm_interrupt_init (void);
> -static void cpm_interrupt (void *regs);
> +static void cpm_interrupt_init(void);
> +static void cpm_interrupt(void *regs);
>
> /************************************************************************/
>
> -int interrupt_init_cpu (unsigned *decrementer_count)
> +int interrupt_init_cpu(unsigned *decrementer_count)
> {
> immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> - *decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
> + *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
>
> /* disable all interrupts */
> out_be32(&immr->im_siu_conf.sc_simask, 0);
>
> /* Configure CPM interrupts */
> - cpm_interrupt_init ();
> + cpm_interrupt_init();
>
> - return (0);
> + return 0;
> }
>
> /************************************************************************/
> @@ -50,7 +50,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
> /*
> * Handle external interrupts
> */
> -void external_interrupt (struct pt_regs *regs)
> +void external_interrupt(struct pt_regs *regs)
> {
> immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
> int irq;
> @@ -88,10 +88,10 @@ void external_interrupt (struct pt_regs *regs)
> }
>
> if (irq_vecs[irq].handler != NULL) {
> - irq_vecs[irq].handler (irq_vecs[irq].arg);
> + irq_vecs[irq].handler(irq_vecs[irq].arg);
> } else {
> - printf ("\nBogus External Interrupt IRQ %d Vector %ld\n",
> - irq, vec);
> + printf("\nBogus External Interrupt IRQ %d Vector %ld\n",
> + irq, vec);
> /* turn off the bogus interrupt to avoid it from now */
> simask &= ~v_bit;
> }
> @@ -106,7 +106,7 @@ void external_interrupt (struct pt_regs *regs)
> /*
> * CPM interrupt handler
> */
> -static void cpm_interrupt (void *regs)
> +static void cpm_interrupt(void *regs)
> {
> immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
> uint vec;
> @@ -123,7 +123,7 @@ static void cpm_interrupt (void *regs)
> (*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
> } else {
> clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
> - printf ("Masking bogus CPM interrupt vector 0x%x\n", vec);
> + printf("Masking bogus CPM interrupt vector 0x%x\n", vec);
> }
> /*
> * After servicing the interrupt,
> @@ -138,7 +138,7 @@ static void cpm_interrupt (void *regs)
> * to do is ACK it and return. This is a no-op function so we don't
> * need any special tests in the interrupt handler.
> */
> -static void cpm_error_interrupt (void *dummy)
> +static void cpm_error_interrupt(void *dummy)
> {
> }
>
> @@ -146,37 +146,31 @@ static void cpm_error_interrupt (void *dummy)
> /*
> * Install and free an interrupt handler
> */
> -void irq_install_handler (int vec, interrupt_handler_t * handler,
> - void *arg)
> +void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
> {
> immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> if ((vec & CPMVEC_OFFSET) != 0) {
> /* CPM interrupt */
> vec &= 0xffff;
> - if (cpm_vecs[vec].handler != NULL) {
> - printf ("CPM interrupt 0x%x replacing 0x%x\n",
> - (uint) handler,
> - (uint) cpm_vecs[vec].handler);
> - }
> + if (cpm_vecs[vec].handler != NULL)
> + printf("CPM interrupt 0x%x replacing 0x%x\n",
> + (uint)handler, (uint)cpm_vecs[vec].handler);
> cpm_vecs[vec].handler = handler;
> cpm_vecs[vec].arg = arg;
> setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
> } else {
> /* SIU interrupt */
> - if (irq_vecs[vec].handler != NULL) {
> - printf ("SIU interrupt %d 0x%x replacing 0x%x\n",
> - vec,
> - (uint) handler,
> - (uint) cpm_vecs[vec].handler);
> - }
> + if (irq_vecs[vec].handler != NULL)
> + printf("SIU interrupt %d 0x%x replacing 0x%x\n",
> + vec, (uint)handler, (uint)cpm_vecs[vec].handler);
> irq_vecs[vec].handler = handler;
> irq_vecs[vec].arg = arg;
> setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
> }
> }
>
> -void irq_free_handler (int vec)
> +void irq_free_handler(int vec)
> {
> immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -196,7 +190,7 @@ void irq_free_handler (int vec)
>
> /************************************************************************/
>
> -static void cpm_interrupt_init (void)
> +static void cpm_interrupt_init(void)
> {
> immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
> uint cicr;
> @@ -214,14 +208,14 @@ static void cpm_interrupt_init (void)
> /*
> * Install the error handler.
> */
> - irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL);
> + irq_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL);
>
> setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN);
>
> /*
> * Install the cpm interrupt handler
> */
> - irq_install_handler (CPM_INTERRUPT, cpm_interrupt, NULL);
> + irq_install_handler(CPM_INTERRUPT, cpm_interrupt, NULL);
> }
>
> /************************************************************************/
> @@ -231,7 +225,7 @@ static void cpm_interrupt_init (void)
> * with interrupts disabled.
> * Trivial implementation - no need to be really accurate.
> */
> -void timer_interrupt_cpu (struct pt_regs *regs)
> +void timer_interrupt_cpu(struct pt_regs *regs)
> {
> immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> diff --git a/arch/powerpc/cpu/mpc8xx/reginfo.c b/arch/powerpc/cpu/mpc8xx/reginfo.c
> index 48615cad01..1ba4d22bdd 100644
> --- a/arch/powerpc/cpu/mpc8xx/reginfo.c
> +++ b/arch/powerpc/cpu/mpc8xx/reginfo.c
> @@ -20,7 +20,7 @@ void mpc8xx_reginfo(void)
> * other useful registers
> */
>
> - printf ("\nSystem Configuration registers\n"
> + printf("\nSystem Configuration registers\n"
> "\tIMMR\t0x%08X\n", get_immr(0));
>
> printf("\tSIUMCR\t0x%08X", in_be32(&sysconf->sc_siumcr));
> diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c
> index 598ca2a7b0..114dfe9b4b 100644
> --- a/arch/powerpc/cpu/mpc8xx/serial.c
> +++ b/arch/powerpc/cpu/mpc8xx/serial.c
> @@ -49,11 +49,11 @@ struct serialbuffer {
>
> static void serial_setdivisor(cpm8xx_t __iomem *cp)
> {
> - int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
> + int divisor = (gd->cpu_clk + 8 * gd->baudrate) / 16 / gd->baudrate;
>
> - if(divisor/16>0x1000) {
> + if (divisor / 16 > 0x1000) {
> /* bad divisor, assume 50MHz clock and 9600 baud */
> - divisor=(50*1000*1000 + 8*9600)/16/9600;
> + divisor = (50 * 1000 * 1000 + 8 * 9600) / 16 / 9600;
> }
>
> #ifdef CONFIG_SYS_BRGCLK_PRESCALE
> @@ -72,7 +72,7 @@ static void serial_setdivisor(cpm8xx_t __iomem *cp)
> * as serial console interface.
> */
>
> -static void smc_setbrg (void)
> +static void smc_setbrg(void)
> {
> immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
> cpm8xx_t __iomem *cp = &(im->im_cpm);
> @@ -88,7 +88,7 @@ static void smc_setbrg (void)
> serial_setdivisor(cp);
> }
>
> -static int smc_init (void)
> +static int smc_init(void)
> {
> immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
> smc_t __iomem *sp;
> @@ -161,7 +161,7 @@ static int smc_init (void)
> out_8(&sp->smc_smce, 0xff);
>
> /* Set up the baud rate generator */
> - smc_setbrg ();
> + smc_setbrg();
>
> /* Make the first buffer the only buffer. */
> setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP);
> @@ -185,18 +185,17 @@ static int smc_init (void)
> /* Enable transmitter/receiver. */
> setbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
>
> - return (0);
> + return 0;
> }
>
> -static void
> -smc_putc(const char c)
> +static void smc_putc(const char c)
> {
> immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
> cpm8xx_t __iomem *cpmp = &(im->im_cpm);
> struct serialbuffer __iomem *rtx;
>
> if (c == '\n')
> - smc_putc ('\r');
> + smc_putc('\r');
>
> rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
>
> @@ -206,19 +205,16 @@ smc_putc(const char c)
> setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);
>
> while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
> - WATCHDOG_RESET ();
> + WATCHDOG_RESET();
> }
>
> -static void
> -smc_puts (const char *s)
> +static void smc_puts(const char *s)
> {
> - while (*s) {
> - smc_putc (*s++);
> - }
> + while (*s)
> + smc_putc(*s++);
> }
>
> -static int
> -smc_getc(void)
> +static int smc_getc(void)
> {
> immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
> cpm8xx_t __iomem *cpmp = &(im->im_cpm);
> @@ -230,7 +226,7 @@ smc_getc(void)
>
> /* Wait for character to show up. */
> while (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
> - WATCHDOG_RESET ();
> + WATCHDOG_RESET();
>
> /* the characters are read one by one,
> * use the rxindex to know the next char to deliver
> @@ -245,11 +241,10 @@ smc_getc(void)
> setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY);
> }
> out_be32(&rtx->rxindex, rxindex);
> - return(c);
> + return c;
> }
>
> -static int
> -smc_tstc(void)
> +static int smc_tstc(void)
> {
> immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
> cpm8xx_t __iomem *cpmp = &(im->im_cpm);
> @@ -260,8 +255,7 @@ smc_tstc(void)
> return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY);
> }
>
> -struct serial_device serial_smc_device =
> -{
> +struct serial_device serial_smc_device = {
> .name = "serial_smc",
> .start = smc_init,
> .stop = NULL,
> diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c
> index c91427e904..8d43efff6c 100644
> --- a/arch/powerpc/cpu/mpc8xx/speed.c
> +++ b/arch/powerpc/cpu/mpc8xx/speed.c
> @@ -16,29 +16,29 @@ void get_brgclk(uint sccr)
> {
> uint divider = 0;
>
> - switch((sccr&SCCR_DFBRG11)>>11){
> - case 0:
> - divider = 1;
> - break;
> - case 1:
> - divider = 4;
> - break;
> - case 2:
> - divider = 16;
> - break;
> - case 3:
> - divider = 64;
> - break;
> + switch ((sccr & SCCR_DFBRG11) >> 11) {
> + case 0:
> + divider = 1;
> + break;
> + case 1:
> + divider = 4;
> + break;
> + case 2:
> + divider = 16;
> + break;
> + case 3:
> + divider = 64;
> + break;
> }
> - gd->arch.brg_clk = gd->cpu_clk/divider;
> + gd->arch.brg_clk = gd->cpu_clk / divider;
> }
>
> /*
> * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
> */
> -int get_clocks (void)
> +int get_clocks(void)
> {
> - uint immr = get_immr (0); /* Return full IMMR contents */
> + uint immr = get_immr(0); /* Return full IMMR contents */
> immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
> uint sccr = in_be32(&immap->im_clkrst.car_sccr);
> /*
> @@ -59,5 +59,5 @@ int get_clocks (void)
>
> get_brgclk(sccr);
>
> - return (0);
> + return 0;
> }
> diff --git a/arch/powerpc/cpu/mpc8xx/spi.c b/arch/powerpc/cpu/mpc8xx/spi.c
> index e7d197f968..6e3e86fb0f 100644
> --- a/arch/powerpc/cpu/mpc8xx/spi.c
> +++ b/arch/powerpc/cpu/mpc8xx/spi.c
> @@ -50,11 +50,7 @@
> /* -------------------
> * Function prototypes
> * ------------------- */
> -void spi_init (void);
> -
> -ssize_t spi_read (uchar *, int, uchar *, int);
> -ssize_t spi_write (uchar *, int, uchar *, int);
> -ssize_t spi_xfer (size_t);
> +ssize_t spi_xfer(size_t);
>
> /* -------------------
> * Variables
> @@ -66,10 +62,10 @@ ssize_t spi_xfer (size_t);
> * Initially we place the RX and TX buffers at a fixed location in DPRAM!
> * ---------------------------------------------------------------------- */
> static uchar *rxbuf =
> - (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
> + (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
> [CONFIG_SYS_SPI_INIT_OFFSET];
> static uchar *txbuf =
> - (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
> + (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
> [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER];
>
> /* **************************************************************************
> @@ -81,7 +77,7 @@ static uchar *txbuf =
> * return: ---
> *
> * *********************************************************************** */
> -void spi_init_f (void)
> +void spi_init_f(void)
> {
> immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
> cpm8xx_t __iomem *cp = &immr->im_cpm;
> @@ -120,7 +116,7 @@ void spi_init_f (void)
> * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
> * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI
> * PBODR[30] = 0 [0x00000002] -> active output: SPICLK
> - * PBODR[31] = 0 [0x00000001] -> active output: GPIO OUT: CS for PCUE/CCM
> + * PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM
> * ---------------------------------------------- */
>
> clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008);
> @@ -209,7 +205,7 @@ void spi_init_f (void)
> * return: ---
> *
> * *********************************************************************** */
> -void spi_init_r (void)
> +void spi_init_r(void)
> {
> immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
> cpm8xx_t __iomem *cp = &immr->im_cpm;
> @@ -224,8 +220,8 @@ void spi_init_r (void)
> rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
>
> /* Allocate memory for RX and TX buffers */
> - rxbuf = (uchar *) malloc (MAX_BUFFER);
> - txbuf = (uchar *) malloc (MAX_BUFFER);
> + rxbuf = (uchar *)malloc(MAX_BUFFER);
> + txbuf = (uchar *)malloc(MAX_BUFFER);
>
> out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf);
> out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf);
> @@ -236,7 +232,7 @@ void spi_init_r (void)
> /****************************************************************************
> * Function: spi_write
> **************************************************************************** */
> -ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
> +ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
> {
> int i;
>
> @@ -253,14 +249,12 @@ ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
> *txbuf = SPI_EEPROM_RDSR; /* read status */
> txbuf[1] = 0;
> spi_xfer(2);
> - if (!(rxbuf[1] & 1)) {
> + if (!(rxbuf[1] & 1))
> break;
> - }
> udelay(1000);
> }
> - if (i >= 1000) {
> - printf ("*** spi_write: Time out while writing!\n");
> - }
> + if (i >= 1000)
> + printf("*** spi_write: Time out while writing!\n");
>
> return len;
> }
> @@ -268,7 +262,7 @@ ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
> /****************************************************************************
> * Function: spi_read
> **************************************************************************** */
> -ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
> +ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
> {
> memset(rxbuf, 0, MAX_BUFFER);
> memset(txbuf, 0, MAX_BUFFER);
> @@ -290,7 +284,7 @@ ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
> /****************************************************************************
> * Function: spi_xfer
> **************************************************************************** */
> -ssize_t spi_xfer (size_t count)
> +ssize_t spi_xfer(size_t count)
> {
> immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
> cpm8xx_t __iomem *cp = &immr->im_cpm;
> @@ -327,16 +321,15 @@ ssize_t spi_xfer (size_t count)
> * Wait for SPI transmit to get out
> * or time out (1 second = 1000 ms)
> * -------------------------------- */
> - for (tm=0; tm<1000; ++tm) {
> + for (tm = 0; tm < 1000; ++tm) {
> if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */
> break;
> if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0)
> break;
> - udelay (1000);
> - }
> - if (tm >= 1000) {
> - printf ("*** spi_xfer: Time out while xferring to/from SPI!\n");
> + udelay(1000);
> }
> + if (tm >= 1000)
> + printf("*** spi_xfer: Time out while xferring to/from SPI!\n");
>
> /* Clear CS for device */
> setbits_be32(&cp->cp_pbdat, 0x0001);
> diff --git a/arch/powerpc/cpu/mpc8xx/traps.c b/arch/powerpc/cpu/mpc8xx/traps.c
> index ec283d83fa..8b8d617eed 100644
> --- a/arch/powerpc/cpu/mpc8xx/traps.c
> +++ b/arch/powerpc/cpu/mpc8xx/traps.c
> @@ -45,7 +45,8 @@ static void print_backtrace(unsigned long *sp)
> if (cnt++ % 7 == 0)
> printf("\n");
> printf("%08lX ", i);
> - if (cnt > 32) break;
> + if (cnt > 32)
> + break;
> sp = (unsigned long *)*sp;
> }
> printf("\n");
> @@ -58,23 +59,19 @@ void show_regs(struct pt_regs *regs)
> printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
> regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
> printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
> - regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
> - regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
> - regs->msr&MSR_IR ? 1 : 0,
> - regs->msr&MSR_DR ? 1 : 0);
> + regs->msr, regs->msr & MSR_EE ? 1 : 0,
> + regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0,
> + regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0,
> + regs->msr & MSR_DR ? 1 : 0);
>
> printf("\n");
> for (i = 0; i < 32; i++) {
> if ((i % 8) == 0)
> - {
> printf("GPR%02d: ", i);
> - }
>
> printf("%08lX ", regs->gpr[i]);
> if ((i % 8) == 7)
> - {
> printf("\n");
> - }
> }
> }
>
> @@ -83,37 +80,37 @@ static void _exception(int signr, struct pt_regs *regs)
> {
> show_regs(regs);
> print_backtrace((unsigned long *)regs->gpr[1]);
> - panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
> + panic("Exception in kernel pc %lx signal %d", regs->nip, signr);
> }
>
> void MachineCheckException(struct pt_regs *regs)
> {
> - unsigned long fixup;
> + unsigned long fixup = search_exception_table(regs->nip);
>
> /* Probing PCI using config cycles cause this exception
> * when a device is not present. Catch it and return to
> * the PCI exception handler.
> */
> - if ((fixup = search_exception_table(regs->nip)) != 0) {
> + if (fixup != 0) {
> regs->nip = fixup;
> return;
> }
>
> printf("Machine check in kernel mode.\n");
> printf("Caused by (from msr): ");
> - printf("regs %p ",regs);
> - switch( regs->msr & 0x000F0000) {
> - case (0x80000000>>12):
> + printf("regs %p ", regs);
> + switch (regs->msr & 0x000F0000) {
> + case (0x80000000 >> 12):
> printf("Machine check signal - probably due to mm fault\n"
> "with mmu off\n");
> break;
> - case (0x80000000>>13):
> + case (0x80000000 >> 13):
> printf("Transfer error ack signal\n");
> break;
> - case (0x80000000>>14):
> + case (0x80000000 >> 14):
> printf("Data parity signal\n");
> break;
> - case (0x80000000>>15):
> + case (0x80000000 >> 15):
> printf("Address parity signal\n");
> break;
> default:
> @@ -155,8 +152,8 @@ void UnknownException(struct pt_regs *regs)
>
> void DebugException(struct pt_regs *regs)
> {
> - printf("Debugger trap at @ %lx\n", regs->nip );
> - show_regs(regs);
> + printf("Debugger trap at @ %lx\n", regs->nip);
> + show_regs(regs);
> }
>
> /* Probe an address by reading. If not present, return -1, otherwise
> diff --git a/arch/powerpc/include/asm/iopin_8xx.h b/arch/powerpc/include/asm/iopin_8xx.h
> index beca988d77..15679a2db5 100644
> --- a/arch/powerpc/include/asm/iopin_8xx.h
> +++ b/arch/powerpc/include/asm/iopin_8xx.h
> @@ -27,8 +27,7 @@ typedef struct {
> #define IOPIN_PORTC 2
> #define IOPIN_PORTD 3
>
> -static __inline__ void
> -iopin_set_high(iopin_t *iopin)
> +static inline void iopin_set_high(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -51,8 +50,7 @@ iopin_set_high(iopin_t *iopin)
> }
> }
>
> -static __inline__ void
> -iopin_set_low(iopin_t *iopin)
> +static inline void iopin_set_low(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -75,8 +73,7 @@ iopin_set_low(iopin_t *iopin)
> }
> }
>
> -static __inline__ uint
> -iopin_is_high(iopin_t *iopin)
> +static inline uint iopin_is_high(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -100,8 +97,7 @@ iopin_is_high(iopin_t *iopin)
> return 0;
> }
>
> -static __inline__ uint
> -iopin_is_low(iopin_t *iopin)
> +static inline uint iopin_is_low(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -125,8 +121,7 @@ iopin_is_low(iopin_t *iopin)
> return 0;
> }
>
> -static __inline__ void
> -iopin_set_out(iopin_t *iopin)
> +static inline void iopin_set_out(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -149,8 +144,7 @@ iopin_set_out(iopin_t *iopin)
> }
> }
>
> -static __inline__ void
> -iopin_set_in(iopin_t *iopin)
> +static inline void iopin_set_in(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -173,8 +167,7 @@ iopin_set_in(iopin_t *iopin)
> }
> }
>
> -static __inline__ uint
> -iopin_is_out(iopin_t *iopin)
> +static inline uint iopin_is_out(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -198,8 +191,7 @@ iopin_is_out(iopin_t *iopin)
> return 0;
> }
>
> -static __inline__ uint
> -iopin_is_in(iopin_t *iopin)
> +static inline uint iopin_is_in(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -223,8 +215,7 @@ iopin_is_in(iopin_t *iopin)
> return 0;
> }
>
> -static __inline__ void
> -iopin_set_odr(iopin_t *iopin)
> +static inline void iopin_set_odr(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -239,8 +230,7 @@ iopin_set_odr(iopin_t *iopin)
> }
> }
>
> -static __inline__ void
> -iopin_set_act(iopin_t *iopin)
> +static inline void iopin_set_act(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -255,8 +245,7 @@ iopin_set_act(iopin_t *iopin)
> }
> }
>
> -static __inline__ uint
> -iopin_is_odr(iopin_t *iopin)
> +static inline uint iopin_is_odr(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -272,8 +261,7 @@ iopin_is_odr(iopin_t *iopin)
> return 0;
> }
>
> -static __inline__ uint
> -iopin_is_act(iopin_t *iopin)
> +static inline uint iopin_is_act(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -289,8 +277,7 @@ iopin_is_act(iopin_t *iopin)
> return 0;
> }
>
> -static __inline__ void
> -iopin_set_ded(iopin_t *iopin)
> +static inline void iopin_set_ded(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -313,8 +300,7 @@ iopin_set_ded(iopin_t *iopin)
> }
> }
>
> -static __inline__ void
> -iopin_set_gen(iopin_t *iopin)
> +static inline void iopin_set_gen(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -337,8 +323,7 @@ iopin_set_gen(iopin_t *iopin)
> }
> }
>
> -static __inline__ uint
> -iopin_is_ded(iopin_t *iopin)
> +static inline uint iopin_is_ded(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -362,8 +347,7 @@ iopin_is_ded(iopin_t *iopin)
> return 0;
> }
>
> -static __inline__ uint
> -iopin_is_gen(iopin_t *iopin)
> +static inline uint iopin_is_gen(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -387,8 +371,7 @@ iopin_is_gen(iopin_t *iopin)
> return 0;
> }
>
> -static __inline__ void
> -iopin_set_opt2(iopin_t *iopin)
> +static inline void iopin_set_opt2(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -399,8 +382,7 @@ iopin_set_opt2(iopin_t *iopin)
> }
> }
>
> -static __inline__ void
> -iopin_set_opt1(iopin_t *iopin)
> +static inline void iopin_set_opt1(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -411,8 +393,7 @@ iopin_set_opt1(iopin_t *iopin)
> }
> }
>
> -static __inline__ uint
> -iopin_is_opt2(iopin_t *iopin)
> +static inline uint iopin_is_opt2(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -424,8 +405,7 @@ iopin_is_opt2(iopin_t *iopin)
> return 0;
> }
>
> -static __inline__ uint
> -iopin_is_opt1(iopin_t *iopin)
> +static inline uint iopin_is_opt1(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -437,8 +417,7 @@ iopin_is_opt1(iopin_t *iopin)
> return 0;
> }
>
> -static __inline__ void
> -iopin_set_falledge(iopin_t *iopin)
> +static inline void iopin_set_falledge(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -449,8 +428,7 @@ iopin_set_falledge(iopin_t *iopin)
> }
> }
>
> -static __inline__ void
> -iopin_set_anyedge(iopin_t *iopin)
> +static inline void iopin_set_anyedge(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -461,8 +439,7 @@ iopin_set_anyedge(iopin_t *iopin)
> }
> }
>
> -static __inline__ uint
> -iopin_is_falledge(iopin_t *iopin)
> +static inline uint iopin_is_falledge(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> @@ -474,8 +451,7 @@ iopin_is_falledge(iopin_t *iopin)
> return 0;
> }
>
> -static __inline__ uint
> -iopin_is_anyedge(iopin_t *iopin)
> +static inline uint iopin_is_anyedge(iopin_t *iopin)
> {
> immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
>
> diff --git a/include/commproc.h b/include/commproc.h
> index 5518cb325d..9536b135dc 100644
> --- a/include/commproc.h
> +++ b/include/commproc.h
> @@ -7,7 +7,7 @@
> *
> * This file contains structures and information for the communication
> * processor channels. Some CPM control and status is available
> - * throught the MPC8xx internal memory map. See immap.h for details.
> + * through the MPC8xx internal memory map. See immap.h for details.
> * This file only contains what I need for the moment, not the total
> * CPM capabilities. I (or someone else) will add definitions as they
> * are needed. -- Dan
> @@ -81,7 +81,7 @@ typedef struct cpm_buf_desc {
> #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
> #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
> #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
> -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
> +#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
> #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
> #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
> #define BD_SC_BR ((ushort)0x0020) /* Break received */
> @@ -582,8 +582,8 @@ typedef struct spi {
> #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
> #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
>
> -#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
> -#define SPMODE_PM(x) ((x) &0xF)
> +#define SPMODE_LEN(x) ((((x) - 1) & 0xF) << 4)
> +#define SPMODE_PM(x) ((x) & 0xF)
>
> /* HDLC parameter RAM.
> */
> @@ -672,7 +672,7 @@ typedef struct hdlc_pram_s {
> #define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
> #define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
>
> -extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
> +void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
>
> /* CPM interrupt configuration vector.
> */
> @@ -680,7 +680,7 @@ extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
> #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
> #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
> #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
> -#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
> +#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
> #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
> #define CICR_IEN ((uint)0x00000080) /* Int. enable */
> #define CICR_SPS ((uint)0x00000001) /* SCC Spread */
>
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 35+ messages in thread* [U-Boot] [U-Boot, v2, 05/10] powerpc, 8xx: Handle checkpatch errors and some of the warnings/checks
2017-07-06 8:33 ` [U-Boot] [PATCH v2 05/10] powerpc, 8xx: Handle checkpatch errors and some of the warnings/checks Christophe Leroy
2017-07-06 9:43 ` Heiko Schocher
@ 2017-07-09 0:24 ` Tom Rini
1 sibling, 0 replies; 35+ messages in thread
From: Tom Rini @ 2017-07-09 0:24 UTC (permalink / raw)
To: u-boot
On Thu, Jul 06, 2017 at 10:33:17AM +0200, Christophe Leroy wrote:
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> Reviewed-by: Heiko Schocher <hs@denx.de>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [U-Boot] [PATCH v2 06/10] powerpc, 8xx: Properly set CPM frequency in the device tree
2017-07-06 8:33 [U-Boot] [PATCH v2 0/10] powerpc, 8xx: Modernise the 8xx Christophe Leroy
` (4 preceding siblings ...)
2017-07-06 8:33 ` [U-Boot] [PATCH v2 05/10] powerpc, 8xx: Handle checkpatch errors and some of the warnings/checks Christophe Leroy
@ 2017-07-06 8:33 ` Christophe Leroy
2017-07-06 9:46 ` Heiko Schocher
2017-07-09 0:25 ` [U-Boot] [U-Boot, v2, " Tom Rini
2017-07-06 8:33 ` [U-Boot] [PATCH v2 07/10] powerpc, 8xx: Migrate to Kconfig Christophe Leroy
` (3 subsequent siblings)
9 siblings, 2 replies; 35+ messages in thread
From: Christophe Leroy @ 2017-07-06 8:33 UTC (permalink / raw)
To: u-boot
For processors whose core runs at twice the bus frequency,
the fallback frequency calculation in Linux provides a wrong
result. Therefore, U-boot needs to pass the correct value.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/cpu/mpc8xx/fdt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c
index 88ee1c502c..f9b74ded5a 100644
--- a/arch/powerpc/cpu/mpc8xx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xx/fdt.c
@@ -20,6 +20,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
"bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"clock-frequency", bd->bi_intfreq, 1);
+ do_fixup_by_compat_u32(blob, "fsl,pq1-soc", "clock-frequency",
+ bd->bi_intfreq, 1);
do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
gd->arch.brg_clk, 1);
--
2.12.0
^ permalink raw reply related [flat|nested] 35+ messages in thread* [U-Boot] [PATCH v2 06/10] powerpc, 8xx: Properly set CPM frequency in the device tree
2017-07-06 8:33 ` [U-Boot] [PATCH v2 06/10] powerpc, 8xx: Properly set CPM frequency in the device tree Christophe Leroy
@ 2017-07-06 9:46 ` Heiko Schocher
2017-07-09 0:25 ` [U-Boot] [U-Boot, v2, " Tom Rini
1 sibling, 0 replies; 35+ messages in thread
From: Heiko Schocher @ 2017-07-06 9:46 UTC (permalink / raw)
To: u-boot
Hello Christophe,
Am 06.07.2017 um 10:33 schrieb Christophe Leroy:
> For processors whose core runs at twice the bus frequency,
> the fallback frequency calculation in Linux provides a wrong
> result. Therefore, U-boot needs to pass the correct value.
>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
> arch/powerpc/cpu/mpc8xx/fdt.c | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Heiko Schocher <hs@denx.de>
bye,
Heiko
>
> diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c
> index 88ee1c502c..f9b74ded5a 100644
> --- a/arch/powerpc/cpu/mpc8xx/fdt.c
> +++ b/arch/powerpc/cpu/mpc8xx/fdt.c
> @@ -20,6 +20,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
> "bus-frequency", bd->bi_busfreq, 1);
> do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
> "clock-frequency", bd->bi_intfreq, 1);
> + do_fixup_by_compat_u32(blob, "fsl,pq1-soc", "clock-frequency",
> + bd->bi_intfreq, 1);
> do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
> gd->arch.brg_clk, 1);
>
>
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 35+ messages in thread
* [U-Boot] [U-Boot, v2, 06/10] powerpc, 8xx: Properly set CPM frequency in the device tree
2017-07-06 8:33 ` [U-Boot] [PATCH v2 06/10] powerpc, 8xx: Properly set CPM frequency in the device tree Christophe Leroy
2017-07-06 9:46 ` Heiko Schocher
@ 2017-07-09 0:25 ` Tom Rini
1 sibling, 0 replies; 35+ messages in thread
From: Tom Rini @ 2017-07-09 0:25 UTC (permalink / raw)
To: u-boot
On Thu, Jul 06, 2017 at 10:33:19AM +0200, Christophe Leroy wrote:
> For processors whose core runs at twice the bus frequency,
> the fallback frequency calculation in Linux provides a wrong
> result. Therefore, U-boot needs to pass the correct value.
>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> Reviewed-by: Heiko Schocher <hs@denx.de>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [U-Boot] [PATCH v2 07/10] powerpc, 8xx: Migrate to Kconfig
2017-07-06 8:33 [U-Boot] [PATCH v2 0/10] powerpc, 8xx: Modernise the 8xx Christophe Leroy
` (5 preceding siblings ...)
2017-07-06 8:33 ` [U-Boot] [PATCH v2 06/10] powerpc, 8xx: Properly set CPM frequency in the device tree Christophe Leroy
@ 2017-07-06 8:33 ` Christophe Leroy
2017-07-06 8:57 ` Bin Meng
` (2 more replies)
2017-07-06 8:33 ` [U-Boot] [PATCH v2 08/10] powerpc, 8xx: move FEC Ethernet driver in drivers/net Christophe Leroy
` (2 subsequent siblings)
9 siblings, 3 replies; 35+ messages in thread
From: Christophe Leroy @ 2017-07-06 8:33 UTC (permalink / raw)
To: u-boot
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
README | 15 ----
arch/powerpc/cpu/mpc8xx/Kconfig | 148 +++++++++++++++++++++++++++++++++++++
arch/powerpc/cpu/mpc8xx/cpu_init.c | 2 +-
arch/powerpc/cpu/mpc8xx/fec.c | 8 +-
arch/powerpc/include/asm/ppc.h | 5 --
drivers/i2c/soft_i2c.c | 2 +-
scripts/config_whitelist.txt | 11 ---
7 files changed, 154 insertions(+), 37 deletions(-)
diff --git a/README b/README
index c3ab481a56..030a452f9a 100644
--- a/README
+++ b/README
@@ -328,9 +328,6 @@ The following options need to be configured:
multiple fs option at one time
for marvell soc family
-- 8xx CPU Options: (if using an MPC8xx CPU)
- CONFIG_8xx_GCLK_FREQ - CPU clock
-
- 85xx CPU Options:
CONFIG_SYS_PPC64
@@ -3993,16 +3990,6 @@ Low Level (hardware related) configuration options:
point to an otherwise UNUSED address space between
the top of RAM and the start of the PCI space.
-- CONFIG_SYS_SIUMCR: SIU Module Configuration (11-6)
-
-- CONFIG_SYS_SYPCR: System Protection Control (11-9)
-
-- CONFIG_SYS_TBSCR: Time Base Status and Control (11-26)
-
-- CONFIG_SYS_PISCR: Periodic Interrupt Status and Control (11-31)
-
-- CONFIG_SYS_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30)
-
- CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)
- CONFIG_SYS_OR_TIMING_SDRAM:
@@ -4011,8 +3998,6 @@ Low Level (hardware related) configuration options:
- CONFIG_SYS_MAMR_PTA:
periodic timer for refresh
-- CONFIG_SYS_DER: Debug Event Register (37-47)
-
- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index cb15dc5ebc..9e1ad33c28 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -10,6 +10,21 @@ choice
endchoice
+choice
+ prompt "CPU select"
+ default MPC866
+
+config MPC866
+ bool "MPC866"
+
+config MPC885
+ bool "MPC885"
+
+endchoice
+
+config 8xx_GCLK_FREQ
+ int "CPU GCLK Frequency"
+
comment "Specific commands"
config CMD_IMMAP
@@ -19,4 +34,137 @@ config CMD_IMMAP
siuinfo - print System Interface Unit (SIU) registers
memcinfo - print Memory Controller registers
+
+comment "Configuration Registers"
+
+config SYS_SIUMCR
+ hex "SIUMCR register"
+ help
+ SIU Module Configuration (11-6)
+
+config SYS_SYPCR
+ hex "SYPCR register"
+ help
+ System Protection Control (11-9)
+
+config SYS_TBSCR
+ hex "TBSCR register"
+ help
+ Time Base Status and Control (11-26)
+
+config SYS_PISCR
+ hex "PISCR register"
+ help
+ Periodic Interrupt Status and Control (11-31)
+
+config SYS_PLPRCR_BOOL
+ bool "Customise PLPRCR"
+
+config SYS_PLPRCR
+ hex "PLPRCR register"
+ depends on SYS_PLPRCR_BOOL
+ help
+ PLL, Low-Power, and Reset Control Register (15-30)
+
+config SYS_SCCR
+ hex "SCCR register"
+ help
+ System Clock and reset Control Register (15-27)
+
+config SYS_SCCR_MASK
+ hex "MASK for setting SCCR register"
+
+config SYS_DER
+ hex "DER register"
+ help
+ Debug Event Register (37-47)
+
+comment "Memory mapping"
+
+config SYS_BR0_PRELIM
+ hex "Preliminary value for BR0"
+
+config SYS_OR0_PRELIM
+ hex "Preliminary value for OR0"
+
+config SYS_BR1_PRELIM_BOOL
+ bool "Define Bank 1"
+
+config SYS_BR1_PRELIM
+ hex "Preliminary value for BR1"
+ depends on SYS_BR1_PRELIM_BOOL
+
+config SYS_OR1_PRELIM
+ hex "Preliminary value for OR1"
+ depends on SYS_BR1_PRELIM_BOOL
+
+config SYS_BR2_PRELIM_BOOL
+ bool "Define Bank 2"
+
+config SYS_BR2_PRELIM
+ hex "Preliminary value for BR2"
+ depends on SYS_BR2_PRELIM_BOOL
+
+config SYS_OR2_PRELIM
+ hex "Preliminary value for OR2"
+ depends on SYS_BR2_PRELIM_BOOL
+
+config SYS_BR3_PRELIM_BOOL
+ bool "Define Bank 3"
+
+config SYS_BR3_PRELIM
+ hex "Preliminary value for BR3"
+ depends on SYS_BR3_PRELIM_BOOL
+
+config SYS_OR3_PRELIM
+ hex "Preliminary value for OR3"
+ depends on SYS_BR3_PRELIM_BOOL
+
+config SYS_BR4_PRELIM_BOOL
+ bool "Define Bank 4"
+
+config SYS_BR4_PRELIM
+ hex "Preliminary value for BR4"
+ depends on SYS_BR4_PRELIM_BOOL
+
+config SYS_OR4_PRELIM
+ hex "Preliminary value for OR4"
+ depends on SYS_BR4_PRELIM_BOOL
+
+config SYS_BR5_PRELIM_BOOL
+ bool "Define Bank 5"
+
+config SYS_BR5_PRELIM
+ hex "Preliminary value for BR5"
+ depends on SYS_BR5_PRELIM_BOOL
+
+config SYS_OR5_PRELIM
+ hex "Preliminary value for OR5"
+ depends on SYS_BR5_PRELIM_BOOL
+
+config SYS_BR6_PRELIM_BOOL
+ bool "Define Bank 6"
+
+config SYS_BR6_PRELIM
+ hex "Preliminary value for BR6"
+ depends on SYS_BR6_PRELIM_BOOL
+
+config SYS_OR6_PRELIM
+ hex "Preliminary value for OR6"
+ depends on SYS_BR6_PRELIM_BOOL
+
+config SYS_BR7_PRELIM_BOOL
+ bool "Define Bank 7"
+
+config SYS_BR7_PRELIM
+ hex "Preliminary value for BR7"
+ depends on SYS_BR7_PRELIM_BOOL
+
+config SYS_OR7_PRELIM
+ hex "Preliminary value for OR7"
+ depends on SYS_BR7_PRELIM_BOOL
+
+config SYS_IMMR
+ hex "Value for IMMR"
+
endmenu
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index 79b12b2408..010d1f8007 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -48,7 +48,7 @@ void cpu_init_f(immap_t __iomem *immr)
/* System integration timers. Don't change EBDF! (15-27) */
out_be32(&immr->im_clkrstk.cark_sccrk, KAPWR_KEY);
- clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK,
+ clrsetbits_be32(&immr->im_clkrst.car_sccr, ~CONFIG_SYS_SCCR_MASK,
CONFIG_SYS_SCCR);
/* BUG MPC866 GLL2 consideration */
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index f2ea0d1b8a..56cb7a506e 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -376,7 +376,7 @@ static void fec_pin_init(int fecidx)
out_be32(&immr->im_cpm.cp_fec1.fec_mii_speed,
((bd->bi_intfreq + 4999999) / 5000000) << 1);
-#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
+#if defined(CONFIG_MPC885) && defined(WANT_MII)
/* use MDC for MII */
setbits_be16(&immr->im_ioport.iop_pdpar, 0x0080);
clrbits_be16(&immr->im_ioport.iop_pddir, 0x0080);
@@ -385,7 +385,7 @@ static void fec_pin_init(int fecidx)
if (fecidx == 0) {
#if defined(CONFIG_ETHER_ON_FEC1)
-#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
+#if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
#if !defined(CONFIG_RMII)
@@ -435,7 +435,7 @@ static void fec_pin_init(int fecidx)
} else if (fecidx == 1) {
#if defined(CONFIG_ETHER_ON_FEC2)
-#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
+#if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
#if !defined(CONFIG_RMII)
setbits_be32(&immr->im_cpm.cp_pepar, 0x0003fffc);
@@ -460,7 +460,7 @@ static void fec_pin_init(int fecidx)
clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000028);
#endif /* CONFIG_RMII */
-#endif /* CONFIG_MPC885_FAMILY */
+#endif /* CONFIG_MPC885 */
#endif /* CONFIG_ETHER_ON_FEC2 */
}
diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h
index 9a8afe1132..c6aa2f0dfb 100644
--- a/arch/powerpc/include/asm/ppc.h
+++ b/arch/powerpc/include/asm/ppc.h
@@ -15,11 +15,6 @@
#if defined(CONFIG_8xx)
#include <asm/8xx_immap.h>
-#if defined(CONFIG_MPC866)
-# define CONFIG_MPC866_FAMILY 1
-#elif defined(CONFIG_MPC885)
-# define CONFIG_MPC885_FAMILY 1
-#endif
#endif
#ifdef CONFIG_MPC86xx
#include <mpc86xx.h>
diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c
index de3758d946..7c2282d731 100644
--- a/drivers/i2c/soft_i2c.c
+++ b/drivers/i2c/soft_i2c.c
@@ -28,7 +28,7 @@
#include <asm/arch/gpio.h>
#endif
#endif
-#if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866)
+#if defined(CONFIG_8xx)
#include <asm/io.h>
#endif
#include <i2c.h>
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 1a7bc674cc..dff46dd6a2 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -15,7 +15,6 @@ CONFIG_88F5182
CONFIG_8xx_CONS_NONE
CONFIG_8xx_CONS_SMC1
CONFIG_8xx_CONS_SMC2
-CONFIG_8xx_GCLK_FREQ
CONFIG_A003399_NOR_WORKAROUND
CONFIG_A008044_WORKAROUND
CONFIG_ACX517AKN
@@ -1543,10 +1542,6 @@ CONFIG_MPC83XX_PCI2
CONFIG_MPC85XX_FEC
CONFIG_MPC85XX_FEC_NAME
CONFIG_MPC85XX_PCI2
-CONFIG_MPC866
-CONFIG_MPC866_FAMILY
-CONFIG_MPC885
-CONFIG_MPC885_FAMILY
CONFIG_MPC8XXX_SPI
CONFIG_MPC8xxx_DISABLE_BPTR
CONFIG_MPLL_FREQ
@@ -2934,7 +2929,6 @@ CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
CONFIG_SYS_DEFAULT_VIDEO_MODE
CONFIG_SYS_DEF_EEPROM_ADDR
-CONFIG_SYS_DER
CONFIG_SYS_DEVICE_NULLDEV
CONFIG_SYS_DFU_DATA_BUF_SIZE
CONFIG_SYS_DFU_MAX_FILE_SIZE
@@ -4508,7 +4502,6 @@ CONFIG_SYS_PIOC_PPUDR_VAL
CONFIG_SYS_PIOD_PDR_VAL1
CONFIG_SYS_PIOD_PPUDR_VAL
CONFIG_SYS_PIO_MODE
-CONFIG_SYS_PISCR
CONFIG_SYS_PIT_BASE
CONFIG_SYS_PIT_PRESCALE
CONFIG_SYS_PIXIS_VBOOT_ENABLE
@@ -4530,7 +4523,6 @@ CONFIG_SYS_PLL_BYPASS
CONFIG_SYS_PLL_FDR
CONFIG_SYS_PLL_ODR
CONFIG_SYS_PLL_SETTLING_TIME
-CONFIG_SYS_PLPRCR
CONFIG_SYS_PLUG_BASE
CONFIG_SYS_PMAN
CONFIG_SYS_PMC_BASE
@@ -4760,7 +4752,6 @@ CONFIG_SYS_SH_SDHI_NR_CHANNEL
CONFIG_SYS_SICRH
CONFIG_SYS_SICRL
CONFIG_SYS_SIL1178_I2C
-CONFIG_SYS_SIUMCR
CONFIG_SYS_SJA1000_BASE
CONFIG_SYS_SMC0_CYCLE0_VAL
CONFIG_SYS_SMC0_MODE0_VAL
@@ -4832,11 +4823,9 @@ CONFIG_SYS_STATUS_OK
CONFIG_SYS_STMICRO_BOOT
CONFIG_SYS_SUPPORT_64BIT_DATA
CONFIG_SYS_SXCNFG_VAL
-CONFIG_SYS_SYPCR
CONFIG_SYS_SYSTEMACE_BASE
CONFIG_SYS_SYSTEMACE_WIDTH
CONFIG_SYS_TBIPA_VALUE
-CONFIG_SYS_TBSCR
CONFIG_SYS_TCLK
CONFIG_SYS_TEXT_ADDR
CONFIG_SYS_TEXT_BASE_NOR
--
2.12.0
^ permalink raw reply related [flat|nested] 35+ messages in thread* [U-Boot] [PATCH v2 07/10] powerpc, 8xx: Migrate to Kconfig
2017-07-06 8:33 ` [U-Boot] [PATCH v2 07/10] powerpc, 8xx: Migrate to Kconfig Christophe Leroy
@ 2017-07-06 8:57 ` Bin Meng
2017-07-06 9:47 ` Heiko Schocher
2017-07-09 0:25 ` [U-Boot] [U-Boot,v2,07/10] " Tom Rini
2 siblings, 0 replies; 35+ messages in thread
From: Bin Meng @ 2017-07-06 8:57 UTC (permalink / raw)
To: u-boot
Hi Christophe,
On Thu, Jul 6, 2017 at 4:33 PM, Christophe Leroy
<christophe.leroy@c-s.fr> wrote:
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
> README | 15 ----
> arch/powerpc/cpu/mpc8xx/Kconfig | 148 +++++++++++++++++++++++++++++++++++++
> arch/powerpc/cpu/mpc8xx/cpu_init.c | 2 +-
> arch/powerpc/cpu/mpc8xx/fec.c | 8 +-
> arch/powerpc/include/asm/ppc.h | 5 --
> drivers/i2c/soft_i2c.c | 2 +-
> scripts/config_whitelist.txt | 11 ---
> 7 files changed, 154 insertions(+), 37 deletions(-)
>
> diff --git a/README b/README
> index c3ab481a56..030a452f9a 100644
> --- a/README
> +++ b/README
> @@ -328,9 +328,6 @@ The following options need to be configured:
> multiple fs option at one time
> for marvell soc family
>
> -- 8xx CPU Options: (if using an MPC8xx CPU)
> - CONFIG_8xx_GCLK_FREQ - CPU clock
> -
> - 85xx CPU Options:
> CONFIG_SYS_PPC64
>
> @@ -3993,16 +3990,6 @@ Low Level (hardware related) configuration options:
> point to an otherwise UNUSED address space between
> the top of RAM and the start of the PCI space.
>
> -- CONFIG_SYS_SIUMCR: SIU Module Configuration (11-6)
> -
> -- CONFIG_SYS_SYPCR: System Protection Control (11-9)
> -
> -- CONFIG_SYS_TBSCR: Time Base Status and Control (11-26)
> -
> -- CONFIG_SYS_PISCR: Periodic Interrupt Status and Control (11-31)
> -
> -- CONFIG_SYS_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30)
> -
> - CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)
>
> - CONFIG_SYS_OR_TIMING_SDRAM:
> @@ -4011,8 +3998,6 @@ Low Level (hardware related) configuration options:
> - CONFIG_SYS_MAMR_PTA:
> periodic timer for refresh
>
> -- CONFIG_SYS_DER: Debug Event Register (37-47)
> -
> - FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
> CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
> CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
> diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
> index cb15dc5ebc..9e1ad33c28 100644
> --- a/arch/powerpc/cpu/mpc8xx/Kconfig
> +++ b/arch/powerpc/cpu/mpc8xx/Kconfig
> @@ -10,6 +10,21 @@ choice
>
> endchoice
>
> +choice
> + prompt "CPU select"
> + default MPC866
> +
> +config MPC866
> + bool "MPC866"
> +
> +config MPC885
> + bool "MPC885"
> +
> +endchoice
> +
> +config 8xx_GCLK_FREQ
> + int "CPU GCLK Frequency"
> +
> comment "Specific commands"
>
> config CMD_IMMAP
> @@ -19,4 +34,137 @@ config CMD_IMMAP
>
> siuinfo - print System Interface Unit (SIU) registers
> memcinfo - print Memory Controller registers
> +
> +comment "Configuration Registers"
> +
> +config SYS_SIUMCR
> + hex "SIUMCR register"
> + help
> + SIU Module Configuration (11-6)
> +
> +config SYS_SYPCR
> + hex "SYPCR register"
> + help
> + System Protection Control (11-9)
> +
> +config SYS_TBSCR
> + hex "TBSCR register"
> + help
> + Time Base Status and Control (11-26)
> +
> +config SYS_PISCR
> + hex "PISCR register"
> + help
> + Periodic Interrupt Status and Control (11-31)
> +
> +config SYS_PLPRCR_BOOL
> + bool "Customise PLPRCR"
> +
> +config SYS_PLPRCR
> + hex "PLPRCR register"
> + depends on SYS_PLPRCR_BOOL
> + help
> + PLL, Low-Power, and Reset Control Register (15-30)
> +
> +config SYS_SCCR
> + hex "SCCR register"
> + help
> + System Clock and reset Control Register (15-27)
> +
> +config SYS_SCCR_MASK
> + hex "MASK for setting SCCR register"
> +
> +config SYS_DER
> + hex "DER register"
> + help
> + Debug Event Register (37-47)
> +
> +comment "Memory mapping"
> +
> +config SYS_BR0_PRELIM
> + hex "Preliminary value for BR0"
> +
> +config SYS_OR0_PRELIM
> + hex "Preliminary value for OR0"
> +
These are really register values and should be converted to use device
tree, instead of Kconfig options.
> +config SYS_BR1_PRELIM_BOOL
> + bool "Define Bank 1"
> +
> +config SYS_BR1_PRELIM
> + hex "Preliminary value for BR1"
> + depends on SYS_BR1_PRELIM_BOOL
> +
> +config SYS_OR1_PRELIM
> + hex "Preliminary value for OR1"
> + depends on SYS_BR1_PRELIM_BOOL
> +
> +config SYS_BR2_PRELIM_BOOL
> + bool "Define Bank 2"
> +
> +config SYS_BR2_PRELIM
> + hex "Preliminary value for BR2"
> + depends on SYS_BR2_PRELIM_BOOL
> +
> +config SYS_OR2_PRELIM
> + hex "Preliminary value for OR2"
> + depends on SYS_BR2_PRELIM_BOOL
> +
> +config SYS_BR3_PRELIM_BOOL
> + bool "Define Bank 3"
> +
> +config SYS_BR3_PRELIM
> + hex "Preliminary value for BR3"
> + depends on SYS_BR3_PRELIM_BOOL
> +
> +config SYS_OR3_PRELIM
> + hex "Preliminary value for OR3"
> + depends on SYS_BR3_PRELIM_BOOL
> +
> +config SYS_BR4_PRELIM_BOOL
> + bool "Define Bank 4"
> +
> +config SYS_BR4_PRELIM
> + hex "Preliminary value for BR4"
> + depends on SYS_BR4_PRELIM_BOOL
> +
> +config SYS_OR4_PRELIM
> + hex "Preliminary value for OR4"
> + depends on SYS_BR4_PRELIM_BOOL
> +
> +config SYS_BR5_PRELIM_BOOL
> + bool "Define Bank 5"
> +
> +config SYS_BR5_PRELIM
> + hex "Preliminary value for BR5"
> + depends on SYS_BR5_PRELIM_BOOL
> +
> +config SYS_OR5_PRELIM
> + hex "Preliminary value for OR5"
> + depends on SYS_BR5_PRELIM_BOOL
> +
> +config SYS_BR6_PRELIM_BOOL
> + bool "Define Bank 6"
> +
> +config SYS_BR6_PRELIM
> + hex "Preliminary value for BR6"
> + depends on SYS_BR6_PRELIM_BOOL
> +
> +config SYS_OR6_PRELIM
> + hex "Preliminary value for OR6"
> + depends on SYS_BR6_PRELIM_BOOL
> +
> +config SYS_BR7_PRELIM_BOOL
> + bool "Define Bank 7"
> +
> +config SYS_BR7_PRELIM
> + hex "Preliminary value for BR7"
> + depends on SYS_BR7_PRELIM_BOOL
> +
> +config SYS_OR7_PRELIM
> + hex "Preliminary value for OR7"
> + depends on SYS_BR7_PRELIM_BOOL
> +
> +config SYS_IMMR
> + hex "Value for IMMR"
> +
> endmenu
[snip]
Regards,
Bin
^ permalink raw reply [flat|nested] 35+ messages in thread
* [U-Boot] [PATCH v2 07/10] powerpc, 8xx: Migrate to Kconfig
2017-07-06 8:33 ` [U-Boot] [PATCH v2 07/10] powerpc, 8xx: Migrate to Kconfig Christophe Leroy
2017-07-06 8:57 ` Bin Meng
@ 2017-07-06 9:47 ` Heiko Schocher
2017-07-09 0:25 ` [U-Boot] [U-Boot,v2,07/10] " Tom Rini
2 siblings, 0 replies; 35+ messages in thread
From: Heiko Schocher @ 2017-07-06 9:47 UTC (permalink / raw)
To: u-boot
Hello Christophe,
Am 06.07.2017 um 10:33 schrieb Christophe Leroy:
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
> README | 15 ----
> arch/powerpc/cpu/mpc8xx/Kconfig | 148 +++++++++++++++++++++++++++++++++++++
> arch/powerpc/cpu/mpc8xx/cpu_init.c | 2 +-
> arch/powerpc/cpu/mpc8xx/fec.c | 8 +-
> arch/powerpc/include/asm/ppc.h | 5 --
> drivers/i2c/soft_i2c.c | 2 +-
> scripts/config_whitelist.txt | 11 ---
> 7 files changed, 154 insertions(+), 37 deletions(-)
Reviewed-by: Heiko Schocher <hs@denx.de>
bye,
Heiko
>
> diff --git a/README b/README
> index c3ab481a56..030a452f9a 100644
> --- a/README
> +++ b/README
> @@ -328,9 +328,6 @@ The following options need to be configured:
> multiple fs option at one time
> for marvell soc family
>
> -- 8xx CPU Options: (if using an MPC8xx CPU)
> - CONFIG_8xx_GCLK_FREQ - CPU clock
> -
> - 85xx CPU Options:
> CONFIG_SYS_PPC64
>
> @@ -3993,16 +3990,6 @@ Low Level (hardware related) configuration options:
> point to an otherwise UNUSED address space between
> the top of RAM and the start of the PCI space.
>
> -- CONFIG_SYS_SIUMCR: SIU Module Configuration (11-6)
> -
> -- CONFIG_SYS_SYPCR: System Protection Control (11-9)
> -
> -- CONFIG_SYS_TBSCR: Time Base Status and Control (11-26)
> -
> -- CONFIG_SYS_PISCR: Periodic Interrupt Status and Control (11-31)
> -
> -- CONFIG_SYS_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30)
> -
> - CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)
>
> - CONFIG_SYS_OR_TIMING_SDRAM:
> @@ -4011,8 +3998,6 @@ Low Level (hardware related) configuration options:
> - CONFIG_SYS_MAMR_PTA:
> periodic timer for refresh
>
> -- CONFIG_SYS_DER: Debug Event Register (37-47)
> -
> - FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
> CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
> CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
> diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
> index cb15dc5ebc..9e1ad33c28 100644
> --- a/arch/powerpc/cpu/mpc8xx/Kconfig
> +++ b/arch/powerpc/cpu/mpc8xx/Kconfig
> @@ -10,6 +10,21 @@ choice
>
> endchoice
>
> +choice
> + prompt "CPU select"
> + default MPC866
> +
> +config MPC866
> + bool "MPC866"
> +
> +config MPC885
> + bool "MPC885"
> +
> +endchoice
> +
> +config 8xx_GCLK_FREQ
> + int "CPU GCLK Frequency"
> +
> comment "Specific commands"
>
> config CMD_IMMAP
> @@ -19,4 +34,137 @@ config CMD_IMMAP
>
> siuinfo - print System Interface Unit (SIU) registers
> memcinfo - print Memory Controller registers
> +
> +comment "Configuration Registers"
> +
> +config SYS_SIUMCR
> + hex "SIUMCR register"
> + help
> + SIU Module Configuration (11-6)
> +
> +config SYS_SYPCR
> + hex "SYPCR register"
> + help
> + System Protection Control (11-9)
> +
> +config SYS_TBSCR
> + hex "TBSCR register"
> + help
> + Time Base Status and Control (11-26)
> +
> +config SYS_PISCR
> + hex "PISCR register"
> + help
> + Periodic Interrupt Status and Control (11-31)
> +
> +config SYS_PLPRCR_BOOL
> + bool "Customise PLPRCR"
> +
> +config SYS_PLPRCR
> + hex "PLPRCR register"
> + depends on SYS_PLPRCR_BOOL
> + help
> + PLL, Low-Power, and Reset Control Register (15-30)
> +
> +config SYS_SCCR
> + hex "SCCR register"
> + help
> + System Clock and reset Control Register (15-27)
> +
> +config SYS_SCCR_MASK
> + hex "MASK for setting SCCR register"
> +
> +config SYS_DER
> + hex "DER register"
> + help
> + Debug Event Register (37-47)
> +
> +comment "Memory mapping"
> +
> +config SYS_BR0_PRELIM
> + hex "Preliminary value for BR0"
> +
> +config SYS_OR0_PRELIM
> + hex "Preliminary value for OR0"
> +
> +config SYS_BR1_PRELIM_BOOL
> + bool "Define Bank 1"
> +
> +config SYS_BR1_PRELIM
> + hex "Preliminary value for BR1"
> + depends on SYS_BR1_PRELIM_BOOL
> +
> +config SYS_OR1_PRELIM
> + hex "Preliminary value for OR1"
> + depends on SYS_BR1_PRELIM_BOOL
> +
> +config SYS_BR2_PRELIM_BOOL
> + bool "Define Bank 2"
> +
> +config SYS_BR2_PRELIM
> + hex "Preliminary value for BR2"
> + depends on SYS_BR2_PRELIM_BOOL
> +
> +config SYS_OR2_PRELIM
> + hex "Preliminary value for OR2"
> + depends on SYS_BR2_PRELIM_BOOL
> +
> +config SYS_BR3_PRELIM_BOOL
> + bool "Define Bank 3"
> +
> +config SYS_BR3_PRELIM
> + hex "Preliminary value for BR3"
> + depends on SYS_BR3_PRELIM_BOOL
> +
> +config SYS_OR3_PRELIM
> + hex "Preliminary value for OR3"
> + depends on SYS_BR3_PRELIM_BOOL
> +
> +config SYS_BR4_PRELIM_BOOL
> + bool "Define Bank 4"
> +
> +config SYS_BR4_PRELIM
> + hex "Preliminary value for BR4"
> + depends on SYS_BR4_PRELIM_BOOL
> +
> +config SYS_OR4_PRELIM
> + hex "Preliminary value for OR4"
> + depends on SYS_BR4_PRELIM_BOOL
> +
> +config SYS_BR5_PRELIM_BOOL
> + bool "Define Bank 5"
> +
> +config SYS_BR5_PRELIM
> + hex "Preliminary value for BR5"
> + depends on SYS_BR5_PRELIM_BOOL
> +
> +config SYS_OR5_PRELIM
> + hex "Preliminary value for OR5"
> + depends on SYS_BR5_PRELIM_BOOL
> +
> +config SYS_BR6_PRELIM_BOOL
> + bool "Define Bank 6"
> +
> +config SYS_BR6_PRELIM
> + hex "Preliminary value for BR6"
> + depends on SYS_BR6_PRELIM_BOOL
> +
> +config SYS_OR6_PRELIM
> + hex "Preliminary value for OR6"
> + depends on SYS_BR6_PRELIM_BOOL
> +
> +config SYS_BR7_PRELIM_BOOL
> + bool "Define Bank 7"
> +
> +config SYS_BR7_PRELIM
> + hex "Preliminary value for BR7"
> + depends on SYS_BR7_PRELIM_BOOL
> +
> +config SYS_OR7_PRELIM
> + hex "Preliminary value for OR7"
> + depends on SYS_BR7_PRELIM_BOOL
> +
> +config SYS_IMMR
> + hex "Value for IMMR"
> +
> endmenu
> diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
> index 79b12b2408..010d1f8007 100644
> --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
> +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
> @@ -48,7 +48,7 @@ void cpu_init_f(immap_t __iomem *immr)
> /* System integration timers. Don't change EBDF! (15-27) */
>
> out_be32(&immr->im_clkrstk.cark_sccrk, KAPWR_KEY);
> - clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK,
> + clrsetbits_be32(&immr->im_clkrst.car_sccr, ~CONFIG_SYS_SCCR_MASK,
> CONFIG_SYS_SCCR);
>
> /* BUG MPC866 GLL2 consideration */
> diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
> index f2ea0d1b8a..56cb7a506e 100644
> --- a/arch/powerpc/cpu/mpc8xx/fec.c
> +++ b/arch/powerpc/cpu/mpc8xx/fec.c
> @@ -376,7 +376,7 @@ static void fec_pin_init(int fecidx)
> out_be32(&immr->im_cpm.cp_fec1.fec_mii_speed,
> ((bd->bi_intfreq + 4999999) / 5000000) << 1);
>
> -#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
> +#if defined(CONFIG_MPC885) && defined(WANT_MII)
> /* use MDC for MII */
> setbits_be16(&immr->im_ioport.iop_pdpar, 0x0080);
> clrbits_be16(&immr->im_ioport.iop_pddir, 0x0080);
> @@ -385,7 +385,7 @@ static void fec_pin_init(int fecidx)
> if (fecidx == 0) {
> #if defined(CONFIG_ETHER_ON_FEC1)
>
> -#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
> +#if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
>
> #if !defined(CONFIG_RMII)
>
> @@ -435,7 +435,7 @@ static void fec_pin_init(int fecidx)
> } else if (fecidx == 1) {
> #if defined(CONFIG_ETHER_ON_FEC2)
>
> -#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
> +#if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
>
> #if !defined(CONFIG_RMII)
> setbits_be32(&immr->im_cpm.cp_pepar, 0x0003fffc);
> @@ -460,7 +460,7 @@ static void fec_pin_init(int fecidx)
> clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000028);
> #endif /* CONFIG_RMII */
>
> -#endif /* CONFIG_MPC885_FAMILY */
> +#endif /* CONFIG_MPC885 */
>
> #endif /* CONFIG_ETHER_ON_FEC2 */
> }
> diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h
> index 9a8afe1132..c6aa2f0dfb 100644
> --- a/arch/powerpc/include/asm/ppc.h
> +++ b/arch/powerpc/include/asm/ppc.h
> @@ -15,11 +15,6 @@
>
> #if defined(CONFIG_8xx)
> #include <asm/8xx_immap.h>
> -#if defined(CONFIG_MPC866)
> -# define CONFIG_MPC866_FAMILY 1
> -#elif defined(CONFIG_MPC885)
> -# define CONFIG_MPC885_FAMILY 1
> -#endif
> #endif
> #ifdef CONFIG_MPC86xx
> #include <mpc86xx.h>
> diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c
> index de3758d946..7c2282d731 100644
> --- a/drivers/i2c/soft_i2c.c
> +++ b/drivers/i2c/soft_i2c.c
> @@ -28,7 +28,7 @@
> #include <asm/arch/gpio.h>
> #endif
> #endif
> -#if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866)
> +#if defined(CONFIG_8xx)
> #include <asm/io.h>
> #endif
> #include <i2c.h>
> diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
> index 1a7bc674cc..dff46dd6a2 100644
> --- a/scripts/config_whitelist.txt
> +++ b/scripts/config_whitelist.txt
> @@ -15,7 +15,6 @@ CONFIG_88F5182
> CONFIG_8xx_CONS_NONE
> CONFIG_8xx_CONS_SMC1
> CONFIG_8xx_CONS_SMC2
> -CONFIG_8xx_GCLK_FREQ
> CONFIG_A003399_NOR_WORKAROUND
> CONFIG_A008044_WORKAROUND
> CONFIG_ACX517AKN
> @@ -1543,10 +1542,6 @@ CONFIG_MPC83XX_PCI2
> CONFIG_MPC85XX_FEC
> CONFIG_MPC85XX_FEC_NAME
> CONFIG_MPC85XX_PCI2
> -CONFIG_MPC866
> -CONFIG_MPC866_FAMILY
> -CONFIG_MPC885
> -CONFIG_MPC885_FAMILY
> CONFIG_MPC8XXX_SPI
> CONFIG_MPC8xxx_DISABLE_BPTR
> CONFIG_MPLL_FREQ
> @@ -2934,7 +2929,6 @@ CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
> CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
> CONFIG_SYS_DEFAULT_VIDEO_MODE
> CONFIG_SYS_DEF_EEPROM_ADDR
> -CONFIG_SYS_DER
> CONFIG_SYS_DEVICE_NULLDEV
> CONFIG_SYS_DFU_DATA_BUF_SIZE
> CONFIG_SYS_DFU_MAX_FILE_SIZE
> @@ -4508,7 +4502,6 @@ CONFIG_SYS_PIOC_PPUDR_VAL
> CONFIG_SYS_PIOD_PDR_VAL1
> CONFIG_SYS_PIOD_PPUDR_VAL
> CONFIG_SYS_PIO_MODE
> -CONFIG_SYS_PISCR
> CONFIG_SYS_PIT_BASE
> CONFIG_SYS_PIT_PRESCALE
> CONFIG_SYS_PIXIS_VBOOT_ENABLE
> @@ -4530,7 +4523,6 @@ CONFIG_SYS_PLL_BYPASS
> CONFIG_SYS_PLL_FDR
> CONFIG_SYS_PLL_ODR
> CONFIG_SYS_PLL_SETTLING_TIME
> -CONFIG_SYS_PLPRCR
> CONFIG_SYS_PLUG_BASE
> CONFIG_SYS_PMAN
> CONFIG_SYS_PMC_BASE
> @@ -4760,7 +4752,6 @@ CONFIG_SYS_SH_SDHI_NR_CHANNEL
> CONFIG_SYS_SICRH
> CONFIG_SYS_SICRL
> CONFIG_SYS_SIL1178_I2C
> -CONFIG_SYS_SIUMCR
> CONFIG_SYS_SJA1000_BASE
> CONFIG_SYS_SMC0_CYCLE0_VAL
> CONFIG_SYS_SMC0_MODE0_VAL
> @@ -4832,11 +4823,9 @@ CONFIG_SYS_STATUS_OK
> CONFIG_SYS_STMICRO_BOOT
> CONFIG_SYS_SUPPORT_64BIT_DATA
> CONFIG_SYS_SXCNFG_VAL
> -CONFIG_SYS_SYPCR
> CONFIG_SYS_SYSTEMACE_BASE
> CONFIG_SYS_SYSTEMACE_WIDTH
> CONFIG_SYS_TBIPA_VALUE
> -CONFIG_SYS_TBSCR
> CONFIG_SYS_TCLK
> CONFIG_SYS_TEXT_ADDR
> CONFIG_SYS_TEXT_BASE_NOR
>
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 35+ messages in thread* [U-Boot] [U-Boot,v2,07/10] powerpc, 8xx: Migrate to Kconfig
2017-07-06 8:33 ` [U-Boot] [PATCH v2 07/10] powerpc, 8xx: Migrate to Kconfig Christophe Leroy
2017-07-06 8:57 ` Bin Meng
2017-07-06 9:47 ` Heiko Schocher
@ 2017-07-09 0:25 ` Tom Rini
2 siblings, 0 replies; 35+ messages in thread
From: Tom Rini @ 2017-07-09 0:25 UTC (permalink / raw)
To: u-boot
On Thu, Jul 06, 2017 at 10:33:21AM +0200, Christophe Leroy wrote:
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> Reviewed-by: Heiko Schocher <hs@denx.de>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [U-Boot] [PATCH v2 08/10] powerpc, 8xx: move FEC Ethernet driver in drivers/net
2017-07-06 8:33 [U-Boot] [PATCH v2 0/10] powerpc, 8xx: Modernise the 8xx Christophe Leroy
` (6 preceding siblings ...)
2017-07-06 8:33 ` [U-Boot] [PATCH v2 07/10] powerpc, 8xx: Migrate to Kconfig Christophe Leroy
@ 2017-07-06 8:33 ` Christophe Leroy
2017-07-06 8:54 ` Bin Meng
2017-07-09 0:25 ` [U-Boot] [U-Boot, v2, " Tom Rini
2017-07-06 8:33 ` [U-Boot] [PATCH v2 09/10] powerpc, 8xx: move SPI driver to drivers/spi/ Christophe Leroy
2017-07-06 8:33 ` [U-Boot] [PATCH v2 10/10] powerpc, 8xx: move Serial driver to drivers/serial/ Christophe Leroy
9 siblings, 2 replies; 35+ messages in thread
From: Christophe Leroy @ 2017-07-06 8:33 UTC (permalink / raw)
To: u-boot
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
README | 15 ------
arch/powerpc/cpu/mpc8xx/Makefile | 1 -
arch/powerpc/cpu/mpc8xx/cpu.c | 2 +-
drivers/net/Kconfig | 58 ++++++++++++++++++++++
drivers/net/Makefile | 1 +
.../cpu/mpc8xx/fec.c => drivers/net/mpc8xx_fec.c | 18 -------
scripts/config_whitelist.txt | 4 --
7 files changed, 60 insertions(+), 39 deletions(-)
rename arch/powerpc/cpu/mpc8xx/fec.c => drivers/net/mpc8xx_fec.c (97%)
diff --git a/README b/README
index 030a452f9a..0f204be0ca 100644
--- a/README
+++ b/README
@@ -4083,21 +4083,6 @@ Low Level (hardware related) configuration options:
Only for 83xx systems. If specified, then DDR should
be configured using CS0 and CS1 instead of CS2 and CS3.
-- CONFIG_ETHER_ON_FEC[12]
- Define to enable FEC[12] on a 8xx series processor.
-
-- CONFIG_FEC[12]_PHY
- Define to the hardcoded PHY address which corresponds
- to the given FEC; i. e.
- #define CONFIG_FEC1_PHY 4
- means that the PHY with address 4 is connected to FEC1
-
- When set to -1, means to probe for first available.
-
-- CONFIG_FEC[12]_PHY_NORXERR
- The PHY does not have a RXERR line (RMII only).
- (so program the FEC to ignore it).
-
- CONFIG_RMII
Enable RMII mode for all FECs.
Note that this is a global option, we can't
diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile
index b5b4bfafb9..f67c3f8463 100644
--- a/arch/powerpc/cpu/mpc8xx/Makefile
+++ b/arch/powerpc/cpu/mpc8xx/Makefile
@@ -9,7 +9,6 @@ extra-y += start.o
extra-y += traps.o
obj-y += cpu.o
obj-y += cpu_init.o
-obj-y += fec.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_CMD_IMMAP) += immap.o
obj-y += interrupts.o
diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c
index 5cfc8c189c..74e6c6d02c 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu.c
@@ -327,7 +327,7 @@ void reset_8xx_watchdog(immap_t __iomem *immr)
*/
int cpu_eth_init(bd_t *bis)
{
-#if defined(FEC_ENET)
+#if defined(CONFIG_MPC8XX_FEC)
fec_initialize(bis);
#endif
return 0;
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 33634c33d4..736aab2e6e 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -246,4 +246,62 @@ config RENESAS_RAVB
This driver implements support for the Ethernet AVB block in
Renesas M3 and H3 SoCs.
+config MPC8XX_FEC
+ bool "Fast Ethernet Controller on MPC8XX"
+ depends on 8xx
+ select MII
+ help
+ This driver implements support for the Fast Ethernet Controller
+ on MPC8XX
+
+config ETHER_ON_FEC1
+ bool "FEC1"
+ depends on MPC8XX_FEC
+ default y
+
+config FEC1_PHY
+ int "FEC1 PHY"
+ depends on ETHER_ON_FEC1
+ default -1
+ help
+ Define to the hardcoded PHY address which corresponds
+ to the given FEC; i. e.
+ #define CONFIG_FEC1_PHY 4
+ means that the PHY with address 4 is connected to FEC1
+
+ When set to -1, means to probe for first available.
+
+config PHY_NORXERR
+ bool "PHY_NORXERR"
+ depends on ETHER_ON_FEC1
+ default n
+ help
+ The PHY does not have a RXERR line (RMII only).
+ (so program the FEC to ignore it).
+
+config ETHER_ON_FEC2
+ bool "FEC2"
+ depends on MPC8XX_FEC && MPC885
+ default y
+
+config FEC2_PHY
+ int "FEC2 PHY"
+ depends on ETHER_ON_FEC2
+ default -1
+ help
+ Define to the hardcoded PHY address which corresponds
+ to the given FEC; i. e.
+ #define CONFIG_FEC1_PHY 4
+ means that the PHY with address 4 is connected to FEC1
+
+ When set to -1, means to probe for first available.
+
+config FEC2_PHY_NORXERR
+ bool "PHY_NORXERR"
+ depends on ETHER_ON_FEC2
+ default n
+ help
+ The PHY does not have a RXERR line (RMII only).
+ (so program the FEC to ignore it).
+
endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 4a5176e087..94a4fd8701 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_LAN91C96) += lan91c96.o
obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
obj-$(CONFIG_MACB) += macb.o
obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
+obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o
obj-$(CONFIG_MVGBE) += mvgbe.o
obj-$(CONFIG_MVNETA) += mvneta.o
obj-$(CONFIG_MVPP2) += mvpp2.o
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/drivers/net/mpc8xx_fec.c
similarity index 97%
rename from arch/powerpc/cpu/mpc8xx/fec.c
rename to drivers/net/mpc8xx_fec.c
index 56cb7a506e..b070d6696a 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/drivers/net/mpc8xx_fec.c
@@ -16,14 +16,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_CMD_NET) && \
- (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2))
-
-/* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */
-#if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2)
-#define CONFIG_ETHER_ON_FEC1 1
-#endif
-
/* define WANT_MII when MII support is required */
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
#define WANT_MII
@@ -65,11 +57,7 @@ static struct ether_fcc_info_s
{
0,
offsetof(immap_t, im_cpm.cp_fec1),
-#if defined(CONFIG_FEC1_PHY)
CONFIG_FEC1_PHY,
-#else
- -1, /* discover */
-#endif
-1,
0,
@@ -79,11 +67,7 @@ static struct ether_fcc_info_s
{
1,
offsetof(immap_t, im_cpm.cp_fec2),
-#if defined(CONFIG_FEC2_PHY)
CONFIG_FEC2_PHY,
-#else
- -1,
-#endif
-1,
0,
},
@@ -846,5 +830,3 @@ int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
return 0;
}
#endif
-
-#endif
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index dff46dd6a2..43b44025dd 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -712,8 +712,6 @@ CONFIG_ETHER_ON_FCC
CONFIG_ETHER_ON_FCC1
CONFIG_ETHER_ON_FCC2
CONFIG_ETHER_ON_FCC3
-CONFIG_ETHER_ON_FEC1
-CONFIG_ETHER_ON_FEC2
CONFIG_ETHPRIME
CONFIG_ETH_BUFSIZE
CONFIG_ETH_RXSIZE
@@ -769,8 +767,6 @@ CONFIG_FEATURE_SH_APPLETS_ALWAYS_WIN
CONFIG_FEATURE_SH_EXTRA_QUIET
CONFIG_FEATURE_SH_FANCY_PROMPT
CONFIG_FEATURE_SH_STANDALONE_SHELL
-CONFIG_FEC1_PHY
-CONFIG_FEC2_PHY
CONFIG_FEC_ENET_DEV
CONFIG_FEC_FIXED_SPEED
CONFIG_FEC_MXC_25M_REF_CLK
--
2.12.0
^ permalink raw reply related [flat|nested] 35+ messages in thread* [U-Boot] [PATCH v2 08/10] powerpc, 8xx: move FEC Ethernet driver in drivers/net
2017-07-06 8:33 ` [U-Boot] [PATCH v2 08/10] powerpc, 8xx: move FEC Ethernet driver in drivers/net Christophe Leroy
@ 2017-07-06 8:54 ` Bin Meng
2017-07-06 12:02 ` Tom Rini
2017-07-09 0:25 ` [U-Boot] [U-Boot, v2, " Tom Rini
1 sibling, 1 reply; 35+ messages in thread
From: Bin Meng @ 2017-07-06 8:54 UTC (permalink / raw)
To: u-boot
Hi Christophe,
On Thu, Jul 6, 2017 at 4:33 PM, Christophe Leroy
<christophe.leroy@c-s.fr> wrote:
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
> README | 15 ------
> arch/powerpc/cpu/mpc8xx/Makefile | 1 -
> arch/powerpc/cpu/mpc8xx/cpu.c | 2 +-
> drivers/net/Kconfig | 58 ++++++++++++++++++++++
> drivers/net/Makefile | 1 +
> .../cpu/mpc8xx/fec.c => drivers/net/mpc8xx_fec.c | 18 -------
> scripts/config_whitelist.txt | 4 --
> 7 files changed, 60 insertions(+), 39 deletions(-)
> rename arch/powerpc/cpu/mpc8xx/fec.c => drivers/net/mpc8xx_fec.c (97%)
>
I've seen all previous discussion on this 8xx support. But since you
are modernising 8xx support, can you convert this driver to DM
instead? We should not add any new legacy driver any more.
[snip]
Regards,
Bin
^ permalink raw reply [flat|nested] 35+ messages in thread
* [U-Boot] [PATCH v2 08/10] powerpc, 8xx: move FEC Ethernet driver in drivers/net
2017-07-06 8:54 ` Bin Meng
@ 2017-07-06 12:02 ` Tom Rini
0 siblings, 0 replies; 35+ messages in thread
From: Tom Rini @ 2017-07-06 12:02 UTC (permalink / raw)
To: u-boot
On Thu, Jul 06, 2017 at 04:54:59PM +0800, Bin Meng wrote:
> Hi Christophe,
>
> On Thu, Jul 6, 2017 at 4:33 PM, Christophe Leroy
> <christophe.leroy@c-s.fr> wrote:
> > Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> > ---
> > README | 15 ------
> > arch/powerpc/cpu/mpc8xx/Makefile | 1 -
> > arch/powerpc/cpu/mpc8xx/cpu.c | 2 +-
> > drivers/net/Kconfig | 58 ++++++++++++++++++++++
> > drivers/net/Makefile | 1 +
> > .../cpu/mpc8xx/fec.c => drivers/net/mpc8xx_fec.c | 18 -------
> > scripts/config_whitelist.txt | 4 --
> > 7 files changed, 60 insertions(+), 39 deletions(-)
> > rename arch/powerpc/cpu/mpc8xx/fec.c => drivers/net/mpc8xx_fec.c (97%)
>
> I've seen all previous discussion on this 8xx support. But since you
> are modernising 8xx support, can you convert this driver to DM
> instead? We should not add any new legacy driver any more.
This is why I was saying incremental change in the -rc3 announcement.
This code will be updated to modern requirements. But it (being the
parts that are still used) will come in, get moved, then get converted.
Or out it goes again :)
--
Tom
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [U-Boot] [U-Boot, v2, 08/10] powerpc, 8xx: move FEC Ethernet driver in drivers/net
2017-07-06 8:33 ` [U-Boot] [PATCH v2 08/10] powerpc, 8xx: move FEC Ethernet driver in drivers/net Christophe Leroy
2017-07-06 8:54 ` Bin Meng
@ 2017-07-09 0:25 ` Tom Rini
1 sibling, 0 replies; 35+ messages in thread
From: Tom Rini @ 2017-07-09 0:25 UTC (permalink / raw)
To: u-boot
On Thu, Jul 06, 2017 at 10:33:23AM +0200, Christophe Leroy wrote:
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 35+ messages in thread
* [U-Boot] [PATCH v2 09/10] powerpc, 8xx: move SPI driver to drivers/spi/
2017-07-06 8:33 [U-Boot] [PATCH v2 0/10] powerpc, 8xx: Modernise the 8xx Christophe Leroy
` (7 preceding siblings ...)
2017-07-06 8:33 ` [U-Boot] [PATCH v2 08/10] powerpc, 8xx: move FEC Ethernet driver in drivers/net Christophe Leroy
@ 2017-07-06 8:33 ` Christophe Leroy
2017-07-09 0:25 ` [U-Boot] [U-Boot, v2, " Tom Rini
2017-07-06 8:33 ` [U-Boot] [PATCH v2 10/10] powerpc, 8xx: move Serial driver to drivers/serial/ Christophe Leroy
9 siblings, 1 reply; 35+ messages in thread
From: Christophe Leroy @ 2017-07-06 8:33 UTC (permalink / raw)
To: u-boot
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/cpu/mpc8xx/Makefile | 1 -
drivers/spi/Kconfig | 6 ++++++
drivers/spi/Makefile | 1 +
arch/powerpc/cpu/mpc8xx/spi.c => drivers/spi/mpc8xx_spi.c | 3 ---
4 files changed, 7 insertions(+), 4 deletions(-)
rename arch/powerpc/cpu/mpc8xx/spi.c => drivers/spi/mpc8xx_spi.c (99%)
diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile
index f67c3f8463..173cf01869 100644
--- a/arch/powerpc/cpu/mpc8xx/Makefile
+++ b/arch/powerpc/cpu/mpc8xx/Makefile
@@ -15,4 +15,3 @@ obj-y += interrupts.o
obj-$(CONFIG_CMD_REGINFO) += reginfo.o
obj-y += serial.o
obj-y += speed.o
-obj-y += spi.o
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index bef864f46e..03d0c05f23 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -223,4 +223,10 @@ config TI_QSPI
Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
This driver support spi flash single, quad and memory reads.
+config MPC8XX_SPI
+ bool "MPC8XX SPI Driver"
+ depends on 8xx
+ help
+ Enable support for SPI on MPC8XX
+
endmenu # menu "SPI Support"
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index c090562c77..9f8b86de76 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
+obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
diff --git a/arch/powerpc/cpu/mpc8xx/spi.c b/drivers/spi/mpc8xx_spi.c
similarity index 99%
rename from arch/powerpc/cpu/mpc8xx/spi.c
rename to drivers/spi/mpc8xx_spi.c
index 6e3e86fb0f..b5bd558526 100644
--- a/arch/powerpc/cpu/mpc8xx/spi.c
+++ b/drivers/spi/mpc8xx_spi.c
@@ -25,8 +25,6 @@
#include <post.h>
#include <serial.h>
-#ifdef CONFIG_SPI
-
#define SPI_EEPROM_WREN 0x06
#define SPI_EEPROM_RDSR 0x05
#define SPI_EEPROM_READ 0x03
@@ -336,4 +334,3 @@ ssize_t spi_xfer(size_t count)
return count;
}
-#endif /* CONFIG_SPI */
--
2.12.0
^ permalink raw reply related [flat|nested] 35+ messages in thread* [U-Boot] [PATCH v2 10/10] powerpc, 8xx: move Serial driver to drivers/serial/
2017-07-06 8:33 [U-Boot] [PATCH v2 0/10] powerpc, 8xx: Modernise the 8xx Christophe Leroy
` (8 preceding siblings ...)
2017-07-06 8:33 ` [U-Boot] [PATCH v2 09/10] powerpc, 8xx: move SPI driver to drivers/spi/ Christophe Leroy
@ 2017-07-06 8:33 ` Christophe Leroy
2017-07-09 0:25 ` [U-Boot] [U-Boot, v2, " Tom Rini
9 siblings, 1 reply; 35+ messages in thread
From: Christophe Leroy @ 2017-07-06 8:33 UTC (permalink / raw)
To: u-boot
At the same time, move to Kconfig
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
README | 19 --------
arch/powerpc/cpu/mpc8xx/Makefile | 1 -
drivers/serial/Kconfig | 53 ++++++++++++++++++++++
drivers/serial/Makefile | 1 +
.../serial.c => drivers/serial/serial_mpc8xx.c | 23 ----------
scripts/config_whitelist.txt | 7 ---
6 files changed, 54 insertions(+), 50 deletions(-)
rename arch/powerpc/cpu/mpc8xx/serial.c => drivers/serial/serial_mpc8xx.c (93%)
diff --git a/README b/README
index 0f204be0ca..c5ddf326b3 100644
--- a/README
+++ b/README
@@ -691,29 +691,10 @@ The following options need to be configured:
Define this variable to enable hw flow control in serial driver.
Current user of this option is drivers/serial/nsl16550.c driver
-- Console Interface:
- Depending on board, define exactly one serial port
- (CONFIG_8xx_CONS_SMC1 or CONFIG_8xx_CONS_SMC2),
- or switch off the serial console by defining
- CONFIG_8xx_CONS_NONE
-
- Note: if CONFIG_8xx_CONS_NONE is defined, the serial
- port routines must be defined elsewhere
- (i.e. serial_init(), serial_getc(), ...)
-
- Console Baudrate:
CONFIG_BAUDRATE - in bps
Select one of the baudrates listed in
CONFIG_SYS_BAUDRATE_TABLE, see below.
- CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale
-
-- Console Rx buffer length
- With CONFIG_SYS_SMC_RXBUFLEN it is possible to define
- the maximum receive buffer length for the SMC.
- This option is actual only for 8xx possible.
- If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE
- must be defined, to setup the maximum idle timeout for
- the SMC.
- Autoboot Command:
CONFIG_BOOTCOMMAND
diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile
index 173cf01869..b40bffb047 100644
--- a/arch/powerpc/cpu/mpc8xx/Makefile
+++ b/arch/powerpc/cpu/mpc8xx/Makefile
@@ -13,5 +13,4 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_CMD_IMMAP) += immap.o
obj-y += interrupts.o
obj-$(CONFIG_CMD_REGINFO) += reginfo.o
-obj-y += serial.o
obj-y += speed.o
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index c64f4a6d7b..b7dd2ac103 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -491,4 +491,57 @@ config STI_ASC_SERIAL
on STiH410 SoC. This is a basic implementation, it supports
following baudrate 9600, 19200, 38400, 57600 and 115200.
+config MPC8XX_CONS
+ bool "Console driver for MPC8XX"
+ depends on 8xx
+ default y
+
+choice
+ prompt "Console port"
+ default 8xx_CONS_SMC1
+ depends on MPC8XX_CONS
+ help
+ Depending on board, select one serial port
+ (CONFIG_8xx_CONS_SMC1 or CONFIG_8xx_CONS_SMC2)
+
+config 8xx_CONS_SMC1
+ bool "SMC1"
+
+config 8xx_CONS_SMC2
+ bool "SMC2"
+
+endchoice
+
+config SYS_SMC_RXBUFLEN
+ int "Console Rx buffer length"
+ depends on MPC8XX_CONS
+ default 1
+ help
+ With CONFIG_SYS_SMC_RXBUFLEN it is possible to define
+ the maximum receive buffer length for the SMC.
+ This option is actual only for 8xx possible.
+ If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE
+ must be defined, to setup the maximum idle timeout for
+ the SMC.
+
+config SYS_MAXIDLE
+ int "maximum idle timeout"
+ depends on MPC8XX_CONS
+ default 0
+
+config SYS_BRGCLK_PRESCALE
+ int "BRG Clock Prescale"
+ depends on MPC8XX_CONS
+ default 1
+
+config SYS_SDSR
+ hex "SDSR Value"
+ depends on MPC8XX_CONS
+ default 0x83
+
+config SYS_SDMR
+ hex "SDMR Value"
+ depends on MPC8XX_CONS
+ default 0
+
endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index dca31b295c..72a6996a0a 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o
obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o
obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
+obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/drivers/serial/serial_mpc8xx.c
similarity index 93%
rename from arch/powerpc/cpu/mpc8xx/serial.c
rename to drivers/serial/serial_mpc8xx.c
index 114dfe9b4b..26a8085a69 100644
--- a/arch/powerpc/cpu/mpc8xx/serial.c
+++ b/drivers/serial/serial_mpc8xx.c
@@ -14,8 +14,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
-
#if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
#define SMC_INDEX 0
#define PROFF_SMC PROFF_SMC1
@@ -30,15 +28,6 @@ DECLARE_GLOBAL_DATA_PTR;
#endif /* CONFIG_8xx_CONS_SMCx */
-#if !defined(CONFIG_SYS_SMC_RXBUFLEN)
-#define CONFIG_SYS_SMC_RXBUFLEN 1
-#define CONFIG_SYS_MAXIDLE 0
-#else
-#if !defined(CONFIG_SYS_MAXIDLE)
-#error "you must define CONFIG_SYS_MAXIDLE"
-#endif
-#endif
-
struct serialbuffer {
cbd_t rxbd; /* Rx BD */
cbd_t txbd; /* Tx BD */
@@ -56,9 +45,7 @@ static void serial_setdivisor(cpm8xx_t __iomem *cp)
divisor = (50 * 1000 * 1000 + 8 * 9600) / 16 / 9600;
}
-#ifdef CONFIG_SYS_BRGCLK_PRESCALE
divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
-#endif
if (divisor <= 0x1000)
out_be32(&cp->cp_brgc1, ((divisor - 1) << 1) | CPM_BRG_EN);
@@ -110,18 +97,10 @@ static int smc_init(void)
out_be32(&im->im_siu_conf.sc_sdcr, 1);
/* clear error conditions */
-#ifdef CONFIG_SYS_SDSR
out_8(&im->im_sdma.sdma_sdsr, CONFIG_SYS_SDSR);
-#else
- out_8(&im->im_sdma.sdma_sdsr, 0x83);
-#endif
/* clear SDMA interrupt mask */
-#ifdef CONFIG_SYS_SDMR
out_8(&im->im_sdma.sdma_sdmr, CONFIG_SYS_SDMR);
-#else
- out_8(&im->im_sdma.sdma_sdmr, 0x00);
-#endif
/* Use Port B for SMCx instead of other functions. */
setbits_be32(&cp->cp_pbpar, IOPINS);
@@ -275,5 +254,3 @@ void mpc8xx_serial_initialize(void)
{
serial_register(&serial_smc_device);
}
-
-#endif /* CONFIG_8xx_CONS_NONE */
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 43b44025dd..95f27b6ead 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -12,9 +12,6 @@ CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
CONFIG_83XX_PCICLK
CONFIG_83XX_PCI_STREAMING
CONFIG_88F5182
-CONFIG_8xx_CONS_NONE
-CONFIG_8xx_CONS_SMC1
-CONFIG_8xx_CONS_SMC2
CONFIG_A003399_NOR_WORKAROUND
CONFIG_A008044_WORKAROUND
CONFIG_ACX517AKN
@@ -2518,7 +2515,6 @@ CONFIG_SYS_BR6_64M
CONFIG_SYS_BR6_8M
CONFIG_SYS_BR6_PRELIM
CONFIG_SYS_BR7_PRELIM
-CONFIG_SYS_BRGCLK_PRESCALE
CONFIG_SYS_BUSCLK
CONFIG_SYS_CACHELINE_SHIFT
CONFIG_SYS_CACHE_ACR0
@@ -4675,7 +4671,6 @@ CONFIG_SYS_SDIO_BASE0
CONFIG_SYS_SDIO_BASE1
CONFIG_SYS_SDIO_BASE2
CONFIG_SYS_SDIO_BASE3
-CONFIG_SYS_SDMR
CONFIG_SYS_SDRAM
CONFIG_SYS_SDRAM1
CONFIG_SYS_SDRAM_BASE
@@ -4721,7 +4716,6 @@ CONFIG_SYS_SDRC_MR_VAL5
CONFIG_SYS_SDRC_TR_VAL
CONFIG_SYS_SDRC_TR_VAL1
CONFIG_SYS_SDRC_TR_VAL2
-CONFIG_SYS_SDSR
CONFIG_SYS_SD_VOLTAGE
CONFIG_SYS_SEC_MON_ADDR
CONFIG_SYS_SEC_MON_OFFSET
@@ -4754,7 +4748,6 @@ CONFIG_SYS_SMC0_MODE0_VAL
CONFIG_SYS_SMC0_PULSE0_VAL
CONFIG_SYS_SMC0_SETUP0_VAL
CONFIG_SYS_SMC_CSR0_VAL
-CONFIG_SYS_SMC_RXBUFLEN
CONFIG_SYS_SMI_BASE
CONFIG_SYS_SPANSION_BASE
CONFIG_SYS_SPANSION_BOOT
--
2.12.0
^ permalink raw reply related [flat|nested] 35+ messages in thread* [U-Boot] [U-Boot, v2, 10/10] powerpc, 8xx: move Serial driver to drivers/serial/
2017-07-06 8:33 ` [U-Boot] [PATCH v2 10/10] powerpc, 8xx: move Serial driver to drivers/serial/ Christophe Leroy
@ 2017-07-09 0:25 ` Tom Rini
0 siblings, 0 replies; 35+ messages in thread
From: Tom Rini @ 2017-07-09 0:25 UTC (permalink / raw)
To: u-boot
On Thu, Jul 06, 2017 at 10:33:27AM +0200, Christophe Leroy wrote:
> At the same time, move to Kconfig
>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 35+ messages in thread