[U-Boot] [PATCH v2 07/10] powerpc, 8xx: Migrate to Kconfig

Christophe Leroy
2017-07-06T08:33:21Z

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
README | 15 ----
arch/powerpc/cpu/mpc8xx/Kconfig | 148 +++++++++++++++++++++++++++++++++++++
arch/powerpc/cpu/mpc8xx/cpu_init.c | 2 +-
arch/powerpc/cpu/mpc8xx/fec.c | 8 +-
arch/powerpc/include/asm/ppc.h | 5 --
drivers/i2c/soft_i2c.c | 2 +-
scripts/config_whitelist.txt | 11 ---
7 files changed, 154 insertions(+), 37 deletions(-)

diff --git a/README b/README
index c3ab481a56..030a452f9a 100644
--- a/README
+++ b/README
@@ -328,9 +328,6 @@ The following options need to be configured:
multiple fs option at one time
for marvell soc family

-- 8xx CPU Options: (if using an MPC8xx CPU)
- CONFIG_8xx_GCLK_FREQ - CPU clock
-
- 85xx CPU Options:
CONFIG_SYS_PPC64

@@ -3993,16 +3990,6 @@ Low Level (hardware related) configuration options:
point to an otherwise UNUSED address space between
the top of RAM and the start of the PCI space.

-- CONFIG_SYS_SIUMCR: SIU Module Configuration (11-6)
-
-- CONFIG_SYS_SYPCR: System Protection Control (11-9)
-
-- CONFIG_SYS_TBSCR: Time Base Status and Control (11-26)
-
-- CONFIG_SYS_PISCR: Periodic Interrupt Status and Control (11-31)
-
-- CONFIG_SYS_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30)
-
- CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)

- CONFIG_SYS_OR_TIMING_SDRAM:
@@ -4011,8 +3998,6 @@ Low Level (hardware related) configuration options:
- CONFIG_SYS_MAMR_PTA:
periodic timer for refresh

-- CONFIG_SYS_DER: Debug Event Register (37-47)
-
- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index cb15dc5ebc..9e1ad33c28 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -10,6 +10,21 @@ choice

endchoice

+choice
+ prompt "CPU select"
+ default MPC866
+
+config MPC866
+ bool "MPC866"
+
+config MPC885
+ bool "MPC885"
+
+endchoice
+
+config 8xx_GCLK_FREQ
+ int "CPU GCLK Frequency"
+
comment "Specific commands"

config CMD_IMMAP
@@ -19,4 +34,137 @@ config CMD_IMMAP

siuinfo - print System Interface Unit (SIU) registers
memcinfo - print Memory Controller registers
+
+comment "Configuration Registers"
+
+config SYS_SIUMCR
+ hex "SIUMCR register"
+ help
+ SIU Module Configuration (11-6)
+
+config SYS_SYPCR
+ hex "SYPCR register"
+ help
+ System Protection Control (11-9)
+
+config SYS_TBSCR
+ hex "TBSCR register"
+ help
+ Time Base Status and Control (11-26)
+
+config SYS_PISCR
+ hex "PISCR register"
+ help
+ Periodic Interrupt Status and Control (11-31)
+
+config SYS_PLPRCR_BOOL
+ bool "Customise PLPRCR"
+
+config SYS_PLPRCR
+ hex "PLPRCR register"
+ depends on SYS_PLPRCR_BOOL
+ help
+ PLL, Low-Power, and Reset Control Register (15-30)
+
+config SYS_SCCR
+ hex "SCCR register"
+ help
+ System Clock and reset Control Register (15-27)
+
+config SYS_SCCR_MASK
+ hex "MASK for setting SCCR register"
+
+config SYS_DER
+ hex "DER register"
+ help
+ Debug Event Register (37-47)
+
+comment "Memory mapping"
+
+config SYS_BR0_PRELIM
+ hex "Preliminary value for BR0"
+
+config SYS_OR0_PRELIM
+ hex "Preliminary value for OR0"
+
+config SYS_BR1_PRELIM_BOOL
+ bool "Define Bank 1"
+
+config SYS_BR1_PRELIM
+ hex "Preliminary value for BR1"
+ depends on SYS_BR1_PRELIM_BOOL
+
+config SYS_OR1_PRELIM
+ hex "Preliminary value for OR1"
+ depends on SYS_BR1_PRELIM_BOOL
+
+config SYS_BR2_PRELIM_BOOL
+ bool "Define Bank 2"
+
+config SYS_BR2_PRELIM
+ hex "Preliminary value for BR2"
+ depends on SYS_BR2_PRELIM_BOOL
+
+config SYS_OR2_PRELIM
+ hex "Preliminary value for OR2"
+ depends on SYS_BR2_PRELIM_BOOL
+
+config SYS_BR3_PRELIM_BOOL
+ bool "Define Bank 3"
+
+config SYS_BR3_PRELIM
+ hex "Preliminary value for BR3"
+ depends on SYS_BR3_PRELIM_BOOL
+
+config SYS_OR3_PRELIM
+ hex "Preliminary value for OR3"
+ depends on SYS_BR3_PRELIM_BOOL
+
+config SYS_BR4_PRELIM_BOOL
+ bool "Define Bank 4"
+
+config SYS_BR4_PRELIM
+ hex "Preliminary value for BR4"
+ depends on SYS_BR4_PRELIM_BOOL
+
+config SYS_OR4_PRELIM
+ hex "Preliminary value for OR4"
+ depends on SYS_BR4_PRELIM_BOOL
+
+config SYS_BR5_PRELIM_BOOL
+ bool "Define Bank 5"
+
+config SYS_BR5_PRELIM
+ hex "Preliminary value for BR5"
+ depends on SYS_BR5_PRELIM_BOOL
+
+config SYS_OR5_PRELIM
+ hex "Preliminary value for OR5"
+ depends on SYS_BR5_PRELIM_BOOL
+
+config SYS_BR6_PRELIM_BOOL
+ bool "Define Bank 6"
+
+config SYS_BR6_PRELIM
+ hex "Preliminary value for BR6"
+ depends on SYS_BR6_PRELIM_BOOL
+
+config SYS_OR6_PRELIM
+ hex "Preliminary value for OR6"
+ depends on SYS_BR6_PRELIM_BOOL
+
+config SYS_BR7_PRELIM_BOOL
+ bool "Define Bank 7"
+
+config SYS_BR7_PRELIM
+ hex "Preliminary value for BR7"
+ depends on SYS_BR7_PRELIM_BOOL
+
+config SYS_OR7_PRELIM
+ hex "Preliminary value for OR7"
+ depends on SYS_BR7_PRELIM_BOOL
+
+config SYS_IMMR
+ hex "Value for IMMR"
+
endmenu
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index 79b12b2408..010d1f8007 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -48,7 +48,7 @@ void cpu_init_f(immap_t __iomem *immr)
/* System integration timers. Don't change EBDF! (15-27) */

out_be32(&immr->im_clkrstk.cark_sccrk, KAPWR_KEY);
- clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK,
+ clrsetbits_be32(&immr->im_clkrst.car_sccr, ~CONFIG_SYS_SCCR_MASK,
CONFIG_SYS_SCCR);

/* BUG MPC866 GLL2 consideration */
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index f2ea0d1b8a..56cb7a506e 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -376,7 +376,7 @@ static void fec_pin_init(int fecidx)
out_be32(&immr->im_cpm.cp_fec1.fec_mii_speed,
((bd->bi_intfreq + 4999999) / 5000000) << 1);

-#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
+#if defined(CONFIG_MPC885) && defined(WANT_MII)
/* use MDC for MII */
setbits_be16(&immr->im_ioport.iop_pdpar, 0x0080);
clrbits_be16(&immr->im_ioport.iop_pddir, 0x0080);
@@ -385,7 +385,7 @@ static void fec_pin_init(int fecidx)
if (fecidx == 0) {
#if defined(CONFIG_ETHER_ON_FEC1)

-#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
+#if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */

#if !defined(CONFIG_RMII)

@@ -435,7 +435,7 @@ static void fec_pin_init(int fecidx)
} else if (fecidx == 1) {
#if defined(CONFIG_ETHER_ON_FEC2)

-#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
+#if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */

#if !defined(CONFIG_RMII)
setbits_be32(&immr->im_cpm.cp_pepar, 0x0003fffc);
@@ -460,7 +460,7 @@ static void fec_pin_init(int fecidx)
clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000028);
#endif /* CONFIG_RMII */

-#endif /* CONFIG_MPC885_FAMILY */
+#endif /* CONFIG_MPC885 */

#endif /* CONFIG_ETHER_ON_FEC2 */
}
diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h
index 9a8afe1132..c6aa2f0dfb 100644
--- a/arch/powerpc/include/asm/ppc.h
+++ b/arch/powerpc/include/asm/ppc.h
@@ -15,11 +15,6 @@

#if defined(CONFIG_8xx)
#include <asm/8xx_immap.h>
-#if defined(CONFIG_MPC866)
-# define CONFIG_MPC866_FAMILY 1
-#elif defined(CONFIG_MPC885)
-# define CONFIG_MPC885_FAMILY 1
-#endif
#endif
#ifdef CONFIG_MPC86xx
#include <mpc86xx.h>
diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c
index de3758d946..7c2282d731 100644
--- a/drivers/i2c/soft_i2c.c
+++ b/drivers/i2c/soft_i2c.c
@@ -28,7 +28,7 @@
#include <asm/arch/gpio.h>
#endif
#endif
-#if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866)
+#if defined(CONFIG_8xx)
#include <asm/io.h>
#endif
#include <i2c.h>
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 1a7bc674cc..dff46dd6a2 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -15,7 +15,6 @@ CONFIG_88F5182
CONFIG_8xx_CONS_NONE
CONFIG_8xx_CONS_SMC1
CONFIG_8xx_CONS_SMC2
-CONFIG_8xx_GCLK_FREQ
CONFIG_A003399_NOR_WORKAROUND
CONFIG_A008044_WORKAROUND
CONFIG_ACX517AKN
@@ -1543,10 +1542,6 @@ CONFIG_MPC83XX_PCI2
CONFIG_MPC85XX_FEC
CONFIG_MPC85XX_FEC_NAME
CONFIG_MPC85XX_PCI2
-CONFIG_MPC866
-CONFIG_MPC866_FAMILY
-CONFIG_MPC885
-CONFIG_MPC885_FAMILY
CONFIG_MPC8XXX_SPI
CONFIG_MPC8xxx_DISABLE_BPTR
CONFIG_MPLL_FREQ
@@ -2934,7 +2929,6 @@ CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
CONFIG_SYS_DEFAULT_VIDEO_MODE
CONFIG_SYS_DEF_EEPROM_ADDR
-CONFIG_SYS_DER
CONFIG_SYS_DEVICE_NULLDEV
CONFIG_SYS_DFU_DATA_BUF_SIZE
CONFIG_SYS_DFU_MAX_FILE_SIZE
@@ -4508,7 +4502,6 @@ CONFIG_SYS_PIOC_PPUDR_VAL
CONFIG_SYS_PIOD_PDR_VAL1
CONFIG_SYS_PIOD_PPUDR_VAL
CONFIG_SYS_PIO_MODE
-CONFIG_SYS_PISCR
CONFIG_SYS_PIT_BASE
CONFIG_SYS_PIT_PRESCALE
CONFIG_SYS_PIXIS_VBOOT_ENABLE
@@ -4530,7 +4523,6 @@ CONFIG_SYS_PLL_BYPASS
CONFIG_SYS_PLL_FDR
CONFIG_SYS_PLL_ODR
CONFIG_SYS_PLL_SETTLING_TIME
-CONFIG_SYS_PLPRCR
CONFIG_SYS_PLUG_BASE
CONFIG_SYS_PMAN
CONFIG_SYS_PMC_BASE
@@ -4760,7 +4752,6 @@ CONFIG_SYS_SH_SDHI_NR_CHANNEL
CONFIG_SYS_SICRH
CONFIG_SYS_SICRL
CONFIG_SYS_SIL1178_I2C
-CONFIG_SYS_SIUMCR
CONFIG_SYS_SJA1000_BASE
CONFIG_SYS_SMC0_CYCLE0_VAL
CONFIG_SYS_SMC0_MODE0_VAL
@@ -4832,11 +4823,9 @@ CONFIG_SYS_STATUS_OK
CONFIG_SYS_STMICRO_BOOT
CONFIG_SYS_SUPPORT_64BIT_DATA
CONFIG_SYS_SXCNFG_VAL
-CONFIG_SYS_SYPCR
CONFIG_SYS_SYSTEMACE_BASE
CONFIG_SYS_SYSTEMACE_WIDTH
CONFIG_SYS_TBIPA_VALUE
-CONFIG_SYS_TBSCR
CONFIG_SYS_TCLK
CONFIG_SYS_TEXT_ADDR
CONFIG_SYS_TEXT_BASE_NOR
--
2.12.0