From mboxrd@z Thu Jan 1 00:00:00 1970 From: Heiko Schocher Date: Thu, 6 Jul 2017 11:43:01 +0200 Subject: [U-Boot] [PATCH v2 04/10] powerpc, 8xx: Implement GLL2 ERRATA In-Reply-To: <466a431b5430548a018c21222080ed4040596147.1499329461.git.christophe.leroy@c-s.fr> References: <466a431b5430548a018c21222080ed4040596147.1499329461.git.christophe.leroy@c-s.fr> Message-ID: <595E0625.1010805@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hello Christophe, Am 06.07.2017 um 10:33 schrieb Christophe Leroy: > Signed-off-by: Christophe Leroy > --- > arch/powerpc/cpu/mpc8xx/cpu_init.c | 8 ++++++++ > 1 file changed, 8 insertions(+) Reviewed-by: Heiko Schocher nitpick only > diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c > index cf1280983a..52406e8483 100644 > --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c > +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c > @@ -51,6 +51,14 @@ void cpu_init_f(immap_t __iomem *immr) > clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK, > CONFIG_SYS_SCCR); > > + /* BUG MPC866 GLL2 consideration */ > + reg = in_be32(&immr->im_clkrst.car_sccr); > + /* probably we use the mode 1:2:1 */ > + if ((reg & 0x00060000) == 0x00020000) { > + clrbits_be32(&immr->im_clkrst.car_sccr, 0x00060000); > + setbits_be32(&immr->im_clkrst.car_sccr, 0x00020000); You may can introduce defines for the magic values here. > + } > + > /* PLL (CPU clock) settings (15-30) */ > > out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY); > bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany