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[178.79.79.213]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48317d835f0sm953745e9.14.2026.02.04.10.18.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Feb 2026 10:18:58 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: u-boot@lists.denx.de, Paul Kocialkowski Cc: Tom Rini , Jagan Teki , Andre Przywara , Chen-Yu Tsai , Icenowy Zheng , Paul Kocialkowski Subject: Re: [PATCH v2 1/3] sunxi: a133: dram: Add NSI arbiter configuration support Date: Wed, 04 Feb 2026 18:33:29 +0100 Message-ID: <5961927.DvuYhMxLoT@jernej-laptop> In-Reply-To: <20260128235727.1322861-1-contact@paulk.fr> References: <20260128235727.1322861-1-contact@paulk.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Dne =C4=8Detrtek, 29. januar 2026 ob 00:57:15 Srednjeevropski standardni = =C4=8Das je Paul Kocialkowski napisal(a): > From: Paul Kocialkowski >=20 > In previous generations of Allwinner SoCs, the memory bus (MBUS) access > arbitration was configured as part of the DRAM top registers. This is no > longer the case starting with the A133, which has a dedicated base > address for the bus arbiter that is now called NSI instead of MBUS. >=20 > NSI appears to be a later iteration of MBUS design, with new dedicated > registers that resemble the previous MBUS ones. Despite NSI not being > documented in the manual, the A133 BSP includes a nsi driver with some > description of the registers. Like previous generations, it implements > port arbitration priority for DRAM access and also supports an optional > QoS mode based on bandwidth limits. >=20 > Configuring port arbitration priority is especially important to make > sure that critical masters are not starved by other less important > ones. This is especially the case with the display engine that needs > to be able to fetch pixels in time for scanout and can easily be > starved by CPU or GPU access. >=20 > This introduces support for the NSI arbiter in the A133 DRAM init > code. The list and order of available ports are highly SoC-specific > and the default config values are set to match the BSP's defaults. >=20 > Signed-off-by: Paul Kocialkowski > Sponsored-by: MEC Electronics GmbH This code looks good in general. However, since NSI seems common thing for newer SoCs (like A523, which is already included in U-Boot), I think it would be better to make some kind of NSI module instead of duplicating definitions for each SoCs. I dislike current MBUS approach, but that was done due to organic code growth without planning. Let's not repeat that here. Best regards, Jernej > --- > .../include/asm/arch-sunxi/cpu_sun50i_h6.h | 4 ++ > .../include/asm/arch-sunxi/dram_sun50i_a133.h | 36 ++++++++++ > arch/arm/mach-sunxi/dram_sun50i_a133.c | 67 ++++++++++++++++++- > 3 files changed, 106 insertions(+), 1 deletion(-) >=20 > diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/i= nclude/asm/arch-sunxi/cpu_sun50i_h6.h > index 2a9b086991c3..8e80c520706b 100644 > --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h > +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h > @@ -16,6 +16,10 @@ > =20 > #define SUNXI_GIC400_BASE 0x03020000 > =20 > +#ifdef CONFIG_MACH_SUN50I_A133 > +#define SUNXI_NSI_BASE 0x03100000 > +#endif > + > #ifdef CONFIG_MACH_SUN50I_H6 > #define SUNXI_DRAM_COM_BASE 0x04002000 > #define SUNXI_DRAM_CTL0_BASE 0x04003000 > diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h b/arch/ar= m/include/asm/arch-sunxi/dram_sun50i_a133.h > index a5fc6ad36560..eadec74cc2b6 100644 > --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h > +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h > @@ -24,6 +24,42 @@ static inline int ns_to_t(int nanoseconds) > return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); > } > =20 > +#define SUNXI_NSI_MODE_REG(i) ((i) * 0x200 + 0x10) > +#define SUNXI_NSI_PRI_CFG_REG(i) ((i) * 0x200 + 0x14) > +#define SUNXI_NSI_PRI_CFG_RD(v) (((v) & 0x3) << 2) > +#define SUNXI_NSI_PRI_CFG_WR(v) ((v) & 0x3) > +#define SUNXI_NSI_PRI_CFG_LOWEST 0 > +#define SUNXI_NSI_PRI_CFG_LOW 1 > +#define SUNXI_NSI_PRI_CFG_HIGH 2 > +#define SUNXI_NSI_PRI_CFG_HIGHEST 3 > +#define SUNXI_NSI_IO_CFG_REG(i) ((i) * 0x200 + 0x18) > +#define SUNXI_NSI_IO_CFG_QOS_SEL_OUTPUT 0 > +#define SUNXI_NSI_IO_CFG_QOS_SEL_INPUT 1 > +#define SUNXI_NSI_ENABLE_REG(i) ((i) * 0x200 + 0xc0) > + > +enum sunxi_nsi_port { > + SUNXI_NSI_PORT_CPU =3D 0, > + SUNXI_NSI_PORT_GPU, > + SUNXI_NSI_PORT_SD1, > + SUNXI_NSI_PORT_MSTG, > + SUNXI_NSI_PORT_GMAC0, > + SUNXI_NSI_PORT_GMAC1, > + SUNXI_NSI_PORT_USB0, > + SUNXI_NSI_PORT_USB1, > + SUNXI_NSI_PORT_NDFC, > + SUNXI_NSI_PORT_DMAC, > + SUNXI_NSI_PORT_CE, > + SUNXI_NSI_PORT_DE0, > + SUNXI_NSI_PORT_DE1, > + SUNXI_NSI_PORT_VE, > + SUNXI_NSI_PORT_CSI, > + SUNXI_NSI_PORT_ISP, > + SUNXI_NSI_PORT_G2D, > + SUNXI_NSI_PORT_EINK, > + SUNXI_NSI_PORT_IOMMU, > + SUNXI_NSI_PORT_CPUS, > +}; > + > /* MBUS part is largely the same as in H6, except for one special regist= er */ > #define MCTL_COM_UNK_008 0x008 > /* NOTE: This register has the same importance as mctl_ctl->clken in H61= 6 */ > diff --git a/arch/arm/mach-sunxi/dram_sun50i_a133.c b/arch/arm/mach-sunxi= /dram_sun50i_a133.c > index 1496f99624dd..204810aecf2a 100644 > --- a/arch/arm/mach-sunxi/dram_sun50i_a133.c > +++ b/arch/arm/mach-sunxi/dram_sun50i_a133.c > @@ -69,6 +69,66 @@ static const u8 phy_init[] =3D { > }; > #endif > =20 > +static void nsi_configure_port(unsigned int port, u8 pri, u8 qos_sel) > +{ > + void *base =3D (void *)SUNXI_NSI_BASE; > + u32 pri_cfg; > + > + /* QoS with bandwidth limits is not supported, disable it. */ > + writel(0, base + SUNXI_NSI_MODE_REG(port)); > + writel(0, base + SUNXI_NSI_ENABLE_REG(port)); > + > + /* > + * QoS direction selection should not be in use, but set it nevertheless > + * to match the BSP behavior (in case it has some other meaning). > + */ > + writel(qos_sel, base + SUNXI_NSI_IO_CFG_REG(port)); > + > + /* Port priority is always active. */ > + pri_cfg =3D SUNXI_NSI_PRI_CFG_RD(pri) | SUNXI_NSI_PRI_CFG_WR(pri); > + > + writel(pri_cfg, base + SUNXI_NSI_PRI_CFG_REG(port)); > +} > + > +#define NSI_CONF(port, pri, qos_sel) \ > + { SUNXI_NSI_PORT_ ## port, SUNXI_NSI_PRI_CFG_ ## pri, \ > + SUNXI_NSI_IO_CFG_QOS_SEL_ ## qos_sel } > + > +static void nsi_set_master_priority(void) > +{ > + struct { > + unsigned int port; > + u8 pri; > + u8 qos_sel; > + } ports[] =3D { > + NSI_CONF(CPU, LOWEST, INPUT), > + NSI_CONF(GPU, LOWEST, INPUT), > + NSI_CONF(SD1, LOWEST, OUTPUT), > + NSI_CONF(MSTG, LOWEST, OUTPUT), > + NSI_CONF(GMAC0, LOWEST, OUTPUT), > + NSI_CONF(GMAC1, LOWEST, OUTPUT), > + NSI_CONF(USB0, LOWEST, OUTPUT), > + NSI_CONF(USB1, LOWEST, OUTPUT), > + NSI_CONF(NDFC, LOWEST, OUTPUT), > + NSI_CONF(DMAC, LOWEST, OUTPUT), > + NSI_CONF(CE, LOWEST, OUTPUT), > + NSI_CONF(DE0, HIGH, INPUT), > + NSI_CONF(DE1, HIGH, INPUT), > + NSI_CONF(VE, LOWEST, INPUT), > + NSI_CONF(CSI, HIGH, INPUT), > + NSI_CONF(ISP, HIGH, INPUT), > + NSI_CONF(G2D, LOWEST, INPUT), > + NSI_CONF(EINK, LOWEST, OUTPUT), > + NSI_CONF(IOMMU, HIGHEST, INPUT), > + NSI_CONF(CPUS, LOWEST, OUTPUT), > + }; > + unsigned int i; > + > + for (i =3D 0; i < ARRAY_SIZE(ports); i++) > + nsi_configure_port(ports[i].port, ports[i].pri, > + ports[i].qos_sel); > +} > + > static void mctl_clk_init(u32 clk) > { > void * const ccm =3D (void *)SUNXI_CCM_BASE; > @@ -1184,6 +1244,7 @@ static const struct dram_para para =3D { > unsigned long sunxi_dram_init(void) > { > struct dram_config config; > + unsigned long size; > =20 > /* Writing to undocumented SYS_CFG area, according to user manual. */ > setbits_le32(0x03000160, BIT(8)); > @@ -1200,5 +1261,9 @@ unsigned long sunxi_dram_init(void) > 1U << config.bankgrps, 1U << config.ranks, > 16U << config.bus_full_width); > =20 > - return calculate_dram_size(&config); > + size =3D calculate_dram_size(&config); > + > + nsi_set_master_priority(); > + > + return size; > } >=20