From mboxrd@z Thu Jan 1 00:00:00 1970 From: Neil Armstrong Date: Sun, 29 Oct 2017 15:42:30 +0100 Subject: [U-Boot] [PATCH 2/2] odroid-c2: enable I2C In-Reply-To: <20171029090901.24299-3-b.galvani@gmail.com> References: <20171029090901.24299-1-b.galvani@gmail.com> <20171029090901.24299-3-b.galvani@gmail.com> Message-ID: <59F5E8D6.50803@baylibre.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable To: u-boot@lists.denx.de Le 29/10/2017 10:09, Beniamino Galvani a =C3=A9crit : > Signed-off-by: Beniamino Galvani > --- > arch/arm/include/asm/arch-meson/gxbb.h | 1 + > board/amlogic/odroid-c2/odroid-c2.c | 1 + > configs/odroid-c2_defconfig | 3 +++ > 3 files changed, 5 insertions(+) >=20 > diff --git a/arch/arm/include/asm/arch-meson/gxbb.h b/arch/arm/include/as= m/arch-meson/gxbb.h > index ce41349792..96c9535f53 100644 > --- a/arch/arm/include/asm/arch-meson/gxbb.h > +++ b/arch/arm/include/asm/arch-meson/gxbb.h > @@ -44,6 +44,7 @@ > #define GXBB_GCLK_MPEG_OTHER GXBB_HIU_ADDR(0x53) > #define GXBB_GCLK_MPEG_AO GXBB_HIU_ADDR(0x54) > =20 > +#define GXBB_GCLK_MPEG_0_I2C BIT(9) > #define GXBB_GCLK_MPEG_1_ETH BIT(3) > =20 > #endif /* __GXBB_H__ */ > diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c= 2/odroid-c2.c > index eac04d8178..a5ea8dc5af 100644 > --- a/board/amlogic/odroid-c2/odroid-c2.c > +++ b/board/amlogic/odroid-c2/odroid-c2.c > @@ -35,6 +35,7 @@ int misc_init_r(void) > GXBB_ETH_REG_0_CLK_EN); > =20 > /* Enable power and clock gate */ > + setbits_le32(GXBB_GCLK_MPEG_0, GXBB_GCLK_MPEG_0_I2C); Hi Beniamino, At some point, this should maybe be implemented as a (basic) clock driver t= o handle these gates. Neil > setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH); > clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK); > =20 > diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig > index f7f8016644..1afd2fc111 100644 > --- a/configs/odroid-c2_defconfig > +++ b/configs/odroid-c2_defconfig > @@ -11,12 +11,15 @@ CONFIG_DEBUG_UART=3Dy > # CONFIG_CMD_IMI is not set > # CONFIG_CMD_FPGA is not set > CONFIG_CMD_GPIO=3Dy > +CONFIG_CMD_I2C=3Dy > # CONFIG_CMD_LOADS is not set > CONFIG_CMD_MMC=3Dy > # CONFIG_CMD_SETEXPR is not set > CONFIG_OF_CONTROL=3Dy > CONFIG_NET_RANDOM_ETHADDR=3Dy > CONFIG_DM_GPIO=3Dy > +CONFIG_DM_I2C=3Dy > +CONFIG_SYS_I2C_MESON=3Dy > CONFIG_DM_MMC=3Dy > CONFIG_MMC_MESON_GX=3Dy > CONFIG_DM_ETH=3Dy >=20