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Date: Thu, 16 Feb 2023 14:20:12 +0800
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Subject: Re: [PATCH v2 16/17] riscv: dts: jh7110: Add initial StarFive
 VisionFive v2 board device tree
Content-Language: en-US
To: Sean Anderson <seanga2@gmail.com>, <u-boot@lists.denx.de>, Rick Chen
 <rick@andestech.com>, Leo <ycliang@andestech.com>, Lukasz Majewski
 <lukma@denx.de>
CC: Lee Kuan Lim <kuanlim.lee@starfivetech.com>, Jianlong Huang
 <jianlong.huang@starfivetech.com>, Emil Renner Berthing <kernel@esmil.dk>
References: <20230118081132.31403-1-yanhong.wang@starfivetech.com>
 <20230118081132.31403-17-yanhong.wang@starfivetech.com>
 <ace5e586-f536-c0e2-5fe2-30d924d3ddfa@gmail.com>
From: yanhong wang <yanhong.wang@starfivetech.com>
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On 2023/1/22 2:46, Sean Anderson wrote:
> On 1/18/23 03:11, Yanhong Wang wrote:
>> Add initial device tree for StarFive VisionFive v2 board.
>>
>> Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
>> ---
>> =C2=A0 arch/riscv/dts/Makefile=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 2 +-
>> =C2=A0 .../dts/starfive_visionfive2-u-boot.dtsi=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 |=C2=A0 84 +++++++
>> =C2=A0 arch/riscv/dts/starfive_visionfive2.dts=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0 | 234 ++++++++++++++++++
>> =C2=A0 3 files changed, 319 insertions(+), 1 deletion(-)
>> =C2=A0 create mode 100644 arch/riscv/dts/starfive_visionfive2-u-boot.d=
tsi
>> =C2=A0 create mode 100644 arch/riscv/dts/starfive_visionfive2.dts
>>
>> diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
>> index 5c15a0f303..0351cc0c38 100644
>> --- a/arch/riscv/dts/Makefile
>> +++ b/arch/riscv/dts/Makefile
>> @@ -7,7 +7,7 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) +=3D openpiton-=
riscv64.dtb
>> =C2=A0 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) +=3D hifive-unleashed-a00=
.dtb
>> =C2=A0 dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) +=3D hifive-unmatched-a00=
.dtb
>> =C2=A0 dtb-$(CONFIG_TARGET_SIPEED_MAIX) +=3D k210-maix-bit.dtb
>> -
>> +dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=3D starfive_visionfive2.d=
tb
>> =C2=A0 include $(srctree)/scripts/Makefile.dts
>> =C2=A0 =C2=A0 targets +=3D $(dtb-y)
>> diff --git a/arch/riscv/dts/starfive_visionfive2-u-boot.dtsi b/arch/ri=
scv/dts/starfive_visionfive2-u-boot.dtsi
>> new file mode 100644
>> index 0000000000..1b4e3392ab
>> --- /dev/null
>> +++ b/arch/riscv/dts/starfive_visionfive2-u-boot.dtsi
>> @@ -0,0 +1,84 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> + */
>> +
>> +#include "binman.dtsi"
>> +#include "jh7110-u-boot.dtsi"
>> +/ {
>> +=C2=A0=C2=A0=C2=A0 chosen {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 u-boot,dm-spl;
>> +=C2=A0=C2=A0=C2=A0 };
>> +
>> +=C2=A0=C2=A0=C2=A0 firmware {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 spi0 =3D &qspi;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 u-boot,dm-spl;
>> +=C2=A0=C2=A0=C2=A0 };
>> +
>> +=C2=A0=C2=A0=C2=A0 config {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 u-boot,dm-spl;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 u-boot,spl-payload-offset =
=3D <0x100000>;
>> +=C2=A0=C2=A0=C2=A0 };
>> +
>> +=C2=A0=C2=A0=C2=A0 memory@40000000 {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 u-boot,dm-spl;
>> +=C2=A0=C2=A0=C2=A0 };
>> +
>> +=C2=A0=C2=A0=C2=A0 soc {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 u-boot,dm-spl;
>> +
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dmc: dmc@15700000 {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 u-=
boot,dm-spl;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 co=
mpatible =3D "starfive,jh7110-dmc";
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 re=
g =3D <0x0 0x15700000 0x0 0x10000>,
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 <0x0 0x13000000 0x0 0x10000>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 re=
sets =3D <&syscrg JH7110_SYSRST_DDR_AXI>,
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 <&syscrg JH7110_SYSRST_DDR_OSC>,
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 <&syscrg JH7110_SYSRST_DDR_APB>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 re=
set-names =3D "axi", "osc", "apb";
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 cl=
ocks =3D <&syscrg JH7110_SYSCLK_PLL1_OUT>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 cl=
ock-names =3D "pll1";
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 cl=
ock-frequency =3D <2133>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 };
>=20
> Again, needs to go in SoC dtsi.
>=20

Thanks. I will move the dmc node to jh7110-u-boot.dtsi in the next versio=
n.

> Here are the rules for where something should go:
>=20
> - If it is part of the chip, it goes in the SoC dtsi, even if it is not=
 always
> =C2=A0 used! You can disable it by default (status =3D "disabled") if t=
his is the case.
> - If it is on the board, it goes in the board dts.
> - If it is a property which is added to a node to support a board perip=
heral,
> =C2=A0 it goes in the board dts.
> - If it is a U-Boot-specific property, it goes in the -u-boot.dts[i]
>=20
> --Sean
>=20
>> +=C2=A0=C2=A0=C2=A0 };
>> +};
>> +
>> +&sys_syscon {
>> +=C2=A0=C2=A0=C2=A0 u-boot,dm-spl;
>> +};
>> +
>> +&uart0 {
>> +=C2=A0=C2=A0=C2=A0 u-boot,dm-spl;
>> +};
>> +
>> +&sdio0 {
>> +=C2=A0=C2=A0=C2=A0 u-boot,dm-spl;
>> +};
>> +
>> +&sdio1 {
>> +=C2=A0=C2=A0=C2=A0 u-boot,dm-spl;
>> +};
>> +
>> +&qspi {
>> +=C2=A0=C2=A0=C2=A0 u-boot,dm-spl;
>> +
>> +=C2=A0=C2=A0=C2=A0 nor-flash@0 {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 u-boot,dm-spl;
>> +=C2=A0=C2=A0=C2=A0 };
>> +};
>> +
>> +&osc {
>> +=C2=A0=C2=A0=C2=A0 u-boot,dm-spl;
>> +};
>> +
>> +&aoncrg {
>> +=C2=A0=C2=A0=C2=A0 u-boot,dm-spl;
>> +};
>> +
>> +&syscrg {
>> +=C2=A0=C2=A0=C2=A0 u-boot,dm-spl;
>> +};
>> +
>> +&stgcrg {
>> +=C2=A0=C2=A0=C2=A0 u-boot,dm-spl;
>> +};
>> diff --git a/arch/riscv/dts/starfive_visionfive2.dts b/arch/riscv/dts/=
starfive_visionfive2.dts
>> new file mode 100644
>> index 0000000000..52b31546da
>> --- /dev/null
>> +++ b/arch/riscv/dts/starfive_visionfive2.dts
>> @@ -0,0 +1,234 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "jh7110.dtsi"
>> +#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
>> +/ {
>> +=C2=A0=C2=A0=C2=A0 #address-cells =3D <2>;
>> +=C2=A0=C2=A0=C2=A0 #size-cells =3D <2>;
>> +=C2=A0=C2=A0=C2=A0 model =3D "StarFive VisionFive V2";
>> +=C2=A0=C2=A0=C2=A0 compatible =3D "starfive,jh7110";
>> +
>> +=C2=A0=C2=A0=C2=A0 aliases {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 spi0 =3D &qspi;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 mmc0 =3D &sdio0;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 mmc1 =3D &sdio1;
>> +=C2=A0=C2=A0=C2=A0 };
>> +
>> +=C2=A0=C2=A0=C2=A0 chosen {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 stdout-path =3D "/soc/seri=
al@10000000:115200";
>> +=C2=A0=C2=A0=C2=A0 };
>> +
>> +=C2=A0=C2=A0=C2=A0 cpus {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 timebase-frequency =3D <40=
00000>;
>> +=C2=A0=C2=A0=C2=A0 };
>> +
>> +=C2=A0=C2=A0=C2=A0 memory@40000000 {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 device_type =3D "memory";
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 reg =3D <0x0 0x40000000 0x=
1 0x0>;
>> +=C2=A0=C2=A0=C2=A0 };
>> +
>> +=C2=A0=C2=A0=C2=A0 soc {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sys_syscon: sys_syscon@130=
30000 {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 co=
mpatible =3D "syscon";
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 re=
g =3D <0x0 0x13030000 0x0 0x1000>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 };
>> +=C2=A0=C2=A0=C2=A0 };
>=20
> ditto
>=20

I will move sys_syscon node to jh7110.dtsi

>> +};
>> +
>> +&S76_0 {
>> +=C2=A0=C2=A0=C2=A0 status =3D "okay";
>> +};
>> +
>> +&osc {
>> +=C2=A0=C2=A0=C2=A0 clock-frequency =3D <24000000>;
>> +};
>> +
>> +&clk_rtc {
>> +=C2=A0=C2=A0=C2=A0 clock-frequency =3D <32768>;
>> +};
>> +
>> +&gmac0_rmii_refin {
>> +=C2=A0=C2=A0=C2=A0 clock-frequency =3D <50000000>;
>> +};
>> +
>> +&gmac0_rgmii_rxin {
>> +=C2=A0=C2=A0=C2=A0 clock-frequency =3D <125000000>;
>> +};
>> +
>> +&gmac1_rmii_refin {
>> +=C2=A0=C2=A0=C2=A0 clock-frequency =3D <50000000>;
>> +};
>> +
>> +&gmac1_rgmii_rxin {
>> +=C2=A0=C2=A0=C2=A0 clock-frequency =3D <125000000>;
>> +};
>> +
>> +&i2stx_bclk_ext {
>> +=C2=A0=C2=A0=C2=A0 clock-frequency =3D <12288000>;
>> +};
>> +
>> +&i2stx_lrck_ext {
>> +=C2=A0=C2=A0=C2=A0 clock-frequency =3D <192000>;
>> +};
>> +
>> +&i2srx_bclk_ext {
>> +=C2=A0=C2=A0=C2=A0 clock-frequency =3D <12288000>;
>> +};
>> +
>> +&i2srx_lrck_ext {
>> +=C2=A0=C2=A0=C2=A0 clock-frequency =3D <192000>;
>> +};
>> +
>> +&tdm_ext {
>> +=C2=A0=C2=A0=C2=A0 clock-frequency =3D <49152000>;
>> +};
>> +
>> +&mclk_ext {
>> +=C2=A0=C2=A0=C2=A0 clock-frequency =3D <12288000>;
>> +};
>> +
>> +&gpio {
>> +=C2=A0=C2=A0=C2=A0 status =3D "okay";
>> +=C2=A0=C2=A0=C2=A0 uart0_pins: uart0-0 {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 tx-pins {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pi=
nmux =3D <GPIOMUX(5, GPOUT_SYS_UART0_TX,
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 GPO=
EN_ENABLE, GPI_NONE)>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bi=
as-disable;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dr=
ive-strength =3D <12>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 in=
put-disable;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 in=
put-schmitt-disable;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sl=
ew-rate =3D <0>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 };
>> +
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 rx-pins {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pi=
nmux =3D <GPIOMUX(6, GPOUT_LOW,
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 GPO=
EN_DISABLE, GPI_SYS_UART0_RX)>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bi=
as-pull-up;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dr=
ive-strength =3D <2>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 in=
put-enable;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 in=
put-schmitt-enable;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sl=
ew-rate =3D <0>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 };
>> +=C2=A0=C2=A0=C2=A0 };
>> +
>> +=C2=A0=C2=A0=C2=A0 mmc0_pins: mmc0-pins {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 mmc0-pins-rest {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pi=
nmux =3D <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 GPO=
EN_ENABLE, GPI_NONE)>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bi=
as-pull-up;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dr=
ive-strength =3D <12>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 in=
put-disable;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 in=
put-schmitt-disable;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sl=
ew-rate =3D <0>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 };
>> +=C2=A0=C2=A0=C2=A0 };
>> +
>> +=C2=A0=C2=A0=C2=A0 sdcard1_pins: sdcard1-pins {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sdcard1-pins0 {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pi=
nmux =3D <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 GPO=
EN_ENABLE, GPI_NONE)>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bi=
as-pull-up;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dr=
ive-strength =3D <12>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 in=
put-disable;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 in=
put-schmitt-disable;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sl=
ew-rate =3D <0>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 };
>> +
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sdcard1-pins1 {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pi=
nmux =3D <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 GPO=
EN_SYS_SDIO1_CMD, GPI_SYS_SDIO1_CMD)>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bi=
as-pull-up;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dr=
ive-strength =3D <12>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 in=
put-enable;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 in=
put-schmitt-enable;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sl=
ew-rate =3D <0>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 };
>> +
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sdcard1-pins2 {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pi=
nmux =3D <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 GPO=
EN_SYS_SDIO1_DATA0, GPI_SYS_SDIO1_DATA0)>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bi=
as-pull-up;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dr=
ive-strength =3D <12>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 in=
put-enable;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 in=
put-schmitt-enable;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sl=
ew-rate =3D <0>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 };
>> +
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sdcard1-pins3 {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pi=
nmux =3D <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 GPO=
EN_SYS_SDIO1_DATA1, GPI_SYS_SDIO1_DATA1)>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bi=
as-pull-up;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dr=
ive-strength =3D <12>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 in=
put-enable;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 in=
put-schmitt-enable;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sl=
ew-rate =3D <0>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 };
>> +
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sdcard1-pins4 {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pi=
nmux =3D <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 GPO=
EN_SYS_SDIO1_DATA2, GPI_SYS_SDIO1_DATA2)>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bi=
as-pull-up;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dr=
ive-strength =3D <12>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 in=
put-enable;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 in=
put-schmitt-enable;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sl=
ew-rate =3D <0>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 };
>> +
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sdcard1-pins5 {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pi=
nmux =3D <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 GPO=
EN_SYS_SDIO1_DATA3, GPI_SYS_SDIO1_DATA3)>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bi=
as-pull-up;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dr=
ive-strength =3D <12>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 in=
put-enable;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 in=
put-schmitt-enable;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sl=
ew-rate =3D <0>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 };
>> +=C2=A0=C2=A0=C2=A0 };
>> +};
>> +
>> +&sdio0 {
>> +=C2=A0=C2=A0=C2=A0 bus-width =3D <8>;
>> +=C2=A0=C2=A0=C2=A0 pinctrl-names =3D "default";
>> +=C2=A0=C2=A0=C2=A0 pinctrl-0 =3D <&mmc0_pins>;
>> +=C2=A0=C2=A0=C2=A0 status =3D "okay";
>> +};
>> +
>> +&sdio1 {
>> +=C2=A0=C2=A0=C2=A0 bus-width =3D <4>;
>> +=C2=A0=C2=A0=C2=A0 pinctrl-names =3D "default";
>> +=C2=A0=C2=A0=C2=A0 pinctrl-0 =3D <&sdcard1_pins>;
>> +=C2=A0=C2=A0=C2=A0 status =3D "okay";
>> +};
>> +
>> +&uart0 {
>> +=C2=A0=C2=A0=C2=A0 reg-offset =3D <0>;
>> +=C2=A0=C2=A0=C2=A0 current-speed =3D <115200>;
>> +=C2=A0=C2=A0=C2=A0 clock-frequency =3D <24000000>;
>> +=C2=A0=C2=A0=C2=A0 pinctrl-names =3D "default";
>> +=C2=A0=C2=A0=C2=A0 pinctrl-0 =3D <&uart0_pins>;
>> +=C2=A0=C2=A0=C2=A0 status =3D "okay";
>> +};
>> +
>> +&qspi {
>> +=C2=A0=C2=A0=C2=A0 spi-max-frequency =3D <250000000>;
>> +=C2=A0=C2=A0=C2=A0 status =3D "okay";
>> +
>> +=C2=A0=C2=A0=C2=A0 nor-flash@0 {
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 compatible =3D "jedec,spi-=
nor";
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 reg=3D<0>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 spi-max-frequency =3D <100=
000000>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 cdns,tshsl-ns =3D <1>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 cdns,tsd2d-ns =3D <1>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 cdns,tchsh-ns =3D <1>;
>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 cdns,tslch-ns =3D <1>;
>> +=C2=A0=C2=A0=C2=A0 };
>> +};
>> +
>> +&syscrg {
>> +=C2=A0=C2=A0=C2=A0 starfive,sys-syscon =3D <&sys_syscon>;
>> +};
>=20
> ditto

I will move it to jh7110.dtsi