From mboxrd@z Thu Jan 1 00:00:00 1970 From: Frank Mori Hess Date: Sun, 03 Dec 2017 10:36:41 -0500 Subject: [U-Boot] arm socfpga: Revert "spi: cadence_qspi_apb: Support 32 bit AHB address" Message-ID: <5a241c93.4d2bc80a.49dc7.267d@mx.google.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de This reverts commit dac3bf20fb2c9b03476be0d73db620f62ab3cee1. Signed-off-by: Frank Mori Hess --- drivers/spi/cadence_qspi_apb.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index e02f2217f4..b300f36607 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -47,6 +47,7 @@ #define CQSPI_INST_TYPE_QUAD 2 #define CQSPI_STIG_DATA_LEN_MAX 8 +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK 0xFFFFF #define CQSPI_DUMMY_CLKS_PER_BYTE 8 #define CQSPI_DUMMY_BYTES_MAX 4 @@ -560,7 +561,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, addr_bytes = cmdlen - 1; /* Setup the indirect trigger address */ - writel((u32)plat->ahbbase, + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Configure the opcode */ @@ -710,7 +711,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, return -EINVAL; } /* Setup the indirect trigger address */ - writel((u32)plat->ahbbase, + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Configure the opcode */ -- 2.11.0