From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 791B9C6FD1C for ; Wed, 22 Mar 2023 22:05:00 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E814A85958; Wed, 22 Mar 2023 23:04:56 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="AHfEsvVU"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id DAAD685958; Wed, 22 Mar 2023 23:04:54 +0100 (CET) Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E5E0085D2F for ; Wed, 22 Mar 2023 23:04:51 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=conor@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 7D879B81E2A; Wed, 22 Mar 2023 22:04:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5CEE6C4339B; Wed, 22 Mar 2023 22:04:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1679522690; bh=/owhVXCsYm/UWKZZcKbjVEoILRGgE8cqMB+2kr7xHSY=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=AHfEsvVUhozviG0/edG4erM2jPXvsT+njJoCqU7Q8Ym5/Xztr/celiJYcyOZPHV4x rNMjzIkYFz2qs5cNLxBn3zoiGrU7KAOHeYTWb4z29/6D3/frKA6F3wfcwTPLYqimvj I8q2t6FBrlYFjO9/PSqXPOdUWr/J9u2IRC/77TK37oiacjnycQqUJDK4EQUyMNqORv MqDOLNitOW0OZH5At+HnnC/8sFBt0qGfM1O4WO/qXraqdupB+v8aMAPuN2Vy9UrzEg iXVptfe9/9AujD5Ab18vFYm3oc5aWsdQK89ToM4yRSBjSJEdqd4ZyBcQ6s9RcnWax3 GUV1rA2aUxfFA== Date: Wed, 22 Mar 2023 22:04:45 +0000 From: Conor Dooley To: Yanhong Wang Cc: u-boot@lists.denx.de, Rick Chen , Leo , Lukasz Majewski , Sean Anderson , Lee Kuan Lim , Jianlong Huang , Emil Renner Berthing Subject: Re: [PATCH v4 14/17] riscv: dts: jh7110: Add initial StarFive JH7110 device tree Message-ID: <5acdbf06-e03a-4236-9c23-63c473afea7b@spud> References: <20230316025332.3297-1-yanhong.wang@starfivetech.com> <20230316025332.3297-15-yanhong.wang@starfivetech.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="qJdRxWFdtsTfuofv" Content-Disposition: inline In-Reply-To: <20230316025332.3297-15-yanhong.wang@starfivetech.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean --qJdRxWFdtsTfuofv Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Mar 16, 2023 at 10:53:29AM +0800, Yanhong Wang wrote: > Add initial device tree for the JH7110 RISC-V SoC. >=20 > Signed-off-by: Yanhong Wang > Tested-by: Conor Dooley > + S7_0: cpu@0 { > + compatible =3D "sifive,s7", "riscv"; > + reg =3D <0>; > + d-cache-block-size =3D <64>; > + d-cache-sets =3D <64>; > + d-cache-size =3D <8192>; > + d-tlb-sets =3D <1>; > + d-tlb-size =3D <40>; > + device_type =3D "cpu"; > + i-cache-block-size =3D <64>; > + i-cache-sets =3D <64>; > + i-cache-size =3D <16384>; > + i-tlb-sets =3D <1>; > + i-tlb-size =3D <40>; > + mmu-type =3D "riscv,sv39"; Copy-pasting from my identical post on linux-riscv: Jess pointed out on IRC that this S7 entry looks wrong as it is claiming that the S7 has an mmu. I didn't go looking back in the history of u74-mc core complex manuals, but the latest version does not show an mmu for the S7. Cheers, Conor. > + next-level-cache =3D <&ccache>; > + riscv,isa =3D "rv64imac_zba_zbb"; > + tlb-split; > + status =3D "disabled"; > + > + cpu0_intc: interrupt-controller { > + compatible =3D "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells =3D <1>; > + }; > + }; --qJdRxWFdtsTfuofv Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZBt7fQAKCRB4tDGHoIJi 0p0KAP9AppdvU1cjCTtBGfrzzBv+u/phlIEMVfugPaGYUH/l1wEAhlGnALid+Efa EIppGkmscqvL17DOH9289fSm5fE0Ag4= =0y+Z -----END PGP SIGNATURE----- --qJdRxWFdtsTfuofv--